* [PATCH 1/6] drm/i915/cnp: Introduce Cannonpoint PCH.
2017-05-08 23:44 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
@ 2017-05-08 23:44 ` Anusha Srivatsa
2017-05-08 23:45 ` [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Anusha Srivatsa
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2017-05-08 23:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Most of south engine display that is in PCH is still the
same as SPT and KBP, except for this key differences:
- Backlight: Backlight programming changed in CNP PCH.
- Panel Power: Sligh programming changed in CNP PCH.
- GMBUS and GPIO: The pin mapping has changed in CNP PCH.
All of these changes follow more the BXT style.
v2: Update definition to use dev_priv isntead of dev (Tvrtko).
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 72fb47a..23d6a5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -216,6 +216,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
+ } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
+ dev_priv->pch_type = PCH_CNP;
+ DRM_DEBUG_KMS("Found CannonPoint PCH\n");
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
(id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b20ed16..ab0c870 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1211,6 +1211,7 @@ enum intel_pch {
PCH_LPT, /* Lynxpoint PCH */
PCH_SPT, /* Sunrisepoint PCH */
PCH_KBP, /* Kabypoint PCH */
+ PCH_CNP, /* Cannonpoint PCH */
PCH_NOP,
};
@@ -2944,11 +2945,13 @@ intel_info(const struct drm_i915_private *dev_priv)
#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
+#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
+#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c99f51c..625e965 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2582,7 +2582,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
I915_WRITE(SDEIIR, iir);
ret = IRQ_HANDLED;
- if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
+ if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
+ HAS_PCH_CNP(dev_priv))
spt_irq_handler(dev_priv, iir);
else
cpt_irq_handler(dev_priv, iir);
@@ -4323,7 +4324,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->disable_vblank = gen8_disable_vblank;
if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
- else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
+ else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
+ HAS_PCH_CNP(dev_priv))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
else
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
2017-05-08 23:44 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
2017-05-08 23:44 ` [PATCH 1/6] drm/i915/cnp: Introduce Cannonpoint PCH Anusha Srivatsa
@ 2017-05-08 23:45 ` Anusha Srivatsa
2017-05-08 23:45 ` [PATCH 3/6] drm/i915/cnp: Get/set proper Raw clock frequency on CNP Anusha Srivatsa
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2017-05-08 23:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
The first two bytes of PCI ID for CNP_LP PCH are the same as that of
SPT_LP. We should really be looking at the first 9 bits instead of the
first 8 to identify platforms, although this seems to have not caused any
problems on earlier platforms. Introduce a 9 bit extended mask for SPT and
CNP while not touching the code for any of the other platforms.
v2: (Rodrigo) Make platform agnostic and fix commit message.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 8 +++++++-
drivers/gpu/drm/i915/i915_drv.h | 4 ++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 23d6a5b..3698968 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -170,6 +170,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
+ unsigned short id_ext = pch->device &
+ INTEL_PCH_DEVICE_ID_MASK_EXT;
+
dev_priv->pch_id = id;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
@@ -206,7 +209,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
- } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
+ } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
@@ -219,6 +222,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+ } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
+ dev_priv->pch_type = PCH_CNP;
+ DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
(id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ab0c870..ed9764a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2937,6 +2937,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
+#define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
@@ -2946,12 +2947,15 @@ intel_info(const struct drm_i915_private *dev_priv)
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
+#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
+#define HAS_PCH_CNP_LP(dev_priv) \
+ ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/6] drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
2017-05-08 23:44 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
2017-05-08 23:44 ` [PATCH 1/6] drm/i915/cnp: Introduce Cannonpoint PCH Anusha Srivatsa
2017-05-08 23:45 ` [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Anusha Srivatsa
@ 2017-05-08 23:45 ` Anusha Srivatsa
2017-05-08 23:45 ` [PATCH 4/6] drm/i915/cnp: Backlight support for CNP Anusha Srivatsa
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2017-05-08 23:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
RAWCLK_FREQ register has changed for platforms with CNP+.
[29:26] This field provides the denominator for the fractional
part of the microsecond counter divider. The numerator
is fixed at 1. Program this field to the denominator of
the fractional portion of reference frequency minus one.
If the fraction is 0, program to 0.
0100b = Fraction .2 MHz = Fraction 1/5.
0000b = Fraction .0 MHz.
[25:16] This field provides the integer part of the microsecond
counter divider. Program this field to the integer portion
of the reference frequenct minus one.
Also this register tells us that proper raw clock should be read
from SFUSE_STRAP and programmed to this register. Up to this point
on other platforms we are reading instead of programming it so
probably relying on whatever BIOS had configured here.
Now on let's follow the spec and also program this register
fetching the right value from SFUSE_STRAP as Spec tells us to do.
v2: Read from SFUSE_STRAP and Program RAWCLK_FREQ instead of
reading the value relying someone else will program that
for us.
v3: Add missing else. (Jani)
v4: Addressing all Ville's catches:
Use macro for shift bits instead of defining shift.
Remove shift from the cleaning bits with mask that already
has it.
Add missing I915_WRITE to actually write the reg.
Stop using useless DIV_ROUND_* on divider that is exact
dividion and use DIV_ROUND_CLOSEST for the fraction part.
v5: Remove useless Read-Modify-Write on raclk_freq reg. (Ville).
v6: Change is per PCH instead of per platform.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_cdclk.c | 29 ++++++++++++++++++++++++++++-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 524fdfd..9310d43 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6838,6 +6838,10 @@ enum {
#define FDL_TP2_TIMER_SHIFT 10
#define FDL_TP2_TIMER_MASK (3<<10)
#define RAWCLK_FREQ_MASK 0x3ff
+#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
+#define CNP_RAWCLK_DIV(div) ((div) << 16)
+#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
+#define CNP_RAWCLK_FRAC(frac) ((frac) << 26)
#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
@@ -8148,6 +8152,7 @@ enum {
/* SFUSE_STRAP */
#define SFUSE_STRAP _MMIO(0xc2014)
#define SFUSE_STRAP_FUSE_LOCK (1<<13)
+#define SFUSE_STRAP_RAW_FREQUENCY (1<<8)
#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
#define SFUSE_STRAP_CRT_DISABLED (1<<6)
#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 2979297..634c89f 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1780,6 +1780,30 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
}
+static int cnp_rawclk(struct drm_i915_private *dev_priv)
+{
+ u32 rawclk;
+ int divider, fraction;
+
+ if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
+ /* 24 MHz */
+ divider = 24000;
+ fraction = 0;
+ } else {
+ /* 19.2 MHz */
+ divider = 19000;
+ fraction = 200;
+ }
+
+ rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
+ if (fraction)
+ rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
+ fraction) - 1);
+
+ I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
+ return divider + fraction;
+}
+
static int pch_rawclk(struct drm_i915_private *dev_priv)
{
return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
@@ -1827,7 +1851,10 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
*/
void intel_update_rawclk(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+
+ if (HAS_PCH_CNP(dev_priv))
+ dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
dev_priv->rawclk_freq = pch_rawclk(dev_priv);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/6] drm/i915/cnp: Backlight support for CNP.
2017-05-08 23:44 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
` (2 preceding siblings ...)
2017-05-08 23:45 ` [PATCH 3/6] drm/i915/cnp: Get/set proper Raw clock frequency on CNP Anusha Srivatsa
@ 2017-05-08 23:45 ` Anusha Srivatsa
2017-05-09 0:10 ` Pandiyan, Dhinakaran
2017-05-08 23:45 ` [PATCH 5/6] drm/i915/cnp: add CNP gmbus support Anusha Srivatsa
` (2 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Anusha Srivatsa @ 2017-05-08 23:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Split out BXT and CNP's setup_backlight(),enable_backlight(),
disable_backlight() and hz_to_pwm() into
two separate functions instead of reusing BXT function.
Reuse set_backlight() and get_backlight() since they have
no reference to the utility pin.
v2: Reuse BXT functions with controller 0 instead of
redefining it. (Jani).
Use dev_priv->rawclk_freq instead of getting the value
from SFUSE_STRAP.
v3: Avoid setup backligh controller along with hooks and
fully reuse hooks setup as suggested by Jani.
v4: Clean up commit message.
v5: Implement per PCH instead per platform.
v6: Introduce a new function for CNP.(Jani and Ville)
v7: Squash the all CNP Backlight support patches into a
single patch. (Jani)
v8: Correct indentation, remove unneeded blank lines and
correct mail address (Jani).
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_panel.c | 94 ++++++++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index cb50c52..22da1e2 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct intel_connector *connector)
}
}
+static void cnp_disable_backlight(struct intel_connector *connector)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_panel *panel = &connector->panel;
+ u32 tmp;
+
+ intel_panel_actually_set_backlight(connector, 0);
+
+ tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ tmp & ~BXT_BLC_PWM_ENABLE);
+}
+
static void pwm_disable_backlight(struct intel_connector *connector)
{
struct intel_panel *panel = &connector->panel;
@@ -1076,6 +1089,36 @@ static void bxt_enable_backlight(struct intel_connector *connector)
pwm_ctl | BXT_BLC_PWM_ENABLE);
}
+static void cnp_enable_backlight(struct intel_connector *connector)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_panel *panel = &connector->panel;
+ enum pipe pipe = intel_get_pipe_from_connector(connector);
+ u32 pwm_ctl;
+
+ pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
+ DRM_DEBUG_KMS("backlight already enabled\n");
+ pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ pwm_ctl);
+ }
+
+ I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+ panel->backlight.max);
+
+ intel_panel_actually_set_backlight(connector, panel->backlight.level);
+
+ pwm_ctl = 0;
+ if (panel->backlight.active_low_pwm)
+ pwm_ctl |= BXT_BLC_PWM_POLARITY;
+
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
+ POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ pwm_ctl | BXT_BLC_PWM_ENABLE);
+}
+
static void pwm_enable_backlight(struct intel_connector *connector)
{
struct intel_panel *panel = &connector->panel;
@@ -1239,6 +1282,18 @@ void intel_backlight_device_unregister(struct intel_connector *connector)
#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
/*
+ * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
+ * Value is found in SFUSE_STRAP.
+ * PWM increment = 1
+ */
+static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+
+ return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
+}
+
+/*
* BXT: PWM clock frequency = 19.2 MHz.
*/
static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
@@ -1633,6 +1688,37 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
return 0;
}
+static int
+cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_panel *panel = &connector->panel;
+ u32 pwm_ctl, val;
+
+ panel->backlight.controller = dev_priv->vbt.backlight.controller;
+
+ pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+
+ panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+ panel->backlight.max =
+ I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
+
+ if (!panel->backlight.max)
+ panel->backlight.max = get_backlight_max_vbt(connector);
+
+ if (!panel->backlight.max)
+ return -ENODEV;
+
+ val = bxt_get_backlight(connector);
+ val = intel_panel_compute_brightness(connector, val);
+ panel->backlight.level = clamp(val, panel->backlight.min,
+ panel->backlight.max);
+
+ panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
+
+ return 0;
+}
+
static int pwm_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
@@ -1749,6 +1835,14 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
panel->backlight.set = bxt_set_backlight;
panel->backlight.get = bxt_get_backlight;
panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
+ panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
+ } else if (HAS_PCH_CNP(dev_priv)) {
+ panel->backlight.setup = cnp_setup_backlight;
+ panel->backlight.enable = cnp_enable_backlight;
+ panel->backlight.disable = cnp_disable_backlight;
+ panel->backlight.set = bxt_set_backlight;
+ panel->backlight.get = bxt_get_backlight;
+ panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
HAS_PCH_KBP(dev_priv)) {
panel->backlight.setup = lpt_setup_backlight;
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 4/6] drm/i915/cnp: Backlight support for CNP.
2017-05-08 23:45 ` [PATCH 4/6] drm/i915/cnp: Backlight support for CNP Anusha Srivatsa
@ 2017-05-09 0:10 ` Pandiyan, Dhinakaran
2017-05-09 0:11 ` Srivatsa, Anusha
0 siblings, 1 reply; 10+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-05-09 0:10 UTC (permalink / raw)
To: Srivatsa, Anusha
Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org, Vivi, Rodrigo
On Mon, 2017-05-08 at 16:45 -0700, Anusha Srivatsa wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Split out BXT and CNP's setup_backlight(),enable_backlight(),
> disable_backlight() and hz_to_pwm() into
> two separate functions instead of reusing BXT function.
>
> Reuse set_backlight() and get_backlight() since they have
> no reference to the utility pin.
>
> v2: Reuse BXT functions with controller 0 instead of
> redefining it. (Jani).
> Use dev_priv->rawclk_freq instead of getting the value
> from SFUSE_STRAP.
> v3: Avoid setup backligh controller along with hooks and
> fully reuse hooks setup as suggested by Jani.
> v4: Clean up commit message.
> v5: Implement per PCH instead per platform.
>
> v6: Introduce a new function for CNP.(Jani and Ville)
>
> v7: Squash the all CNP Backlight support patches into a
> single patch. (Jani)
>
> v8: Correct indentation, remove unneeded blank lines and
> correct mail address (Jani).
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_panel.c | 94 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index cb50c52..22da1e2 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct intel_connector *connector)
> }
> }
>
> +static void cnp_disable_backlight(struct intel_connector *connector)
> +{
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct intel_panel *panel = &connector->panel;
> + u32 tmp;
> +
> + intel_panel_actually_set_backlight(connector, 0);
> +
> + tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + tmp & ~BXT_BLC_PWM_ENABLE);
> +}
> +
> static void pwm_disable_backlight(struct intel_connector *connector)
> {
> struct intel_panel *panel = &connector->panel;
> @@ -1076,6 +1089,36 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> pwm_ctl | BXT_BLC_PWM_ENABLE);
> }
>
> +static void cnp_enable_backlight(struct intel_connector *connector)
> +{
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct intel_panel *panel = &connector->panel;
> + enum pipe pipe = intel_get_pipe_from_connector(connector);
> + u32 pwm_ctl;
> +
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
> + DRM_DEBUG_KMS("backlight already enabled\n");
> + pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl);
> + }
> +
> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> + panel->backlight.max);
> +
> + intel_panel_actually_set_backlight(connector, panel->backlight.level);
> +
> + pwm_ctl = 0;
> + if (panel->backlight.active_low_pwm)
> + pwm_ctl |= BXT_BLC_PWM_POLARITY;
> +
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> + POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> + pwm_ctl | BXT_BLC_PWM_ENABLE);
> +}
> +
> static void pwm_enable_backlight(struct intel_connector *connector)
> {
> struct intel_panel *panel = &connector->panel;
> @@ -1239,6 +1282,18 @@ void intel_backlight_device_unregister(struct intel_connector *connector)
> #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
>
> /*
> + * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
> + * Value is found in SFUSE_STRAP.
> + * PWM increment = 1
> + */
> +static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> +{
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> +
> + return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
> +}
> +
> +/*
> * BXT: PWM clock frequency = 19.2 MHz.
> */
> static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> @@ -1633,6 +1688,37 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
> return 0;
> }
>
> +static int
> +cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
> +{
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct intel_panel *panel = &connector->panel;
> + u32 pwm_ctl, val;
> +
> + panel->backlight.controller = dev_priv->vbt.backlight.controller;
> +
> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +
> + panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> + panel->backlight.max =
> + I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
> +
> + if (!panel->backlight.max)
> + panel->backlight.max = get_backlight_max_vbt(connector);
> +
> + if (!panel->backlight.max)
> + return -ENODEV;
> +
> + val = bxt_get_backlight(connector);
> + val = intel_panel_compute_brightness(connector, val);
> + panel->backlight.level = clamp(val, panel->backlight.min,
> + panel->backlight.max);
> +
> + panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
> +
> + return 0;
> +}
> +
> static int pwm_setup_backlight(struct intel_connector *connector,
> enum pipe pipe)
> {
> @@ -1749,6 +1835,14 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
> panel->backlight.set = bxt_set_backlight;
> panel->backlight.get = bxt_get_backlight;
> panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> + panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
This diff should not be here.
-DK
> + } else if (HAS_PCH_CNP(dev_priv)) {
> + panel->backlight.setup = cnp_setup_backlight;
> + panel->backlight.enable = cnp_enable_backlight;
> + panel->backlight.disable = cnp_disable_backlight;
> + panel->backlight.set = bxt_set_backlight;
> + panel->backlight.get = bxt_get_backlight;
> + panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
> } else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
> HAS_PCH_KBP(dev_priv)) {
> panel->backlight.setup = lpt_setup_backlight;
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 4/6] drm/i915/cnp: Backlight support for CNP.
2017-05-09 0:10 ` Pandiyan, Dhinakaran
@ 2017-05-09 0:11 ` Srivatsa, Anusha
0 siblings, 0 replies; 10+ messages in thread
From: Srivatsa, Anusha @ 2017-05-09 0:11 UTC (permalink / raw)
To: Pandiyan, Dhinakaran
Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org, Vivi, Rodrigo
>-----Original Message-----
>From: Pandiyan, Dhinakaran
>Sent: Monday, May 8, 2017 5:10 PM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>Nikula, Jani <jani.nikula@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915/cnp: Backlight support for CNP.
>
>On Mon, 2017-05-08 at 16:45 -0700, Anusha Srivatsa wrote:
>> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> Split out BXT and CNP's setup_backlight(),enable_backlight(),
>> disable_backlight() and hz_to_pwm() into two separate functions
>> instead of reusing BXT function.
>>
>> Reuse set_backlight() and get_backlight() since they have no reference
>> to the utility pin.
>>
>> v2: Reuse BXT functions with controller 0 instead of
>> redefining it. (Jani).
>> Use dev_priv->rawclk_freq instead of getting the value
>> from SFUSE_STRAP.
>> v3: Avoid setup backligh controller along with hooks and
>> fully reuse hooks setup as suggested by Jani.
>> v4: Clean up commit message.
>> v5: Implement per PCH instead per platform.
>>
>> v6: Introduce a new function for CNP.(Jani and Ville)
>>
>> v7: Squash the all CNP Backlight support patches into a single patch.
>> (Jani)
>>
>> v8: Correct indentation, remove unneeded blank lines and correct mail
>> address (Jani).
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> Suggested-by: Jani Nikula <jani.nikula@intel.com>
>> Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_panel.c | 94
>> ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 94 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_panel.c
>> b/drivers/gpu/drm/i915/intel_panel.c
>> index cb50c52..22da1e2 100644
>> --- a/drivers/gpu/drm/i915/intel_panel.c
>> +++ b/drivers/gpu/drm/i915/intel_panel.c
>> @@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct
>intel_connector *connector)
>> }
>> }
>>
>> +static void cnp_disable_backlight(struct intel_connector *connector)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> + struct intel_panel *panel = &connector->panel;
>> + u32 tmp;
>> +
>> + intel_panel_actually_set_backlight(connector, 0);
>> +
>> + tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
>> + tmp & ~BXT_BLC_PWM_ENABLE);
>> +}
>> +
>> static void pwm_disable_backlight(struct intel_connector *connector)
>> {
>> struct intel_panel *panel = &connector->panel; @@ -1076,6 +1089,36
>> @@ static void bxt_enable_backlight(struct intel_connector *connector)
>> pwm_ctl | BXT_BLC_PWM_ENABLE);
>> }
>>
>> +static void cnp_enable_backlight(struct intel_connector *connector) {
>> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> + struct intel_panel *panel = &connector->panel;
>> + enum pipe pipe = intel_get_pipe_from_connector(connector);
>> + u32 pwm_ctl;
>> +
>> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>> + if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
>> + DRM_DEBUG_KMS("backlight already enabled\n");
>> + pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
>> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
>> + pwm_ctl);
>> + }
>> +
>> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
>> + panel->backlight.max);
>> +
>> + intel_panel_actually_set_backlight(connector,
>> +panel->backlight.level);
>> +
>> + pwm_ctl = 0;
>> + if (panel->backlight.active_low_pwm)
>> + pwm_ctl |= BXT_BLC_PWM_POLARITY;
>> +
>> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
>> + POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>> + I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
>> + pwm_ctl | BXT_BLC_PWM_ENABLE);
>> +}
>> +
>> static void pwm_enable_backlight(struct intel_connector *connector)
>> {
>> struct intel_panel *panel = &connector->panel; @@ -1239,6 +1282,18
>> @@ void intel_backlight_device_unregister(struct intel_connector
>> *connector) #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
>>
>> /*
>> + * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
>> + * Value is found in SFUSE_STRAP.
>> + * PWM increment = 1
>> + */
>> +static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32
>> +pwm_freq_hz) {
>> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> +
>> + return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq),
>pwm_freq_hz); }
>> +
>> +/*
>> * BXT: PWM clock frequency = 19.2 MHz.
>> */
>> static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32
>> pwm_freq_hz) @@ -1633,6 +1688,37 @@ bxt_setup_backlight(struct
>intel_connector *connector, enum pipe unused)
>> return 0;
>> }
>>
>> +static int
>> +cnp_setup_backlight(struct intel_connector *connector, enum pipe
>> +unused) {
>> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> + struct intel_panel *panel = &connector->panel;
>> + u32 pwm_ctl, val;
>> +
>> + panel->backlight.controller = dev_priv->vbt.backlight.controller;
>> +
>> + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>> +
>> + panel->backlight.active_low_pwm = pwm_ctl &
>BXT_BLC_PWM_POLARITY;
>> + panel->backlight.max =
>> + I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
>> +
>> + if (!panel->backlight.max)
>> + panel->backlight.max = get_backlight_max_vbt(connector);
>> +
>> + if (!panel->backlight.max)
>> + return -ENODEV;
>> +
>> + val = bxt_get_backlight(connector);
>> + val = intel_panel_compute_brightness(connector, val);
>> + panel->backlight.level = clamp(val, panel->backlight.min,
>> + panel->backlight.max);
>> +
>> + panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
>> +
>> + return 0;
>> +}
>> +
>> static int pwm_setup_backlight(struct intel_connector *connector,
>> enum pipe pipe)
>> {
>> @@ -1749,6 +1835,14 @@ intel_panel_init_backlight_funcs(struct intel_panel
>*panel)
>> panel->backlight.set = bxt_set_backlight;
>> panel->backlight.get = bxt_get_backlight;
>> panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
>> + panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
>
>This diff should not be here.
Ah! Nice catch... Will rebase again and send.
Thanks a lot.
Anusha
>-DK
>
>
>> + } else if (HAS_PCH_CNP(dev_priv)) {
>> + panel->backlight.setup = cnp_setup_backlight;
>> + panel->backlight.enable = cnp_enable_backlight;
>> + panel->backlight.disable = cnp_disable_backlight;
>> + panel->backlight.set = bxt_set_backlight;
>> + panel->backlight.get = bxt_get_backlight;
>> + panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
>> } else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
>> HAS_PCH_KBP(dev_priv)) {
>> panel->backlight.setup = lpt_setup_backlight;
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 5/6] drm/i915/cnp: add CNP gmbus support
2017-05-08 23:44 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
` (3 preceding siblings ...)
2017-05-08 23:45 ` [PATCH 4/6] drm/i915/cnp: Backlight support for CNP Anusha Srivatsa
@ 2017-05-08 23:45 ` Anusha Srivatsa
2017-05-08 23:45 ` [PATCH 6/6] drm/i915/cnp: Panel Power sequence changes for CNP PCH Anusha Srivatsa
2017-05-09 6:46 ` ✗ Fi.CI.BAT: failure for Cannonpoint Enabling Patches Patchwork
6 siblings, 0 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2017-05-08 23:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Daniel Vetter, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.
v2: Don't drop "_BXT" as the indicator of the first platform
supporting this pin numbers. Suggested by Daniel.
v3: Add missing else and fix register table since CNP GPIO_CTL
starts on 0xC5014.
v4: Fix pin number and map according to the current available VBT.
Re-add pin 4 for port D. Lost during some rebase.
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 8 +++++---
drivers/gpu/drm/i915/intel_i2c.c | 20 ++++++++++++++++++--
3 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9310d43..18fc7d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2626,9 +2626,10 @@ enum skl_disp_power_wells {
#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
#define GMBUS_PIN_DPD 6 /* HDMID */
#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
-#define GMBUS_PIN_1_BXT 1
+#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
#define GMBUS_PIN_2_BXT 2
#define GMBUS_PIN_3_BXT 3
+#define GMBUS_PIN_4_CNP 4
#define GMBUS_NUM_PINS 7 /* including 0 */
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
#define GMBUS_SW_CLR_INT (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 58d6903..2789681 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1885,19 +1885,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
switch (port) {
case PORT_B:
- if (IS_GEN9_LP(dev_priv))
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_1_BXT;
else
ddc_pin = GMBUS_PIN_DPB;
break;
case PORT_C:
- if (IS_GEN9_LP(dev_priv))
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_2_BXT;
else
ddc_pin = GMBUS_PIN_DPC;
break;
case PORT_D:
- if (IS_CHERRYVIEW(dev_priv))
+ if (HAS_PCH_CNP(dev_priv))
+ ddc_pin = GMBUS_PIN_4_CNP;
+ else if (IS_CHERRYVIEW(dev_priv))
ddc_pin = GMBUS_PIN_DPD_CHV;
else
ddc_pin = GMBUS_PIN_DPD;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b6401e8..3eb4a91 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -68,11 +68,25 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
};
+/*
+ * FIXME: Spec maps 3-misc-0xc541c and 4-portd-0xc5420.
+ * However, current available pre-prod VBT maps:
+ * portD to pin 3 using 0xc5420.
+ */
+static const struct gmbus_pin gmbus_pins_cnp[] = {
+ [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "misc", GPIOE },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOD },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (IS_GEN9_LP(dev_priv))
+ if (HAS_PCH_CNP(dev_priv))
+ return &gmbus_pins_cnp[pin];
+ else if (IS_GEN9_LP(dev_priv))
return &gmbus_pins_bxt[pin];
else if (IS_GEN9_BC(dev_priv))
return &gmbus_pins_skl[pin];
@@ -87,7 +101,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (IS_GEN9_LP(dev_priv))
+ if (HAS_PCH_CNP(dev_priv))
+ size = ARRAY_SIZE(gmbus_pins_cnp);
+ else if (IS_GEN9_LP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt);
else if (IS_GEN9_BC(dev_priv))
size = ARRAY_SIZE(gmbus_pins_skl);
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 6/6] drm/i915/cnp: Panel Power sequence changes for CNP PCH.
2017-05-08 23:44 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
` (4 preceding siblings ...)
2017-05-08 23:45 ` [PATCH 5/6] drm/i915/cnp: add CNP gmbus support Anusha Srivatsa
@ 2017-05-08 23:45 ` Anusha Srivatsa
2017-05-09 6:46 ` ✗ Fi.CI.BAT: failure for Cannonpoint Enabling Patches Patchwork
6 siblings, 0 replies; 10+ messages in thread
From: Anusha Srivatsa @ 2017-05-08 23:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
As for BXT, PP_DIVISOR was removed from CNP PCH and power
cycle delay has been moved to PP_CONTROL.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 08834f7..6563e93 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
- if (!IS_GEN9_LP(dev_priv))
+ if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
regs->pp_div = PP_DIVISOR(pps_idx);
}
@@ -5217,7 +5217,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
- if (!IS_GEN9_LP(dev_priv)) {
+ if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
@@ -5235,7 +5235,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
- if (IS_GEN9_LP(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT;
if (tmp > 0)
@@ -5392,7 +5392,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
- if (IS_GEN9_LP(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5426,7 +5426,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
- IS_GEN9_LP(dev_priv) ?
+ (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
I915_READ(regs.pp_div));
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* ✗ Fi.CI.BAT: failure for Cannonpoint Enabling Patches
2017-05-08 23:44 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
` (5 preceding siblings ...)
2017-05-08 23:45 ` [PATCH 6/6] drm/i915/cnp: Panel Power sequence changes for CNP PCH Anusha Srivatsa
@ 2017-05-09 6:46 ` Patchwork
6 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-05-09 6:46 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: Cannonpoint Enabling Patches
URL : https://patchwork.freedesktop.org/series/24151/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
CHK kernel/config_data.h
CC [M] drivers/gpu/drm/i915/intel_panel.o
drivers/gpu/drm/i915/intel_panel.c: In function ‘cnp_enable_backlight’:
drivers/gpu/drm/i915/intel_panel.c:1096:12: error: unused variable ‘pipe’ [-Werror=unused-variable]
enum pipe pipe = intel_get_pipe_from_connector(connector);
^
cc1: all warnings being treated as errors
scripts/Makefile.build:294: recipe for target 'drivers/gpu/drm/i915/intel_panel.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_panel.o] Error 1
scripts/Makefile.build:553: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:553: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:553: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1002: recipe for target 'drivers' failed
make: *** [drivers] Error 2
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^ permalink raw reply [flat|nested] 10+ messages in thread