Re: [PATCH 10/22] drm/i915/icl: Wa_1406680159

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Wed, May 02, 2018 at 01:34:09PM -0700, Oscar Mateo wrote:
> Disable GWL clock gating to prevent two different issues that
> might cause hangs.
> 
> Please notice that one of the issues is pre-production only.
> 
> v2: Rebased on top of the WA refactoring
> v3: Wa_2201832410 officially merged with Wa_1406680159
> v4: Added References (Mika)
> 
> References: HSDES#1406680159

Probably worth to mention HSDES 1406681710
where WA is better described.

> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 38e3776..ffb0e30 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -745,6 +745,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
>  			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
>  			    MSCUNIT_CLKGATE_DIS));
> +
> +	/* Wa_1406680159:icl */
> +	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
> +		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
> +		    GWUNIT_CLKGATE_DIS));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
> 
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