Re: [PATCH 11/22] drm/i915/icl: Wa_1604302699

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Disable I2M Write for performance reasons.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1604302699
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
>  drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b7e5ca0..f6a38fd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7227,7 +7227,9 @@ enum {
>  #define GEN7_L3CNTLREG3				_MMIO(0xB024)
>  
>  #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
> -#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> +#define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
> +#define  GEN7_WA_L3_CHICKEN_MODE		0x20000000

Seems that the GEN7 part jumped on the wrong side of the fence.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +#define  GEN11_I2M_WRITE_DISABLE		(1 << 28)
>  
>  #define GEN7_L3SQCREG4				_MMIO(0xb034)
>  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ffb0e30..bba43fd 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -750,6 +750,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
>  		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
>  		    GWUNIT_CLKGATE_DIS));
> +
> +	/* Wa_1604302699:icl */
> +	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
> +		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
> +		    GEN11_I2M_WRITE_DISABLE));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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