Re: [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Wed, May 02, 2018 at 01:34:01PM -0700, Oscar Mateo wrote:
> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> power by dynamically changing its clock frequency in low-throughput
> conditions. This patches enables it by default on Gen11.
> 
> v2: Wrong operation to clear the bit (Praveen)
> v3: Rebased on top of the WA refactoring
> v4: Move to icl_init_clock_gating, since it's not a WA (Rodrigo)

thanks

> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Praveen Paneri <praveen.paneri@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 454009f..3b5d298 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8253,6 +8253,9 @@ enum {
>  #define GEN8_GARBCNTL                   _MMIO(0xB004)
>  #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>  
> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
> +#define   DFR_DISABLE			(1 << 9)
> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9c6e48c..4a63e38 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8664,6 +8664,13 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>  	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>  }
>  
> +static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> +	/* This is not an Wa. Enable to reduce Sampler power */
> +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> +}
> +
>  static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	if (!HAS_PCH_CNP(dev_priv))
> @@ -9191,7 +9198,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_ICELAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = nop_init_clock_gating;
> +		dev_priv->display.init_clock_gating = icl_init_clock_gating;
>  	else if (IS_CANNONLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>  	else if (IS_COFFEELAKE(dev_priv))
> -- 
> 1.9.1
> 
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