Re: [v3 1/7] i915/dp/fec: Cache the FEC_CAPABLE DPCD register

[Manasi Navare <manasi.d.navare@intel.com>]

On Thu, Oct 25, 2018 at 09:49:37PM -0700, Anusha Srivatsa wrote:
> Similar to DSC DPCD registers, let us cache
> FEC_CAPABLE register to avoid using stale
> values. With this we can avoid aux reads
> everytime and instead read the cached values.
> 
> v2: Avoid using memset and array for a single
> field. (Manasi,Jani)
> 
> Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 10 ++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5a638503e36a..16d1db7c9398 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4198,9 +4198,13 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
>  	/*
>  	 *Clear the cached register set to avoid using stale values
>  	 * for the sinks that do not support DSC.
> +	 * Similarly, clear the cached FEC register.

You dont need this comment here about clearing cached reg since you have
a separate comment below.

>  	 */
>  	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
>  
> +	/* Clear fec_capable to avoid using stale values */
> +	intel_dp->fec_capable = 0;
> +
>  	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
>  	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
>  	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> @@ -4214,6 +4218,12 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
>  			      (int)sizeof(intel_dp->dsc_dpcd),
>  			      intel_dp->dsc_dpcd);
>  	}

Why cant you embed reading FEC reg in the above condition.
Within that just check !edp and read fec reg.

Manasi

> +	/* FEC is supported only on DP 1.4 */
> +	if (!intel_dp_is_edp(intel_dp) && intel_dp->dpcd[DP_DPCD_REV] >= 0x14) {
> +		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
> +				      &intel_dp->fec_capable) < 0)
> +			DRM_ERROR("Failed to read FEC DPCD register\n");
> +	}
>  }
>  
>  static bool
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 16bbc3768e02..9a94c6544bf5 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1119,6 +1119,7 @@ struct intel_dp {
>  	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>  	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
>  	u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> +	u8 fec_capable;
>  	/* source rates */
>  	int num_source_rates;
>  	const int *source_rates;
> -- 
> 2.17.1
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx