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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [v3 4/7] i915/dp/fec: Add can_fec to the crtc state.
Date: Tue, 30 Oct 2018 21:38:54 +0200	[thread overview]
Message-ID: <20181030193854.GI9144@intel.com> (raw)
In-Reply-To: <20181030185712.GH9144@intel.com>

On Tue, Oct 30, 2018 at 08:57:12PM +0200, Ville Syrjälä wrote:
> On Thu, Oct 25, 2018 at 09:49:40PM -0700, Anusha Srivatsa wrote:
> > Add a crtc state for FEC. Currently, the state
> > is determined by platform, DP and DSC being
> > enabled. Moving forward we can use the state
> > to have error correction on other scenarios too
> > if needed.
> > 
> > Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c  | 22 ++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_drv.h |  3 +++
> >  2 files changed, 25 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index cfcef9e4b5d9..4776ce6f2174 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2045,6 +2045,23 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
> >  	return false;
> >  }
> >  
> > +static bool intel_dp_can_fec(struct intel_dp *intel_dp,
> > +			     struct intel_crtc_state *pipe_config)
> > +{
> > +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> > +	if (INTEL_GEN(dev_priv) < 11 || intel_dp_is_edp(intel_dp))
> > +		return false;
> 
> We don't need FEC for eDP DSC?

This stuff maybe needs another sink vs. source split and whatnot.

Maybe along these lines:

source_supportes_fec()
{
	return GEN >= 11 && port != PORT_A;
}

sink_supports_fec()
{
	return whatever;
}

supports_fec()
{
	return source_supports_fec() &&
		sink_supports_fec();
}

compute_dsc()
{
	/* eDP DSC does not need FEC */
	fec_enable = !is_edp();

	if (fec_enable && !supports_fec())
		return false;

	if (!supports_dsc())
		return false;

	...
}


> 
> > +
> > +	/* On Gen 11, FEC is Supported Only for DP SST modes.
> > +	 * Let us start by enabling FEC for Compressed streams.
> > +	 */
> > +	if (pipe_config->dsc_params.compression_enable)
> > +		return true;
> > +	else
> > +		return false;
> > +
> > +}
> >  static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  					struct intel_crtc_state *pipe_config,
> >  					struct link_config_limits *limits)
> > @@ -2129,6 +2146,11 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  		      pipe_config->dsc_params.compressed_bpp,
> >  		      pipe_config->dsc_params.slice_count);
> >  
> > +	/* For DP 1.4, Enable DSC if FEC can be configured */
> > +	pipe_config->can_fec = intel_dp_can_fec(intel_dp, pipe_config);
> > +	if (!pipe_config->can_fec)
> > +		return false;
> > +
> >  	return true;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 9a94c6544bf5..9dac242ead12 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -940,6 +940,9 @@ struct intel_crtc_state {
> >  		u8 slice_count;
> >  	} dsc_params;
> >  	struct drm_dsc_config dp_dsc_cfg;
> > +
> > +	/* Forward Error correction State */
> > +	bool can_fec;
> 
> 'fec_enable' is what I'd call this.
> 
> We're rather inconsistent with  foo_enable vs. foo_enabled vs.
> enable_foo, but one has to pick something.
> 
> >  };
> >  
> >  struct intel_crtc {
> > -- 
> > 2.17.1
> 
> -- 
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-10-30 19:38 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-26  4:49 [v3 0/7] Forward Error Correction Anusha Srivatsa
2018-10-26  4:49 ` [v3 1/7] i915/dp/fec: Cache the FEC_CAPABLE DPCD register Anusha Srivatsa
2018-10-30  2:29   ` Manasi Navare
2018-10-26  4:49 ` [v3 2/7] drm/dp/fec: DRM helper for Forward Error Correction Anusha Srivatsa
2018-10-30  2:30   ` Manasi Navare
2018-10-26  4:49 ` [v3 3/7] i915/dp/fec: Check for FEC Support Anusha Srivatsa
2018-10-26  4:49 ` [v3 4/7] i915/dp/fec: Add can_fec to the crtc state Anusha Srivatsa
2018-10-30  2:44   ` Manasi Navare
2018-10-30 18:57   ` Ville Syrjälä
2018-10-30 19:38     ` Ville Syrjälä [this message]
2018-10-26  4:49 ` [v3 5/7] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Anusha Srivatsa
2018-10-26  4:49 ` [v3 6/7] i915/dp/fec: Configure the Forward Error Correction bits Anusha Srivatsa
2018-10-26  4:49 ` [v3 7/7] drm/i915/fec: Disable FEC state Anusha Srivatsa
2018-10-26  5:07 ` ✗ Fi.CI.BAT: failure for Forward Error Correction (rev3) Patchwork

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