From: Patchwork <patchwork@emeril.freedesktop.org>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe
Date: Sat, 03 Nov 2018 03:59:28 -0000 [thread overview]
Message-ID: <20181103035928.3499.62723@emeril.freedesktop.org> (raw)
In-Reply-To: <20181103034932.26493-1-manasi.d.navare@intel.com>
== Series Details ==
Series: series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe
URL : https://patchwork.freedesktop.org/series/51997/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e904fd188f2c drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 342 lines checked
c5a2fc29ad7f drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34:
Co-developed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+ bool convert_rgb;
-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+ bool enable422;
-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+ bool block_pred_enable;
-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+ bool vbr_enable;
-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+ bool native_422;
-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+ bool native_420;
total: 0 errors, 1 warnings, 6 checks, 121 lines checked
9e8cbea7c63a drm/dsc: Define Rate Control values that do not change over configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Srivatsa, Anusha <anusha.srivatsa@intel.com>'
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
2fdfc3121810 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 285 lines checked
16ed1feab6af drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
d16ba85051ec drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:942:
+ bool compression_enable;
-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:943:
+ bool dsc_split;
total: 0 errors, 0 warnings, 2 checks, 22 lines checked
476f87616dbe drm/i915/dp: Compute DSC pipe config in atomic check
-:273: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#273: FILE: drivers/gpu/drm/i915/intel_dp.c:2112:
+ limits.max_bpp >= DP_DSC_MIN_SUPPORTED_BPC*3)
^
total: 0 errors, 0 warnings, 1 checks, 292 lines checked
7f3efca7e47a drm/i915/dp: Do not enable PSR2 if DSC is enabled
a11590e2c032 drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68:
Co-developed-by: Manasi Navare <manasi.d.navare@intel.com>
-:95: WARNING:MISSING_SPACE: break quoted strings at a space character
#95: FILE: drivers/gpu/drm/i915/intel_dp.c:2080:
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d"
+ "Compressed BPP = %d\n",
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#119:
new file mode 100644
-:405: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#405: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};
total: 0 errors, 3 warnings, 1 checks, 496 lines checked
d30d485fbaa5 drm/i915/dsc: Compute Rate Control parameters for DSC
-:141: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#141: FILE: drivers/gpu/drm/i915/intel_vdsc.c:411:
+ vdsc_cfg->slice_bpg_offset)*
^
-:173: CHECK:LINE_SPACING: Please don't use multiple blank lines
#173: FILE: drivers/gpu/drm/i915/intel_vdsc.c:443:
+
+
total: 0 errors, 0 warnings, 2 checks, 138 lines checked
6d3d7696244f drm/i915/dp: Enable/Disable DSC in DP Sink
3ff059cd1079 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
55228524d5aa drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
-:45: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#45: FILE: drivers/gpu/drm/i915/i915_drv.h:3488:
+extern void intel_dsc_enable(struct intel_encoder *encoder,
-:369: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#369: FILE: drivers/gpu/drm/i915/intel_vdsc.c:865:
+ rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] <<
^
-:372: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#372: FILE: drivers/gpu/drm/i915/intel_vdsc.c:868:
+ rc_buf_thresh_dword[i/4]);
^
-:413: WARNING:LONG_LINE: line over 100 characters
#413: FILE: drivers/gpu/drm/i915/intel_vdsc.c:909:
+ rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
-:413: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#413: FILE: drivers/gpu/drm/i915/intel_vdsc.c:909:
+ rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
^
-:420: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#420: FILE: drivers/gpu/drm/i915/intel_vdsc.c:916:
+ rc_range_params_dword[i/2]);
^
-:498: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#498: FILE: drivers/gpu/drm/i915/intel_vdsc.c:994:
+{
+
-:505: WARNING:RETURN_VOID: void function return statements are not generally useful
#505: FILE: drivers/gpu/drm/i915/intel_vdsc.c:1001:
+ return;
+}
total: 0 errors, 2 warnings, 6 checks, 449 lines checked
093a1a6e72a0 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
60aae01038ed drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
a92c77c255c1 drm/i915/dp: Configure Display stream splitter registers during DSC enable
2a5b79ad1d98 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
-:35: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:3490:
+extern void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
-:91: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#91: FILE: drivers/gpu/drm/i915/intel_vdsc.c:1075:
+
+}
total: 0 errors, 0 warnings, 2 checks, 50 lines checked
9e778cbe005f drm/i915/dsc: Enable and disable appropriate power wells for VDSC
64bb1ef628e8 drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
-:127: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'.
#127: FILE: drivers/gpu/drm/i915/i915_debugfs.c:5113:
+ debugfs_create_file("i915_dsc_support", S_IRUGO, root,
-:163: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#163: FILE: drivers/gpu/drm/i915/intel_drv.h:1205:
+ bool force_dsc_en;
total: 0 errors, 1 warnings, 1 checks, 118 lines checked
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next prev parent reply other threads:[~2018-11-03 3:59 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-03 3:49 [CI 01/19] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-03 3:49 ` [CI 02/19] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-03 3:49 ` [CI 03/19] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-03 3:49 ` [CI 04/19] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-03 3:49 ` [CI 05/19] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-03 3:49 ` [CI 06/19] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-03 3:49 ` [CI 07/19] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-03 3:49 ` [CI 08/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-03 3:49 ` [CI 09/19] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-03 3:49 ` [CI 10/19] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-03 3:49 ` [CI 11/19] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-03 3:49 ` [CI 12/19] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-03 3:49 ` [CI 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-03 3:49 ` [CI 14/19] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-03 3:49 ` [CI 15/19] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-03 3:49 ` [CI 16/19] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-03 3:49 ` [CI 17/19] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-03 3:49 ` [CI 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-03 3:49 ` [CI 19/19] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-11-03 3:59 ` Patchwork [this message]
2018-11-03 4:06 ` ✗ Fi.CI.SPARSE: warning for series starting with [CI,01/19] drm/dsc: Define Display Stream Compression PPS infoframe Patchwork
2018-11-03 4:22 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-03 5:45 ` ✓ Fi.CI.IGT: " Patchwork
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