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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH 09/10] drm/i915/tgl:Added DC3CO counter in i915_dmc_info.
Date: Fri, 28 Jun 2019 18:37:53 +0530	[thread overview]
Message-ID: <20190628130754.9527-10-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190628130754.9527-1-anshuman.gupta@intel.com>

This patch exposes DC3CO counter in i915_dmc_info debugfs.
Which will be useful for DC3CO validation.
DMC firmware is using DMC_DEBUG3 register as DC3CO counter.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 15 ++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h     |  3 +++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 072464a18050..76e425cc19c2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2719,9 +2719,22 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
-	if (WARN_ON(INTEL_GEN(dev_priv) > 11))
+	if (WARN_ON(INTEL_GEN(dev_priv) > 12))
 		goto out;
 
+	/*
+	 * B.Spes specify that DMC_DEBUG3 is general debug register
+	 * DMC folks uses this register for DC3CO counter for TGL
+	 */
+	/*
+	 * It requires TGL plaform enabling pacthes to be merged in order to use
+	 * IS_TIGERLAKE() macro. Using INTEL_GEN instead of IS_TIGERLAKE in
+	 * order to avoid compilation errors.
+	 */
+	//if (IS_TIGERLAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) == 12)
+		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
 	seq_printf(m, "DC3 -> DC5 count: %d\n",
 		   I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
 						    SKL_CSR_DC3_DC5_COUNT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf59ff40719f..3febd29df5d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7221,6 +7221,9 @@ enum {
 #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 
+/* DMC DEBUG COUNTERS for TGL*/
+#define DMC_DEBUG3		_MMIO(0x101090) /*DC3CO debug counter*/
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.21.0

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  parent reply	other threads:[~2019-06-28 13:12 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-28 13:07 [PATCH 00/10] DC3CO Support for TGL Anshuman Gupta
2019-06-28 13:07 ` [PATCH 01/10] drm/i915/tgl:Added DC3CO required register and bits Anshuman Gupta
2019-06-28 13:07 ` [PATCH 02/10] i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-06-28 13:07 ` [PATCH 03/10] i915:Added DC3CO power well Anshuman Gupta
2019-06-28 13:07 ` [PATCH 04/10] drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
2019-06-28 13:07 ` [PATCH 05/10] drm/i915/tgl:Added helper function to prefer dc3co over dc5 Anshuman Gupta
2019-06-28 13:07 ` [PATCH 06/10] drm/i915/tgl:Added VIDEO power domain Anshuman Gupta
2019-06-28 13:07 ` [PATCH 07/10] drm/i915/tgl:DC3CO PSR2 helper Anshuman Gupta
2019-06-28 13:07 ` [PATCH 08/10] drm/i915/tgl:switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-06-28 13:07 ` Anshuman Gupta [this message]
2019-06-28 13:07 ` [PATCH 10/10] drm/i915/tgl: Added new DC5/DC6 counter Anshuman Gupta

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