[PATCH 07/10] drm/i915/tgl:DC3CO PSR2 helper.

[Anshuman Gupta <anshuman.gupta@intel.com>]

This patch adds dc3co helper function to enable/disable
psr2 deep sleep.
This patch make sure DC3CO disallowed before PSR2 exit,
it does that essentially by putting a reference to
POWER_DOMAIN_VIDEO before PSR2 exit.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: jose.souza@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_psr.h |  2 ++
 2 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 963663ba0edf..1c0cbfd50ad4 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -542,6 +542,60 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
 
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+	int idle_frames = 0;
+
+	idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+	/*
+	 * PSR registers are moved to each transcoder, it requires
+	 * https://patchwork.freedesktop.org/series/62416/ series
+	 * to be merged in order to use new PSR macro, as of now
+	 * using old PSR register macro to avoid compilation error.
+	 * similar logic on other places using the PSR2_CTL reg.
+	 */
+	//val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
+	val = I915_READ(EDP_PSR2_CTL);
+	val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+	val |= idle_frames;
+	//I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+	I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+	int idle_frames;
+
+	/*
+	 * Let's use 6 as the minimum to cover all known cases including the
+	 * off-by-one issue that HW has in some cases.
+	 */
+	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+	idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT;
+	//val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
+	val = I915_READ(EDP_PSR2_CTL);
+	val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+	val |= idle_frames;
+	//I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+	I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+	intel_wakeref_t wakeref __maybe_unused;
+
+	/* Before PSR2 exit disallow dc3co*/
+	mutex_lock(&dev_priv->csr.dc5_mutex);
+	wakeref	= fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+	if (wakeref)
+		intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO,
+					dev_priv->csr.dc5_wakeref);
+	mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -798,6 +852,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
 	}
 
 	if (dev_priv->psr.psr2_enabled) {
+		tgl_disallow_dc3co_on_psr2_exit(dev_priv);
 		val = I915_READ(EDP_PSR2_CTL);
 		WARN_ON(!(val & EDP_PSR2_ENABLE));
 		I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
diff --git a/drivers/gpu/drm/i915/intel_psr.h b/drivers/gpu/drm/i915/intel_psr.h
index dc818826f36d..6fb4c385489c 100644
--- a/drivers/gpu/drm/i915/intel_psr.h
+++ b/drivers/gpu/drm/i915/intel_psr.h
@@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
 			    u32 *out_value);
 bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx