From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH 02/10] i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask.
Date: Fri, 28 Jun 2019 18:37:46 +0530 [thread overview]
Message-ID: <20190628130754.9527-3-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190628130754.9527-1-anshuman.gupta@intel.com>
This patch enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 3 ++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index b5be0abbba35..eed19ce3c18a 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
- "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+ "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+ "3=up to DC6 with DC3CO)");
i915_param_named_unsafe(enable_fbc, int, 0600,
"Enable frame buffer compression for power savings "
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b4abababdf6c..c860c1107c82 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -948,6 +948,10 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
+
+ if (INTEL_GEN(dev_priv) == 12)
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ | DC_STATE_EN_DC9;
if (INTEL_GEN(dev_priv) >= 11)
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
@@ -3754,7 +3758,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(dev_priv) == 12) {
+ max_dc = 3;
+ mask = DC_STATE_EN_DC9;
+ } else if (INTEL_GEN(dev_priv) >= 11) {
max_dc = 2;
/*
* DC9 has a separate HW flow from the rest of the DC states,
@@ -3780,7 +3787,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
requested_dc = enable_dc;
} else if (enable_dc == -1) {
requested_dc = max_dc;
- } else if (enable_dc > max_dc && enable_dc <= 2) {
+ } else if (enable_dc > max_dc && enable_dc <= 3) {
DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
enable_dc, max_dc);
requested_dc = max_dc;
@@ -3789,6 +3796,8 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
requested_dc = max_dc;
}
+ if (requested_dc > 2)
+ mask |= DC_STATE_EN_DC3CO;
if (requested_dc > 1)
mask |= DC_STATE_EN_UPTO_DC6;
if (requested_dc > 0)
--
2.21.0
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next prev parent reply other threads:[~2019-06-28 13:12 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 13:07 [PATCH 00/10] DC3CO Support for TGL Anshuman Gupta
2019-06-28 13:07 ` [PATCH 01/10] drm/i915/tgl:Added DC3CO required register and bits Anshuman Gupta
2019-06-28 13:07 ` Anshuman Gupta [this message]
2019-06-28 13:07 ` [PATCH 03/10] i915:Added DC3CO power well Anshuman Gupta
2019-06-28 13:07 ` [PATCH 04/10] drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
2019-06-28 13:07 ` [PATCH 05/10] drm/i915/tgl:Added helper function to prefer dc3co over dc5 Anshuman Gupta
2019-06-28 13:07 ` [PATCH 06/10] drm/i915/tgl:Added VIDEO power domain Anshuman Gupta
2019-06-28 13:07 ` [PATCH 07/10] drm/i915/tgl:DC3CO PSR2 helper Anshuman Gupta
2019-06-28 13:07 ` [PATCH 08/10] drm/i915/tgl:switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-06-28 13:07 ` [PATCH 09/10] drm/i915/tgl:Added DC3CO counter in i915_dmc_info Anshuman Gupta
2019-06-28 13:07 ` [PATCH 10/10] drm/i915/tgl: Added new DC5/DC6 counter Anshuman Gupta
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