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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH 06/10] drm/i915/tgl:Added VIDEO power domain.
Date: Fri, 28 Jun 2019 18:37:50 +0530	[thread overview]
Message-ID: <20190628130754.9527-7-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190628130754.9527-1-anshuman.gupta@intel.com>

Added POWER_DOMAIN_VIDEO power domain and added its helper stuff.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well.
which can disallow DC5/6 in order to allow dc3co.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         | 6 ++++++
 drivers/gpu/drm/i915/intel_display.h    | 1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index acc1bc963b06..af4eb223afa2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -360,6 +360,12 @@ struct intel_csr {
 	u32 allowed_dc_mask;
 	intel_wakeref_t wakeref;
 	bool prefer_dc3co;
+	intel_wakeref_t dc5_wakeref;
+	/*
+	 * Mutex to protect dc5_wakeref which make maintain proper
+	 * power domain reference count of POWER_DOMAIN_VIDEO
+	 */
+	struct mutex dc5_mutex;
 };
 
 enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 41f2aa966abc..2789c590ed59 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -251,6 +251,7 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_PORT_OTHER,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO,
+	POWER_DOMAIN_VIDEO,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 056b02c1ab6b..a9714c8ef21a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -472,6 +472,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "VGA";
 	case POWER_DOMAIN_AUDIO:
 		return "AUDIO";
+	case POWER_DOMAIN_VIDEO:
+		return "VIDEO";
 	case POWER_DOMAIN_AUX_A:
 		return "AUX_A";
 	case POWER_DOMAIN_AUX_B:
@@ -2905,6 +2907,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	 */
 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	ICL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_VIDEO) |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
-- 
2.21.0

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  parent reply	other threads:[~2019-06-28 13:12 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-28 13:07 [PATCH 00/10] DC3CO Support for TGL Anshuman Gupta
2019-06-28 13:07 ` [PATCH 01/10] drm/i915/tgl:Added DC3CO required register and bits Anshuman Gupta
2019-06-28 13:07 ` [PATCH 02/10] i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-06-28 13:07 ` [PATCH 03/10] i915:Added DC3CO power well Anshuman Gupta
2019-06-28 13:07 ` [PATCH 04/10] drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
2019-06-28 13:07 ` [PATCH 05/10] drm/i915/tgl:Added helper function to prefer dc3co over dc5 Anshuman Gupta
2019-06-28 13:07 ` Anshuman Gupta [this message]
2019-06-28 13:07 ` [PATCH 07/10] drm/i915/tgl:DC3CO PSR2 helper Anshuman Gupta
2019-06-28 13:07 ` [PATCH 08/10] drm/i915/tgl:switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-06-28 13:07 ` [PATCH 09/10] drm/i915/tgl:Added DC3CO counter in i915_dmc_info Anshuman Gupta
2019-06-28 13:07 ` [PATCH 10/10] drm/i915/tgl: Added new DC5/DC6 counter Anshuman Gupta

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