* [PATCH 1/5] drm/i915/tgl: Add DKL phy pll registers
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
@ 2019-07-25 23:56 ` Lucas De Marchi
2019-07-25 23:56 ` [PATCH 2/5] drm/i915/tgl: re-indent code to prepare for DKL changes Lucas De Marchi
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2019-07-25 23:56 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
These are the registers needed to program Dekel PHY. Some register
definitions reuse the MG PHY definitions. Add a comment on those so we
don't need to duplicate the functions for programming them.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 94 +++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..0ea556abee1a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9976,6 +9976,100 @@ enum skl_power_gate {
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
+#define _DKL_PHY1_BASE 0x168000
+#define _DKL_PHY2_BASE 0x169000
+#define _DKL_PHY3_BASE 0x16A000
+#define _DKL_PHY4_BASE 0x16B000
+#define _DKL_PHY5_BASE 0x16C000
+#define _DKL_PHY6_BASE 0x16D000
+
+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+#define _DKL_PLL_DIV0 0x200
+#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
+#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
+#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
+#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
+#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << 8)
+#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << 8)
+#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
+#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
+#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV0)
+
+#define _DKL_PLL_DIV1 0x204
+#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
+#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
+#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV1)
+
+#define _DKL_PLL_SSC 0x210
+#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
+#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
+#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
+#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
+#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
+#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
+#define DKL_PLL_SSC_EN (1 << 9)
+#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_SSC)
+
+#define _DKL_PLL_BIAS 0x214
+#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
+#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << 8)
+#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0xFF << 8)
+#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_BIAS)
+
+#define _DKL_PLL_TDC_COLDST_BIAS 0x218
+#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
+#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
+#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
+#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
+#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_TDC_COLDST_BIAS)
+
+#define _DKL_REFCLKIN_CTL 0x12C
+/* Bits are the same as MG_REFCLKIN_CTL */
+#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_REFCLKIN_CTL)
+
+#define _DKL_CLKTOP2_HSCLKCTL 0xD4
+/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
+#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CLKTOP2_HSCLKCTL)
+
+#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
+/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
+#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CLKTOP2_CORECLKCTL1)
+
+/*
+ * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
+ * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
+ * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
+ * bits that point the 4KB window into the full PHY register space.
+ */
+#define _HIP_INDEX_REG0 0x1010A0
+#define _HIP_INDEX_REG1 0x1010A4
+#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 3 \
+ ? _HIP_INDEX_REG0 \
+ : _HIP_INDEX_REG1)
+#define HIP_INDEX_VAL(index, tc_port) ((index) << (((tc_port) * 8) % 32))
+
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
--
2.21.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/5] drm/i915/tgl: re-indent code to prepare for DKL changes
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
2019-07-25 23:56 ` [PATCH 1/5] drm/i915/tgl: Add DKL phy pll registers Lucas De Marchi
@ 2019-07-25 23:56 ` Lucas De Marchi
2019-07-25 23:56 ` [PATCH 3/5] drm/i915/tgl: Add DKL phy pll state calculations Lucas De Marchi
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2019-07-25 23:56 UTC (permalink / raw)
To: intel-gfx
The final save operation into pll_state of the calculations done will
be different for DKL PHY. Prepare for that by reindenting code so it's
easier to check for correctness. This one has no change in behavior.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-10-lucas.demarchi@intel.com
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 119 ++++++++++--------
1 file changed, 66 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f9bdf8514a53..7eefd63a8b7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2804,60 +2804,73 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
}
ssc_steplog = 4;
- pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
- MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
- MG_PLL_DIV0_FBDIV_INT(m2div_int);
-
- pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
- MG_PLL_DIV1_DITHER_DIV_2 |
- MG_PLL_DIV1_NDIVRATIO(1) |
- MG_PLL_DIV1_FBPREDIV(m1div);
-
- pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
- MG_PLL_LF_AFCCNTSEL_512 |
- MG_PLL_LF_GAINCTRL(1) |
- MG_PLL_LF_INT_COEFF(int_coeff) |
- MG_PLL_LF_PROP_COEFF(prop_coeff);
-
- pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
- MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
- MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
- MG_PLL_FRAC_LOCK_DCODITHEREN |
- MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
- if (use_ssc || m2div_rem > 0)
- pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
-
- pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
- MG_PLL_SSC_TYPE(2) |
- MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
- MG_PLL_SSC_STEPNUM(ssc_steplog) |
- MG_PLL_SSC_FLLEN |
- MG_PLL_SSC_STEPSIZE(ssc_stepsize);
-
- pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
- MG_PLL_TDC_COLDST_IREFINT_EN |
- MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
- MG_PLL_TDC_TDCOVCCORR_EN |
- MG_PLL_TDC_TDCSEL(3);
-
- pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
- MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
- MG_PLL_BIAS_BIAS_BONUS(10) |
- MG_PLL_BIAS_BIASCAL_EN |
- MG_PLL_BIAS_CTRIM(12) |
- MG_PLL_BIAS_VREF_RDAC(4) |
- MG_PLL_BIAS_IREFTRIM(iref_trim);
-
- if (refclk_khz == 38400) {
- pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
- pll_state->mg_pll_bias_mask = 0;
- } else {
- pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
- pll_state->mg_pll_bias_mask = -1U;
- }
+ /* write pll_state calculations */
+ {
+ pll_state->mg_pll_div0 =
+ (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
+ MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
+ MG_PLL_DIV0_FBDIV_INT(m2div_int);
+
+ pll_state->mg_pll_div1 =
+ MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
+ MG_PLL_DIV1_DITHER_DIV_2 |
+ MG_PLL_DIV1_NDIVRATIO(1) |
+ MG_PLL_DIV1_FBPREDIV(m1div);
+
+ pll_state->mg_pll_lf =
+ MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
+ MG_PLL_LF_AFCCNTSEL_512 |
+ MG_PLL_LF_GAINCTRL(1) |
+ MG_PLL_LF_INT_COEFF(int_coeff) |
+ MG_PLL_LF_PROP_COEFF(prop_coeff);
+
+ pll_state->mg_pll_frac_lock =
+ MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
+ MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
+ MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
+ MG_PLL_FRAC_LOCK_DCODITHEREN |
+ MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
+ if (use_ssc || m2div_rem > 0)
+ pll_state->mg_pll_frac_lock |=
+ MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
+
+ pll_state->mg_pll_ssc =
+ (use_ssc ? MG_PLL_SSC_EN : 0) |
+ MG_PLL_SSC_TYPE(2) |
+ MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
+ MG_PLL_SSC_STEPNUM(ssc_steplog) |
+ MG_PLL_SSC_FLLEN |
+ MG_PLL_SSC_STEPSIZE(ssc_stepsize);
+
+ pll_state->mg_pll_tdc_coldst_bias =
+ MG_PLL_TDC_COLDST_COLDSTART |
+ MG_PLL_TDC_COLDST_IREFINT_EN |
+ MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
+ MG_PLL_TDC_TDCOVCCORR_EN |
+ MG_PLL_TDC_TDCSEL(3);
+
+ pll_state->mg_pll_bias =
+ MG_PLL_BIAS_BIAS_GB_SEL(3) |
+ MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
+ MG_PLL_BIAS_BIAS_BONUS(10) |
+ MG_PLL_BIAS_BIASCAL_EN |
+ MG_PLL_BIAS_CTRIM(12) |
+ MG_PLL_BIAS_VREF_RDAC(4) |
+ MG_PLL_BIAS_IREFTRIM(iref_trim);
+
+ if (refclk_khz == 38400) {
+ pll_state->mg_pll_tdc_coldst_bias_mask =
+ MG_PLL_TDC_COLDST_COLDSTART;
+ pll_state->mg_pll_bias_mask = 0;
+ } else {
+ pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
+ pll_state->mg_pll_bias_mask = -1U;
+ }
- pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask;
- pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
+ pll_state->mg_pll_tdc_coldst_bias &=
+ pll_state->mg_pll_tdc_coldst_bias_mask;
+ pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
+ }
return true;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/5] drm/i915/tgl: Add DKL phy pll state calculations
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
2019-07-25 23:56 ` [PATCH 1/5] drm/i915/tgl: Add DKL phy pll registers Lucas De Marchi
2019-07-25 23:56 ` [PATCH 2/5] drm/i915/tgl: re-indent code to prepare for DKL changes Lucas De Marchi
@ 2019-07-25 23:56 ` Lucas De Marchi
2019-07-25 23:56 ` [PATCH 4/5] drm/i915/tgl: start adding the DKL PLLs to use on TC ports Lucas De Marchi
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2019-07-25 23:56 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reuse the existing calculate icl_calc_mg_pll_state() function.
Since the pll variables are calculated differently for DKL phy, add
support for the same.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 59 ++++++++++++++++---
1 file changed, 50 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 7eefd63a8b7e..3a1348ea6714 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2625,7 +2625,8 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
- struct intel_dpll_hw_state *state)
+ struct intel_dpll_hw_state *state,
+ bool is_dkl)
{
u32 dco_min_freq, dco_max_freq;
int div1_vals[] = {7, 5, 3, 2};
@@ -2647,8 +2648,13 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
continue;
if (div2 >= 2) {
- a_divratio = is_dp ? 10 : 5;
- tlinedrv = 2;
+ if (is_dkl) {
+ a_divratio = 5;
+ tlinedrv = 1;
+ } else {
+ a_divratio = is_dp ? 10 : 5;
+ tlinedrv = 2;
+ }
} else {
a_divratio = 5;
tlinedrv = 0;
@@ -2698,7 +2704,8 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
* adapted to integer-only calculation, that's why it looks so different.
*/
static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
- struct intel_dpll_hw_state *pll_state)
+ struct intel_dpll_hw_state *pll_state,
+ bool is_dkl)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
int refclk_khz = dev_priv->cdclk.hw.ref;
@@ -2715,7 +2722,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
memset(pll_state, 0, sizeof(*pll_state));
if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
- pll_state)) {
+ pll_state, is_dkl)) {
DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
return false;
}
@@ -2723,8 +2730,11 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
m1div = 2;
m2div_int = dco_khz / (refclk_khz * m1div);
if (m2div_int > 255) {
- m1div = 4;
- m2div_int = dco_khz / (refclk_khz * m1div);
+ if (!is_dkl) {
+ m1div = 4;
+ m2div_int = dco_khz / (refclk_khz * m1div);
+ }
+
if (m2div_int > 255) {
DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
clock);
@@ -2753,6 +2763,12 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
iref_trim = 28;
iref_pulse_w = 1;
break;
+
+ /*
+ * TODO: spec adds a case for ndiv = 4 when refclk > 80MHz,
+ * however this doesn't seem possible from the input.
+ * See Issue 17526.
+ */
default:
MISSING_CASE(refclk_khz);
return false;
@@ -2805,7 +2821,31 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
ssc_steplog = 4;
/* write pll_state calculations */
- {
+ if (is_dkl) {
+ pll_state->mg_pll_div0 =
+ DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
+ DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
+ DKL_PLL_DIV0_FBPREDIV(m1div) |
+ DKL_PLL_DIV0_FBDIV_INT(m2div_int);
+
+ pll_state->mg_pll_div1 =
+ DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
+ DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
+
+ pll_state->mg_pll_ssc =
+ DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
+ DKL_PLL_SSC_STEP_LEN(ssc_steplen) |
+ DKL_PLL_SSC_STEP_NUM(ssc_steplog) |
+ (use_ssc ? DKL_PLL_SSC_EN : 0);
+
+ pll_state->mg_pll_tdc_coldst_bias =
+ DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
+ DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
+
+ pll_state->mg_pll_bias =
+ (m2div_frac > 0 ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
+ DKL_PLL_BIAS_FBDIV_FRAC(m2div_frac);
+ } else {
pll_state->mg_pll_div0 =
(m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
@@ -2963,6 +3003,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct icl_port_dpll *port_dpll;
enum intel_dpll_id dpll_id;
+ bool is_dkl = INTEL_GEN(dev_priv) >= 12;
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
@@ -2983,7 +3024,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
- if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
+ if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state, is_dkl)) {
DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n");
goto err_unreference_tbt_pll;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/5] drm/i915/tgl: start adding the DKL PLLs to use on TC ports
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
` (2 preceding siblings ...)
2019-07-25 23:56 ` [PATCH 3/5] drm/i915/tgl: Add DKL phy pll state calculations Lucas De Marchi
@ 2019-07-25 23:56 ` Lucas De Marchi
2019-07-25 23:56 ` [PATCH 5/5] drm/i915/tgl: Add support for dkl pll write Lucas De Marchi
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2019-07-25 23:56 UTC (permalink / raw)
To: intel-gfx
The disable function can be the same as for MG phy since the same
registers are used. The others are different as registers change -
prepare for that using an empty dkl_pll_write() to be implemented later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 98 ++++++++++++++++++-
1 file changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 3a1348ea6714..049b68e0c61c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3158,6 +3158,60 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
return ret;
}
+static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll,
+ struct intel_dpll_hw_state *hw_state)
+{
+ const enum intel_dpll_id id = pll->info->id;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(id);
+ intel_wakeref_t wakeref;
+ bool ret = false;
+ u32 val;
+
+ wakeref = intel_display_power_get_if_enabled(dev_priv,
+ POWER_DOMAIN_DISPLAY_CORE);
+ if (!wakeref)
+ return false;
+
+ val = I915_READ(MG_PLL_ENABLE(tc_port));
+ if (!(val & PLL_ENABLE))
+ goto out;
+
+ /*
+ * All registers read here have the same HIP_INDEX_REG even though
+ * they are on different building blocks
+ */
+ I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+ hw_state->mg_refclkin_ctl = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+ hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+
+ hw_state->mg_clktop2_hsclkctl =
+ I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+ hw_state->mg_clktop2_hsclkctl &=
+ MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
+
+ hw_state->mg_clktop2_coreclkctl1 =
+ I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ hw_state->mg_clktop2_coreclkctl1 &=
+ MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
+ hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port));
+ hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port));
+ hw_state->mg_pll_ssc = I915_READ(DKL_PLL_SSC(tc_port));
+ hw_state->mg_pll_bias = I915_READ(DKL_PLL_BIAS(tc_port));
+ hw_state->mg_pll_tdc_coldst_bias =
+ I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+
+ ret = true;
+out:
+ intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
+ return ret;
+}
+
static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state,
@@ -3292,6 +3346,12 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
}
+static void dkl_pll_write(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ /* TODO */
+}
+
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
@@ -3399,6 +3459,31 @@ static void mg_pll_enable(struct drm_i915_private *dev_priv,
/* DVFS post sequence would be here. See the comment above. */
}
+static void dkl_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ /*
+ * From spec: MG register instances are being used for TypeC in general. The
+ * same MG register instances should be programmed for Dekel PLLs as well
+ */
+ i915_reg_t enable_reg =
+ MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+
+ icl_pll_power_enable(dev_priv, pll, enable_reg);
+
+ dkl_pll_write(dev_priv, pll);
+
+ /*
+ * DVFS pre sequence would be here, but in our driver the cdclk code
+ * paths should already be setting the appropriate voltage, hence we do
+ * nothing here.
+ */
+
+ icl_pll_enable(dev_priv, pll, enable_reg);
+
+ /* DVFS post sequence would be here. See the comment above. */
+}
+
static void icl_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
@@ -3543,11 +3628,22 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
+ .enable = dkl_pll_enable,
+ .disable = mg_pll_disable,
+ .get_hw_state = dkl_pll_get_hw_state,
+};
+
static const struct dpll_info tgl_plls[] = {
{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
{ "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
- /* TODO: Add typeC plls */
+ { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
+ { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
+ { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
+ { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
+ { "TC PLL 5", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL5, 0 },
+ { "TC PLL 6", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL6, 0 },
{ },
};
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/5] drm/i915/tgl: Add support for dkl pll write
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
` (3 preceding siblings ...)
2019-07-25 23:56 ` [PATCH 4/5] drm/i915/tgl: start adding the DKL PLLs to use on TC ports Lucas De Marchi
@ 2019-07-25 23:56 ` Lucas De Marchi
2019-07-26 2:23 ` ✓ Fi.CI.BAT: success for Tiger Lake: DKL phy PLLs Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2019-07-25 23:56 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Add a new function to write to dkl phy pll registers. As per the
spec all the registers are read modify write.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 ++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 049b68e0c61c..5606a83326e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3349,7 +3349,70 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
static void dkl_pll_write(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- /* TODO */
+ struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
+ u32 val;
+
+ /*
+ * All registers programmed here have the same HIP_INDEX_REG even
+ * though on different building block
+ */
+ I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+ /* All the registers are RMW */
+ val = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+ val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+ val |= hw_state->mg_refclkin_ctl;
+ I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val);
+
+ val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+ val |= hw_state->mg_clktop2_coreclkctl1;
+ I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+
+ val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+ val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+ val |= hw_state->mg_clktop2_hsclkctl;
+ I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+
+ val = I915_READ(DKL_PLL_DIV0(tc_port));
+ val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK |
+ DKL_PLL_DIV0_PROP_COEFF_MASK |
+ DKL_PLL_DIV0_FBPREDIV_MASK |
+ DKL_PLL_DIV0_FBDIV_INT_MASK);
+ val |= hw_state->mg_pll_div0;
+ I915_WRITE(DKL_PLL_DIV0(tc_port), val);
+
+ val = I915_READ(DKL_PLL_DIV1(tc_port));
+ val = ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
+ DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
+ val |= hw_state->mg_pll_div1;
+ I915_WRITE(DKL_PLL_DIV1(tc_port), val);
+
+ val = I915_READ(DKL_PLL_SSC(tc_port));
+ val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+ DKL_PLL_SSC_STEP_LEN_MASK |
+ DKL_PLL_SSC_STEP_NUM_MASK |
+ DKL_PLL_SSC_EN);
+ val |= hw_state->mg_pll_ssc;
+ I915_WRITE(DKL_PLL_SSC(tc_port), val);
+
+ val = I915_READ(DKL_PLL_BIAS(tc_port));
+ val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
+ DKL_PLL_BIAS_FBDIV_FRAC_MASK);
+ val |= hw_state->mg_pll_bias;
+ I915_WRITE(DKL_PLL_BIAS(tc_port), val);
+
+ val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
+ DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
+ val |= hw_state->mg_pll_tdc_coldst_bias;
+ I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+
+ POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
}
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* ✓ Fi.CI.BAT: success for Tiger Lake: DKL phy PLLs
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
` (4 preceding siblings ...)
2019-07-25 23:56 ` [PATCH 5/5] drm/i915/tgl: Add support for dkl pll write Lucas De Marchi
@ 2019-07-26 2:23 ` Patchwork
2019-07-27 2:42 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-07-26 2:23 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake: DKL phy PLLs
URL : https://patchwork.freedesktop.org/series/64273/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13764
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/
Known issues
------------
Here are the changes found in Patchwork_13764 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_create@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-u3/igt@gem_ctx_create@basic.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2600: [PASS][3] -> [INCOMPLETE][4] ([fdo#105411])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-snb-2600/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-snb-2600/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108569])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_exec@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-u3/igt@gem_ctx_exec@basic.html
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [DMESG-FAIL][9] ([fdo#110899]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][17] ([fdo#109271]) -> [PASS][18] +23 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899
Participating hosts (53 -> 45)
------------------------------
Additional (1): fi-pnv-d510
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-8109u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13764
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13764: 547d8a64866c1c4f5dc2dd468a06e1acba7e56a1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
547d8a64866c drm/i915/tgl: Add support for dkl pll write
6839f83e8899 drm/i915/tgl: start adding the DKL PLLs to use on TC ports
fbe654a11aa0 drm/i915/tgl: Add DKL phy pll state calculations
316f1e64a405 drm/i915/tgl: re-indent code to prepare for DKL changes
cad88564dc78 drm/i915/tgl: Add DKL phy pll registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* ✓ Fi.CI.IGT: success for Tiger Lake: DKL phy PLLs
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
` (5 preceding siblings ...)
2019-07-26 2:23 ` ✓ Fi.CI.BAT: success for Tiger Lake: DKL phy PLLs Patchwork
@ 2019-07-27 2:42 ` Patchwork
2019-08-12 16:13 ` [PATCH 0/5] " Lucas De Marchi
2019-08-13 21:18 ` Lucas De Marchi
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-07-27 2:42 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake: DKL phy PLLs
URL : https://patchwork.freedesktop.org/series/64273/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6557_full -> Patchwork_13764_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13764_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-kbl6/igt@gem_ctx_isolation@rcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-kbl2/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb1/igt@gem_exec_balancer@smoke.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-iclb8/igt@gem_exec_balancer@smoke.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-random:
- shard-skl: [PASS][5] -> [FAIL][6] ([fdo#103232])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-256x256-random.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-256x256-random.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
- shard-skl: [PASS][7] -> [FAIL][8] ([fdo#103184] / [fdo#103232]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-skl1/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +5 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109642] / [fdo#111068])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_psr2_su@page_flip.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-iclb8/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +4 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][17] ([fdo#108566]) -> [PASS][18] +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-apl5/igt@gem_ctx_isolation@rcs0-s3.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][19] ([fdo#108566]) -> [PASS][20] +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [INCOMPLETE][21] ([fdo#110741]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][23] ([fdo#105363]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@modeset-vs-vblank-race:
- shard-glk: [FAIL][25] ([fdo#103060]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk9/igt@kms_flip@modeset-vs-vblank-race.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-glk9/igt@kms_flip@modeset-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@basic:
- shard-iclb: [FAIL][27] ([fdo#103167]) -> [PASS][28] +6 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_frontbuffer_tracking@basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-iclb4/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][29] ([fdo#104108]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][31] ([fdo#108145]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [SKIP][33] ([fdo#109441]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb4/igt@kms_psr@psr2_sprite_render.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][35] ([fdo#99912]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-apl3/igt@kms_setmode@basic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-apl4/igt@kms_setmode@basic.html
- shard-hsw: [FAIL][37] ([fdo#99912]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-hsw2/igt@kms_setmode@basic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-hsw1/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-hang-bcs0:
- shard-iclb: [FAIL][39] -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb1/igt@perf_pmu@busy-hang-bcs0.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-iclb6/igt@perf_pmu@busy-hang-bcs0.html
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-iclb: [FAIL][41] ([fdo#105010]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb6/igt@perf_pmu@rc6-runtime-pm-long.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/shard-iclb2/igt@perf_pmu@rc6-runtime-pm-long.html
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 8)
------------------------------
Missing (1): pig-skl-6260u
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6557 -> Patchwork_13764
CI-20190529: 20190529
CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13764: 547d8a64866c1c4f5dc2dd468a06e1acba7e56a1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13764/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 0/5] Tiger Lake: DKL phy PLLs
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
` (6 preceding siblings ...)
2019-07-27 2:42 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-08-12 16:13 ` Lucas De Marchi
2019-08-13 21:18 ` Lucas De Marchi
8 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2019-08-12 16:13 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Intel Graphics
+Vandita
On Thu, Jul 25, 2019 at 4:57 PM Lucas De Marchi
<lucas.demarchi@intel.com> wrote:
>
> Mostly the same patches as https://patchwork.freedesktop.org/series/63670/.
> Rebased.
>
> Lucas De Marchi (2):
> drm/i915/tgl: re-indent code to prepare for DKL changes
> drm/i915/tgl: start adding the DKL PLLs to use on TC ports
Vandita, can you review these 2 patches since they are related to yours?
Thanks
Lucas De Marchi
>
> Vandita Kulkarni (3):
> drm/i915/tgl: Add DKL phy pll registers
> drm/i915/tgl: Add DKL phy pll state calculations
> drm/i915/tgl: Add support for dkl pll write
>
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 335 ++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 94 +++++
> 2 files changed, 368 insertions(+), 61 deletions(-)
>
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 0/5] Tiger Lake: DKL phy PLLs
2019-07-25 23:56 [PATCH 0/5] Tiger Lake: DKL phy PLLs Lucas De Marchi
` (7 preceding siblings ...)
2019-08-12 16:13 ` [PATCH 0/5] " Lucas De Marchi
@ 2019-08-13 21:18 ` Lucas De Marchi
8 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2019-08-13 21:18 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Intel Graphics
I'm dropping this series as Clint is working on this and may have a
different implementation.
Lucas De Marchi
On Thu, Jul 25, 2019 at 4:57 PM Lucas De Marchi
<lucas.demarchi@intel.com> wrote:
>
> Mostly the same patches as https://patchwork.freedesktop.org/series/63670/.
> Rebased.
>
> Lucas De Marchi (2):
> drm/i915/tgl: re-indent code to prepare for DKL changes
> drm/i915/tgl: start adding the DKL PLLs to use on TC ports
>
> Vandita Kulkarni (3):
> drm/i915/tgl: Add DKL phy pll registers
> drm/i915/tgl: Add DKL phy pll state calculations
> drm/i915/tgl: Add support for dkl pll write
>
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 335 ++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 94 +++++
> 2 files changed, 368 insertions(+), 61 deletions(-)
>
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread