Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: nanley.g.chery@intel.com,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	dhinakaran.pandiyan@intel.com, ville.syrjala@intel.com
Subject: [PATCH v7 1/7] drm/framebuffer: Format modifier for Intel Gen-12 render compression
Date: Mon, 25 Nov 2019 16:26:29 -0800	[thread overview]
Message-ID: <20191126002635.5779-2-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20191126002635.5779-1-radhakrishna.sripada@intel.com>

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8caaaf7ff91b..5ba481f49931 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: nanley.g.chery@intel.com,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	dhinakaran.pandiyan@intel.com, ville.syrjala@intel.com
Subject: [Intel-gfx] [PATCH v7 1/7] drm/framebuffer: Format modifier for Intel Gen-12 render compression
Date: Mon, 25 Nov 2019 16:26:29 -0800	[thread overview]
Message-ID: <20191126002635.5779-2-radhakrishna.sripada@intel.com> (raw)
Message-ID: <20191126002629.84FpU4Y4Ta5qo4UWDGicBNtjrD9lahteeATCVfkei5k@z> (raw)
In-Reply-To: <20191126002635.5779-1-radhakrishna.sripada@intel.com>

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8caaaf7ff91b..5ba481f49931 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-11-26  0:25 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-26  0:26 [PATCH v7 0/7] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-11-26  0:26 ` [Intel-gfx] " Radhakrishna Sripada
2019-11-26  0:26 ` Radhakrishna Sripada [this message]
2019-11-26  0:26   ` [Intel-gfx] [PATCH v7 1/7] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
2019-12-12 15:49   ` Radhakrishna Sripada
2019-11-26  0:26 ` [PATCH v7 2/7] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada
2019-11-26  0:26   ` [Intel-gfx] " Radhakrishna Sripada
2019-12-12 15:51   ` Radhakrishna Sripada
2019-11-26  0:26 ` [PATCH v7 3/7] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada
2019-11-26  0:26   ` [Intel-gfx] " Radhakrishna Sripada
2019-12-12 15:53   ` Radhakrishna Sripada
2019-11-26  0:26 ` [PATCH v7 4/7] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
2019-11-26  0:26   ` [Intel-gfx] " Radhakrishna Sripada
2019-12-12 15:59   ` Radhakrishna Sripada
2019-11-26  0:26 ` [PATCH v7 5/7] drm/i915: Extract framebufer CCS offset checks into a function Radhakrishna Sripada
2019-11-26  0:26   ` [Intel-gfx] " Radhakrishna Sripada
2019-12-12 16:00   ` Radhakrishna Sripada
2019-11-26  0:26 ` [PATCH v7 6/7] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
2019-11-26  0:26   ` [Intel-gfx] " Radhakrishna Sripada
2019-11-26  0:26 ` [PATCH v7 7/7] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Radhakrishna Sripada
2019-11-26  0:26   ` [Intel-gfx] " Radhakrishna Sripada
2019-11-26 20:48   ` Matt Roper
2019-11-26 20:48     ` [Intel-gfx] " Matt Roper
2019-11-26 21:52     ` Sripada, Radhakrishna
2019-11-26 21:52       ` [Intel-gfx] " Sripada, Radhakrishna
2019-11-26 22:00       ` Matt Roper
2019-11-26 22:00         ` [Intel-gfx] " Matt Roper
2019-11-26 22:29         ` Sripada, Radhakrishna
2019-11-26 22:29           ` [Intel-gfx] " Sripada, Radhakrishna
2019-11-27  6:49     ` Saarinen, Jani
2019-11-27  6:49       ` [Intel-gfx] " Saarinen, Jani
2019-11-27  0:26   ` [PATCH v8 " Radhakrishna Sripada
2019-11-27  0:26     ` [Intel-gfx] " Radhakrishna Sripada
2019-11-26  0:34 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev10) Patchwork
2019-11-26  0:34   ` [Intel-gfx] " Patchwork
2019-11-26  0:57 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-26  0:57   ` [Intel-gfx] " Patchwork
2019-11-27  2:39 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev11) Patchwork
2019-11-27  2:39   ` [Intel-gfx] " Patchwork
2019-11-27  3:03 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-27  3:03   ` [Intel-gfx] " Patchwork
2019-11-27 13:55 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-27 13:55   ` [Intel-gfx] " Patchwork
2019-12-03 21:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev12) Patchwork
2019-12-03 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191126002635.5779-2-radhakrishna.sripada@intel.com \
    --to=radhakrishna.sripada@intel.com \
    --cc=dhinakaran.pandiyan@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=nanley.g.chery@intel.com \
    --cc=ville.syrjala@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox