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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl, ehl
Date: Mon, 23 Dec 2019 17:20:25 -0800	[thread overview]
Message-ID: <20191224012026.3157766-3-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20191224012026.3157766-1-matthew.d.roper@intel.com>

Workaround database indicates we should disable clock gating of both the
vsunit and hsunit.

Bspec: 33450
Bspec: 33451
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 +++-
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bbfedeb00b7f..968a43f7cd98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4177,7 +4177,9 @@ enum {
 #define  CPSSUNIT_CLKGATE_DIS		REG_BIT(9)
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
-#define  VFUNIT_CLKGATE_DIS		(1 << 20)
+#define   VFUNIT_CLKGATE_DIS		REG_BIT(20)
+#define   HSUNIT_CLKGATE_DIS		REG_BIT(8)
+#define   VSUNIT_CLKGATE_DIS		REG_BIT(3)
 
 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
 #define   CGPSF_CLKGATE_DIS		(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 31ec82337e4f..58ba6cbf9a57 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6590,6 +6590,14 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* WaEnable32PlaneMode:icl */
 	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
 		   _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
+
+	/*
+	 * Wa_1408615072:icl,ehl  (vsunit)
+	 * Wa_1407596294:icl,ehl  (hsunit)
+	 */
+	intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE,
+			 0, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
+
 }
 
 static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.23.0

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  parent reply	other threads:[~2019-12-24  1:20 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-24  1:20 [Intel-gfx] [PATCH 0/3] Workaround updates Matt Roper
2019-12-24  1:20 ` [Intel-gfx] [PATCH 1/3] drm/i915: Extend WaDisableDARBFClkGating to icl, ehl, tgl Matt Roper
2019-12-24 16:52   ` Lucas De Marchi
2019-12-24  1:20 ` Matt Roper [this message]
2019-12-24 17:05   ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl, ehl Lucas De Marchi
2019-12-24  1:20 ` [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Extend Wa_1408615072 to tgl Matt Roper
2019-12-24 17:20   ` Lucas De Marchi
2019-12-24  1:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Workaround updates Patchwork
2019-12-24  6:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Workaround updates (rev2) Patchwork
2019-12-24 17:15   ` Matt Roper
2019-12-24 17:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Workaround updates (rev3) Patchwork
2019-12-25 19:31 ` [Intel-gfx] [PATCH 0/3] Workaround updates Lionel Landwerlin
2019-12-26 17:39   ` Matt Roper
2019-12-26 18:09     ` Lionel Landwerlin
2019-12-26 18:36       ` Matt Roper
2019-12-27 10:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for Workaround updates (rev3) Patchwork
2019-12-27 18:49   ` Matt Roper

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