From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Extend Wa_1408615072 to tgl
Date: Mon, 23 Dec 2019 17:20:26 -0800 [thread overview]
Message-ID: <20191224012026.3157766-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20191224012026.3157766-1-matthew.d.roper@intel.com>
Although the workaround number and description are the same, the vsunit
clock gate disable bit has moved to a new register and location on
gen12.
Bspec: 52890
Bspec: 52758
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 968a43f7cd98..030a3f3e69af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4181,6 +4181,9 @@ enum {
#define HSUNIT_CLKGATE_DIS REG_BIT(8)
#define VSUNIT_CLKGATE_DIS REG_BIT(3)
+#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
+#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
+
#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
#define CGPSF_CLKGATE_DIS (1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 58ba6cbf9a57..fe02ac3a3674 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6605,6 +6605,10 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
u32 vd_pg_enable = 0;
unsigned int i;
+ /* Wa_1408615072:tgl */
+ intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
+ 0, VSUNIT_CLKGATE_DIS_TGL);
+
/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
for (i = 0; i < I915_MAX_VCS; i++) {
if (HAS_ENGINE(dev_priv, _VCS(i)))
--
2.23.0
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next prev parent reply other threads:[~2019-12-24 1:20 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-24 1:20 [Intel-gfx] [PATCH 0/3] Workaround updates Matt Roper
2019-12-24 1:20 ` [Intel-gfx] [PATCH 1/3] drm/i915: Extend WaDisableDARBFClkGating to icl, ehl, tgl Matt Roper
2019-12-24 16:52 ` Lucas De Marchi
2019-12-24 1:20 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl, ehl Matt Roper
2019-12-24 17:05 ` Lucas De Marchi
2019-12-24 1:20 ` Matt Roper [this message]
2019-12-24 17:20 ` [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Extend Wa_1408615072 to tgl Lucas De Marchi
2019-12-24 1:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Workaround updates Patchwork
2019-12-24 6:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Workaround updates (rev2) Patchwork
2019-12-24 17:15 ` Matt Roper
2019-12-24 17:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Workaround updates (rev3) Patchwork
2019-12-25 19:31 ` [Intel-gfx] [PATCH 0/3] Workaround updates Lionel Landwerlin
2019-12-26 17:39 ` Matt Roper
2019-12-26 18:09 ` Lionel Landwerlin
2019-12-26 18:36 ` Matt Roper
2019-12-27 10:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for Workaround updates (rev3) Patchwork
2019-12-27 18:49 ` Matt Roper
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