* [Intel-gfx] [PATCH v3 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain()
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
@ 2020-04-07 21:39 ` José Roberto de Souza
2020-04-08 9:11 ` You-Sheng Yang
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 3/8] drm/i915/display: Split hsw_power_well_enable() into two José Roberto de Souza
` (9 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: José Roberto de Souza @ 2020-04-07 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Cooper Chiou, Kai-Heng Feng, You-Sheng Yang
This is a similar function to intel_aux_power_domain() but it do not
care about TBT ports, this will be needed by ICL TC sequences.
v2:
- renamed to intel_legacy_aux_to_power_domain()
Cc: Imre Deak <imre.deak@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++++--
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70ec301fe6e3..a95960b71001 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7291,7 +7291,17 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
}
}
- switch (dig_port->aux_ch) {
+ return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+}
+
+/*
+ * Converts aux_ch to power_domain without caring about TBT ports for that use
+ * intel_aux_power_domain()
+ */
+enum intel_display_power_domain
+intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
+{
+ switch (aux_ch) {
case AUX_CH_A:
return POWER_DOMAIN_AUX_A;
case AUX_CH_B:
@@ -7307,7 +7317,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
case AUX_CH_G:
return POWER_DOMAIN_AUX_G;
default:
- MISSING_CASE(dig_port->aux_ch);
+ MISSING_CASE(aux_ch);
return POWER_DOMAIN_AUX_A;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index cc7f287804d7..8d872ed0de36 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -583,6 +583,8 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
enum intel_display_power_domain intel_port_to_power_domain(enum port port);
enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port);
+enum intel_display_power_domain
+intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config);
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
--
2.26.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v3 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain()
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
@ 2020-04-08 9:11 ` You-Sheng Yang
0 siblings, 0 replies; 18+ messages in thread
From: You-Sheng Yang @ 2020-04-08 9:11 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx; +Cc: Cooper Chiou, Kai-Heng Feng
[-- Attachment #1.1.1: Type: text/plain, Size: 2710 bytes --]
Also verified this v3 series.
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
On 2020-04-08 05:39, José Roberto de Souza wrote:
> This is a similar function to intel_aux_power_domain() but it do not
> care about TBT ports, this will be needed by ICL TC sequences.
>
> v2:
> - renamed to intel_legacy_aux_to_power_domain()
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++++--
> drivers/gpu/drm/i915/display/intel_display.h | 2 ++
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 70ec301fe6e3..a95960b71001 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7291,7 +7291,17 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
> }
> }
>
> - switch (dig_port->aux_ch) {
> + return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> +}
> +
> +/*
> + * Converts aux_ch to power_domain without caring about TBT ports for that use
> + * intel_aux_power_domain()
> + */
> +enum intel_display_power_domain
> +intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
> +{
> + switch (aux_ch) {
> case AUX_CH_A:
> return POWER_DOMAIN_AUX_A;
> case AUX_CH_B:
> @@ -7307,7 +7317,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
> case AUX_CH_G:
> return POWER_DOMAIN_AUX_G;
> default:
> - MISSING_CASE(dig_port->aux_ch);
> + MISSING_CASE(aux_ch);
> return POWER_DOMAIN_AUX_A;
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index cc7f287804d7..8d872ed0de36 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -583,6 +583,8 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
> enum intel_display_power_domain intel_port_to_power_domain(enum port port);
> enum intel_display_power_domain
> intel_aux_power_domain(struct intel_digital_port *dig_port);
> +enum intel_display_power_domain
> +intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
> void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> struct intel_crtc_state *pipe_config);
> void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
>
[-- Attachment #1.2: OpenPGP digital signature --]
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[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v3 3/8] drm/i915/display: Split hsw_power_well_enable() into two
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
@ 2020-04-07 21:39 ` José Roberto de Souza
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 4/8] drm/i915/tc/icl: Implement TC cold sequences José Roberto de Souza
` (8 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: José Roberto de Souza @ 2020-04-07 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: You-Sheng Yang
This is a preparation for ICL TC cold exit sequences.
v2:
- renamed new functions to hsw_power_well_enable_prepare()/complete()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
---
.../drm/i915/display/intel_display_power.c | 39 +++++++++++++++----
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5a8b94d9a10f..1cd271d0f114 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -380,16 +380,16 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
SKL_FUSE_PG_DIST_STATUS(pg), 1));
}
-static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
+static void hsw_power_well_enable_prepare(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
int pw_idx = power_well->desc->hsw.idx;
- bool wait_fuses = power_well->desc->hsw.has_fuses;
- enum skl_power_gate uninitialized_var(pg);
u32 val;
- if (wait_fuses) {
+ if (power_well->desc->hsw.has_fuses) {
+ enum skl_power_gate pg;
+
pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
SKL_PW_CTL_IDX_TO_PG(pw_idx);
/*
@@ -406,25 +406,46 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
val = intel_de_read(dev_priv, regs->driver);
intel_de_write(dev_priv, regs->driver,
val | HSW_PWR_WELL_CTL_REQ(pw_idx));
+}
+
+static void hsw_power_well_enable_complete(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ int pw_idx = power_well->desc->hsw.idx;
+
hsw_wait_for_power_well_enable(dev_priv, power_well);
/* Display WA #1178: cnl */
if (IS_CANNONLAKE(dev_priv) &&
pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
+ u32 val;
+
val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
}
- if (wait_fuses)
+ if (power_well->desc->hsw.has_fuses) {
+ enum skl_power_gate pg;
+
+ pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+ SKL_PW_CTL_IDX_TO_PG(pw_idx);
gen9_wait_for_power_well_fuses(dev_priv, pg);
+ }
hsw_power_well_post_enable(dev_priv,
power_well->desc->hsw.irq_pipe_mask,
power_well->desc->hsw.has_vga);
}
+static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ hsw_power_well_enable_prepare(dev_priv, power_well);
+ hsw_power_well_enable_complete(dev_priv, power_well);
+}
+
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -570,7 +591,11 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
val |= DP_AUX_CH_CTL_TBT_IO;
intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
- hsw_power_well_enable(dev_priv, power_well);
+ hsw_power_well_enable_prepare(dev_priv, power_well);
+
+ /* TODO ICL TC cold handling */
+
+ hsw_power_well_enable_complete(dev_priv, power_well);
if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc->hsw.is_tc_tbt) {
enum tc_port tc_port;
--
2.26.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [Intel-gfx] [PATCH v3 4/8] drm/i915/tc/icl: Implement TC cold sequences
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 2/8] drm/i915/display: Add intel_legacy_aux_to_power_domain() José Roberto de Souza
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 3/8] drm/i915/display: Split hsw_power_well_enable() into two José Roberto de Souza
@ 2020-04-07 21:39 ` José Roberto de Souza
2020-04-07 22:03 ` Imre Deak
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells José Roberto de Souza
` (7 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: José Roberto de Souza @ 2020-04-07 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Cooper Chiou, Kai-Heng Feng
This is required for legacy/static TC ports as IOM is not aware of
the connection and will not trigger the TC cold exit.
Just request PCODE to exit TCCOLD is not enough as it could enter
again before driver makes use of the port, to prevent it BSpec states
that aux powerwell should be held.
So here embedding the TC cold exit sequence into ICL aux enable,
it will enable aux and then request TC cold to exit.
The TC cold block(exit and aux hold) and unblock was added to some
exported TC functions for the others and to access PHY registers,
callers should enable and keep aux powerwell enabled during access.
Also adding TC cold check and warnig in tc_port_load_fia_params() as
at this point of the driver initialization we can't request power
wells, if we get this warning we will need to figure out how to handle
it.
v2:
- moved ICL TC cold exit function to intel_display_power
- using dig_port->tc_legacy_port to only execute sequences for legacy
ports, hopefully VBTs will have this right
- fixed check to call _hsw_power_well_continue_enable()
- calling _hsw_power_well_continue_enable() unconditionally in
icl_tc_phy_aux_power_well_enable(), if needed we will surpress timeout
warnings of TC legacy ports
- only blocking TC cold around fia access
v3:
- added timeout of 5msec to not loop forever if
sandybridge_pcode_write_timeout() keeps returning -EAGAIN
returning -EAGAIN in in icl_tc_cold_exit()
- removed leftover tc_cold_wakeref
- added one msec sleep when PCODE returns -EAGAIN
BSpec: 21750
Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1296
Cc: Imre Deak <imre.deak@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
.../drm/i915/display/intel_display_power.c | 24 ++++++-
drivers/gpu/drm/i915/display/intel_tc.c | 64 +++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 82 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1cd271d0f114..2d7b2999561a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -575,6 +575,27 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
#define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
+static void icl_tc_cold_exit(struct drm_i915_private *i915)
+{
+ const ktime_t timeout = ktime_add_ms(ktime_get_raw(), 5);
+ int ret;
+
+ do {
+ ret = sandybridge_pcode_write_timeout(i915,
+ ICL_PCODE_EXIT_TCCOLD,
+ 0, 250, 1);
+ if (ret == -EAGAIN)
+ msleep(1);
+ } while (ret == -EAGAIN && ktime_compare(timeout, ktime_get_raw()) > 0);
+
+ /* Spec states that TC cold exit can take up to 1ms to complete */
+ if (!ret)
+ msleep(1);
+
+ drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
+ "succeeded");
+}
+
static void
icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
@@ -593,7 +614,8 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
hsw_power_well_enable_prepare(dev_priv, power_well);
- /* TODO ICL TC cold handling */
+ if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
+ icl_tc_cold_exit(dev_priv);
hsw_power_well_enable_complete(dev_priv, power_well);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 9b850c11aa78..74061bf9b2b9 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -34,6 +34,7 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
if (INTEL_INFO(i915)->display.has_modular_fia) {
modular_fia = intel_uncore_read(&i915->uncore,
PORT_TX_DFLEXDPSP(FIA1));
+ drm_WARN_ON(&i915->drm, modular_fia == 0xffffffff);
modular_fia &= MODULAR_FIA_MASK;
} else {
modular_fia = 0;
@@ -52,6 +53,37 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
}
}
+static intel_wakeref_t
+tc_cold_block(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum intel_display_power_domain domain;
+
+ if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
+ return 0;
+
+ domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+ return intel_display_power_get(i915, domain);
+}
+
+static void
+tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum intel_display_power_domain domain;
+
+ /*
+ * wakeref == -1, means some error happened saving save_depot_stack but
+ * power should still be put down and 0 is a invalid save_depot_stack
+ * id so can be used to skip it for non TC legacy ports.
+ */
+ if (wakeref == 0)
+ return;
+
+ domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+ intel_display_power_put_async(i915, domain, wakeref);
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -415,9 +447,14 @@ static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
enum tc_port_mode old_tc_mode = dig_port->tc_mode;
intel_display_power_flush_work(i915);
- drm_WARN_ON(&i915->drm,
- intel_display_power_is_enabled(i915,
- intel_aux_power_domain(dig_port)));
+ if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port) {
+ enum intel_display_power_domain aux_domain;
+ bool aux_powered;
+
+ aux_domain = intel_aux_power_domain(dig_port);
+ aux_powered = intel_display_power_is_enabled(i915, aux_domain);
+ drm_WARN_ON(&i915->drm, aux_powered);
+ }
icl_tc_phy_disconnect(dig_port);
icl_tc_phy_connect(dig_port, required_lanes);
@@ -439,9 +476,11 @@ intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
{
struct intel_encoder *encoder = &dig_port->base;
+ intel_wakeref_t tc_cold_wref;
int active_links = 0;
mutex_lock(&dig_port->tc_lock);
+ tc_cold_wref = tc_cold_block(dig_port);
dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
if (dig_port->dp.is_mst)
@@ -466,6 +505,7 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
dig_port->tc_port_name,
tc_port_mode_name(dig_port->tc_mode));
+ tc_cold_unblock(dig_port, tc_cold_wref);
mutex_unlock(&dig_port->tc_lock);
}
@@ -487,10 +527,15 @@ static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
bool intel_tc_port_connected(struct intel_digital_port *dig_port)
{
bool is_connected;
+ intel_wakeref_t tc_cold_wref;
intel_tc_port_lock(dig_port);
+ tc_cold_wref = tc_cold_block(dig_port);
+
is_connected = tc_port_live_status_mask(dig_port) &
BIT(dig_port->tc_mode);
+
+ tc_cold_unblock(dig_port, tc_cold_wref);
intel_tc_port_unlock(dig_port);
return is_connected;
@@ -506,9 +551,16 @@ static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
mutex_lock(&dig_port->tc_lock);
- if (!dig_port->tc_link_refcount &&
- intel_tc_port_needs_reset(dig_port))
- intel_tc_port_reset_mode(dig_port, required_lanes);
+ if (!dig_port->tc_link_refcount) {
+ intel_wakeref_t tc_cold_wref;
+
+ tc_cold_wref = tc_cold_block(dig_port);
+
+ if (intel_tc_port_needs_reset(dig_port))
+ intel_tc_port_reset_mode(dig_port, required_lanes);
+
+ tc_cold_unblock(dig_port, tc_cold_wref);
+ }
drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
dig_port->tc_lock_wakeref = wakeref;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a7bd6db164b..0389afa2361f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9108,6 +9108,7 @@ enum {
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
+#define ICL_PCODE_EXIT_TCCOLD 0x12
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
#define DISPLAY_IPS_CONTROL 0x19
/* See also IPS_CTL */
--
2.26.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v3 4/8] drm/i915/tc/icl: Implement TC cold sequences
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 4/8] drm/i915/tc/icl: Implement TC cold sequences José Roberto de Souza
@ 2020-04-07 22:03 ` Imre Deak
2020-04-07 22:20 ` Souza, Jose
0 siblings, 1 reply; 18+ messages in thread
From: Imre Deak @ 2020-04-07 22:03 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: Cooper Chiou, intel-gfx, Kai-Heng Feng
On Tue, Apr 07, 2020 at 02:39:56PM -0700, José Roberto de Souza wrote:
> This is required for legacy/static TC ports as IOM is not aware of
> the connection and will not trigger the TC cold exit.
>
> Just request PCODE to exit TCCOLD is not enough as it could enter
> again before driver makes use of the port, to prevent it BSpec states
> that aux powerwell should be held.
>
> So here embedding the TC cold exit sequence into ICL aux enable,
> it will enable aux and then request TC cold to exit.
>
> The TC cold block(exit and aux hold) and unblock was added to some
> exported TC functions for the others and to access PHY registers,
> callers should enable and keep aux powerwell enabled during access.
>
> Also adding TC cold check and warnig in tc_port_load_fia_params() as
> at this point of the driver initialization we can't request power
> wells, if we get this warning we will need to figure out how to handle
> it.
>
> v2:
> - moved ICL TC cold exit function to intel_display_power
> - using dig_port->tc_legacy_port to only execute sequences for legacy
> ports, hopefully VBTs will have this right
> - fixed check to call _hsw_power_well_continue_enable()
> - calling _hsw_power_well_continue_enable() unconditionally in
> icl_tc_phy_aux_power_well_enable(), if needed we will surpress timeout
> warnings of TC legacy ports
> - only blocking TC cold around fia access
>
> v3:
> - added timeout of 5msec to not loop forever if
> sandybridge_pcode_write_timeout() keeps returning -EAGAIN
> returning -EAGAIN in in icl_tc_cold_exit()
> - removed leftover tc_cold_wakeref
> - added one msec sleep when PCODE returns -EAGAIN
>
> BSpec: 21750
> Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1296
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 24 ++++++-
> drivers/gpu/drm/i915/display/intel_tc.c | 64 +++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 3 files changed, 82 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1cd271d0f114..2d7b2999561a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -575,6 +575,27 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
>
> #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
>
> +static void icl_tc_cold_exit(struct drm_i915_private *i915)
> +{
> + const ktime_t timeout = ktime_add_ms(ktime_get_raw(), 5);
> + int ret;
> +
> + do {
> + ret = sandybridge_pcode_write_timeout(i915,
> + ICL_PCODE_EXIT_TCCOLD,
> + 0, 250, 1);
> + if (ret == -EAGAIN)
> + msleep(1);
> + } while (ret == -EAGAIN && ktime_compare(timeout, ktime_get_raw()) > 0);
this could exit after a single pcode_write() that polled for 1ms, and
msleep(1); is not needed in the last iteration. Retrying 3 times as
discussed earlier would solve that.
> +
> + /* Spec states that TC cold exit can take up to 1ms to complete */
> + if (!ret)
> + msleep(1);
> +
> + drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
> + "succeeded");
You missed turning this to an error.
> +}
> +
> static void
> icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> @@ -593,7 +614,8 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>
> hsw_power_well_enable_prepare(dev_priv, power_well);
>
> - /* TODO ICL TC cold handling */
> + if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
> + icl_tc_cold_exit(dev_priv);
>
> hsw_power_well_enable_complete(dev_priv, power_well);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 9b850c11aa78..74061bf9b2b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -34,6 +34,7 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
> if (INTEL_INFO(i915)->display.has_modular_fia) {
> modular_fia = intel_uncore_read(&i915->uncore,
> PORT_TX_DFLEXDPSP(FIA1));
> + drm_WARN_ON(&i915->drm, modular_fia == 0xffffffff);
> modular_fia &= MODULAR_FIA_MASK;
> } else {
> modular_fia = 0;
> @@ -52,6 +53,37 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
> }
> }
>
> +static intel_wakeref_t
> +tc_cold_block(struct intel_digital_port *dig_port)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum intel_display_power_domain domain;
> +
> + if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
> + return 0;
> +
> + domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> + return intel_display_power_get(i915, domain);
> +}
> +
> +static void
> +tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum intel_display_power_domain domain;
> +
> + /*
> + * wakeref == -1, means some error happened saving save_depot_stack but
> + * power should still be put down and 0 is a invalid save_depot_stack
> + * id so can be used to skip it for non TC legacy ports.
> + */
> + if (wakeref == 0)
> + return;
> +
> + domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> + intel_display_power_put_async(i915, domain, wakeref);
> +}
> +
> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -415,9 +447,14 @@ static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
> enum tc_port_mode old_tc_mode = dig_port->tc_mode;
>
> intel_display_power_flush_work(i915);
> - drm_WARN_ON(&i915->drm,
> - intel_display_power_is_enabled(i915,
> - intel_aux_power_domain(dig_port)));
> + if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port) {
> + enum intel_display_power_domain aux_domain;
> + bool aux_powered;
> +
> + aux_domain = intel_aux_power_domain(dig_port);
> + aux_powered = intel_display_power_is_enabled(i915, aux_domain);
> + drm_WARN_ON(&i915->drm, aux_powered);
> + }
>
> icl_tc_phy_disconnect(dig_port);
> icl_tc_phy_connect(dig_port, required_lanes);
> @@ -439,9 +476,11 @@ intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
> void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
> {
> struct intel_encoder *encoder = &dig_port->base;
> + intel_wakeref_t tc_cold_wref;
> int active_links = 0;
>
> mutex_lock(&dig_port->tc_lock);
> + tc_cold_wref = tc_cold_block(dig_port);
>
> dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
> if (dig_port->dp.is_mst)
> @@ -466,6 +505,7 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
> dig_port->tc_port_name,
> tc_port_mode_name(dig_port->tc_mode));
>
> + tc_cold_unblock(dig_port, tc_cold_wref);
> mutex_unlock(&dig_port->tc_lock);
> }
>
> @@ -487,10 +527,15 @@ static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
> bool intel_tc_port_connected(struct intel_digital_port *dig_port)
> {
> bool is_connected;
> + intel_wakeref_t tc_cold_wref;
>
> intel_tc_port_lock(dig_port);
> + tc_cold_wref = tc_cold_block(dig_port);
> +
> is_connected = tc_port_live_status_mask(dig_port) &
> BIT(dig_port->tc_mode);
> +
> + tc_cold_unblock(dig_port, tc_cold_wref);
> intel_tc_port_unlock(dig_port);
>
> return is_connected;
> @@ -506,9 +551,16 @@ static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
>
> mutex_lock(&dig_port->tc_lock);
>
> - if (!dig_port->tc_link_refcount &&
> - intel_tc_port_needs_reset(dig_port))
> - intel_tc_port_reset_mode(dig_port, required_lanes);
> + if (!dig_port->tc_link_refcount) {
> + intel_wakeref_t tc_cold_wref;
> +
> + tc_cold_wref = tc_cold_block(dig_port);
> +
> + if (intel_tc_port_needs_reset(dig_port))
> + intel_tc_port_reset_mode(dig_port, required_lanes);
> +
> + tc_cold_unblock(dig_port, tc_cold_wref);
> + }
>
> drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
> dig_port->tc_lock_wakeref = wakeref;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1a7bd6db164b..0389afa2361f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9108,6 +9108,7 @@ enum {
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> +#define ICL_PCODE_EXIT_TCCOLD 0x12
> #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> #define DISPLAY_IPS_CONTROL 0x19
> /* See also IPS_CTL */
> --
> 2.26.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v3 4/8] drm/i915/tc/icl: Implement TC cold sequences
2020-04-07 22:03 ` Imre Deak
@ 2020-04-07 22:20 ` Souza, Jose
2020-04-07 22:43 ` Imre Deak
0 siblings, 1 reply; 18+ messages in thread
From: Souza, Jose @ 2020-04-07 22:20 UTC (permalink / raw)
To: Deak, Imre
Cc: Chiou, Cooper, intel-gfx@lists.freedesktop.org,
kai.heng.feng@canonical.com
On Wed, 2020-04-08 at 01:03 +0300, Imre Deak wrote:
> On Tue, Apr 07, 2020 at 02:39:56PM -0700, José Roberto de Souza
> wrote:
> > This is required for legacy/static TC ports as IOM is not aware of
> > the connection and will not trigger the TC cold exit.
> >
> > Just request PCODE to exit TCCOLD is not enough as it could enter
> > again before driver makes use of the port, to prevent it BSpec
> > states
> > that aux powerwell should be held.
> >
> > So here embedding the TC cold exit sequence into ICL aux enable,
> > it will enable aux and then request TC cold to exit.
> >
> > The TC cold block(exit and aux hold) and unblock was added to some
> > exported TC functions for the others and to access PHY registers,
> > callers should enable and keep aux powerwell enabled during access.
> >
> > Also adding TC cold check and warnig in tc_port_load_fia_params()
> > as
> > at this point of the driver initialization we can't request power
> > wells, if we get this warning we will need to figure out how to
> > handle
> > it.
> >
> > v2:
> > - moved ICL TC cold exit function to intel_display_power
> > - using dig_port->tc_legacy_port to only execute sequences for
> > legacy
> > ports, hopefully VBTs will have this right
> > - fixed check to call _hsw_power_well_continue_enable()
> > - calling _hsw_power_well_continue_enable() unconditionally in
> > icl_tc_phy_aux_power_well_enable(), if needed we will surpress
> > timeout
> > warnings of TC legacy ports
> > - only blocking TC cold around fia access
> >
> > v3:
> > - added timeout of 5msec to not loop forever if
> > sandybridge_pcode_write_timeout() keeps returning -EAGAIN
> > returning -EAGAIN in in icl_tc_cold_exit()
> > - removed leftover tc_cold_wakeref
> > - added one msec sleep when PCODE returns -EAGAIN
> >
> > BSpec: 21750
> > Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1296
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Cooper Chiou <cooper.chiou@intel.com>
> > Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > .../drm/i915/display/intel_display_power.c | 24 ++++++-
> > drivers/gpu/drm/i915/display/intel_tc.c | 64
> > +++++++++++++++++--
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 3 files changed, 82 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 1cd271d0f114..2d7b2999561a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -575,6 +575,27 @@ static void icl_tc_port_assert_ref_held(struct
> > drm_i915_private *dev_priv,
> >
> > #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) -
> > TGL_PW_CTL_IDX_AUX_TC1)
> >
> > +static void icl_tc_cold_exit(struct drm_i915_private *i915)
> > +{
> > + const ktime_t timeout = ktime_add_ms(ktime_get_raw(), 5);
> > + int ret;
> > +
> > + do {
> > + ret = sandybridge_pcode_write_timeout(i915,
> > + ICL_PCODE_EXIT_TC
> > COLD,
> > + 0, 250, 1);
> > + if (ret == -EAGAIN)
> > + msleep(1);
> > + } while (ret == -EAGAIN && ktime_compare(timeout,
> > ktime_get_raw()) > 0);
>
> this could exit after a single pcode_write() that polled for 1ms, and
> msleep(1); is not needed in the last iteration. Retrying 3 times as
> discussed earlier would solve that.
>
> > +
> > + /* Spec states that TC cold exit can take up to 1ms to complete
> > */
> > + if (!ret)
> > + msleep(1);
> > +
> > + drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
> > + "succeeded");
>
> You missed turning this to an error.
Can we postpone this at least for ICL?
The ICL machines in CI don't have
the IFWI that have this PCODE command, so it is failing.
I have asked to
CI team do update but it is going to take a while. VLK-9040
>
> > +}
> > +
> > static void
> > icl_tc_phy_aux_power_well_enable(struct drm_i915_private
> > *dev_priv,
> > struct i915_power_well *power_well)
> > @@ -593,7 +614,8 @@ icl_tc_phy_aux_power_well_enable(struct
> > drm_i915_private *dev_priv,
> >
> > hsw_power_well_enable_prepare(dev_priv, power_well);
> >
> > - /* TODO ICL TC cold handling */
> > + if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
> > + icl_tc_cold_exit(dev_priv);
> >
> > hsw_power_well_enable_complete(dev_priv, power_well);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 9b850c11aa78..74061bf9b2b9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -34,6 +34,7 @@ tc_port_load_fia_params(struct drm_i915_private
> > *i915,
> > if (INTEL_INFO(i915)->display.has_modular_fia) {
> > modular_fia = intel_uncore_read(&i915->uncore,
> > PORT_TX_DFLEXDPSP(FIA1)
> > );
> > + drm_WARN_ON(&i915->drm, modular_fia == 0xffffffff);
> > modular_fia &= MODULAR_FIA_MASK;
> > } else {
> > modular_fia = 0;
> > @@ -52,6 +53,37 @@ tc_port_load_fia_params(struct drm_i915_private
> > *i915,
> > }
> > }
> >
> > +static intel_wakeref_t
> > +tc_cold_block(struct intel_digital_port *dig_port)
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > + enum intel_display_power_domain domain;
> > +
> > + if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
> > + return 0;
> > +
> > + domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> > + return intel_display_power_get(i915, domain);
> > +}
> > +
> > +static void
> > +tc_cold_unblock(struct intel_digital_port *dig_port,
> > intel_wakeref_t wakeref)
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > + enum intel_display_power_domain domain;
> > +
> > + /*
> > + * wakeref == -1, means some error happened saving
> > save_depot_stack but
> > + * power should still be put down and 0 is a invalid
> > save_depot_stack
> > + * id so can be used to skip it for non TC legacy ports.
> > + */
> > + if (wakeref == 0)
> > + return;
> > +
> > + domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> > + intel_display_power_put_async(i915, domain, wakeref);
> > +}
> > +
> > u32 intel_tc_port_get_lane_mask(struct intel_digital_port
> > *dig_port)
> > {
> > struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > @@ -415,9 +447,14 @@ static void intel_tc_port_reset_mode(struct
> > intel_digital_port *dig_port,
> > enum tc_port_mode old_tc_mode = dig_port->tc_mode;
> >
> > intel_display_power_flush_work(i915);
> > - drm_WARN_ON(&i915->drm,
> > - intel_display_power_is_enabled(i915,
> > - intel_aux_power_domain(dig_port
> > )));
> > + if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port) {
> > + enum intel_display_power_domain aux_domain;
> > + bool aux_powered;
> > +
> > + aux_domain = intel_aux_power_domain(dig_port);
> > + aux_powered = intel_display_power_is_enabled(i915,
> > aux_domain);
> > + drm_WARN_ON(&i915->drm, aux_powered);
> > + }
> >
> > icl_tc_phy_disconnect(dig_port);
> > icl_tc_phy_connect(dig_port, required_lanes);
> > @@ -439,9 +476,11 @@ intel_tc_port_link_init_refcount(struct
> > intel_digital_port *dig_port,
> > void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
> > {
> > struct intel_encoder *encoder = &dig_port->base;
> > + intel_wakeref_t tc_cold_wref;
> > int active_links = 0;
> >
> > mutex_lock(&dig_port->tc_lock);
> > + tc_cold_wref = tc_cold_block(dig_port);
> >
> > dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
> > if (dig_port->dp.is_mst)
> > @@ -466,6 +505,7 @@ void intel_tc_port_sanitize(struct
> > intel_digital_port *dig_port)
> > dig_port->tc_port_name,
> > tc_port_mode_name(dig_port->tc_mode));
> >
> > + tc_cold_unblock(dig_port, tc_cold_wref);
> > mutex_unlock(&dig_port->tc_lock);
> > }
> >
> > @@ -487,10 +527,15 @@ static bool intel_tc_port_needs_reset(struct
> > intel_digital_port *dig_port)
> > bool intel_tc_port_connected(struct intel_digital_port *dig_port)
> > {
> > bool is_connected;
> > + intel_wakeref_t tc_cold_wref;
> >
> > intel_tc_port_lock(dig_port);
> > + tc_cold_wref = tc_cold_block(dig_port);
> > +
> > is_connected = tc_port_live_status_mask(dig_port) &
> > BIT(dig_port->tc_mode);
> > +
> > + tc_cold_unblock(dig_port, tc_cold_wref);
> > intel_tc_port_unlock(dig_port);
> >
> > return is_connected;
> > @@ -506,9 +551,16 @@ static void __intel_tc_port_lock(struct
> > intel_digital_port *dig_port,
> >
> > mutex_lock(&dig_port->tc_lock);
> >
> > - if (!dig_port->tc_link_refcount &&
> > - intel_tc_port_needs_reset(dig_port))
> > - intel_tc_port_reset_mode(dig_port, required_lanes);
> > + if (!dig_port->tc_link_refcount) {
> > + intel_wakeref_t tc_cold_wref;
> > +
> > + tc_cold_wref = tc_cold_block(dig_port);
> > +
> > + if (intel_tc_port_needs_reset(dig_port))
> > + intel_tc_port_reset_mode(dig_port,
> > required_lanes);
> > +
> > + tc_cold_unblock(dig_port, tc_cold_wref);
> > + }
> >
> > drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
> > dig_port->tc_lock_wakeref = wakeref;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 1a7bd6db164b..0389afa2361f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9108,6 +9108,7 @@ enum {
> > #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((poin
> > t) << 16) | (0x1 << 8))
> > #define GEN6_PCODE_READ_D_COMP 0x10
> > #define GEN6_PCODE_WRITE_D_COMP 0x11
> > +#define ICL_PCODE_EXIT_TCCOLD 0x12
> > #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> > #define DISPLAY_IPS_CONTROL 0x19
> > /* See also IPS_CTL */
> > --
> > 2.26.0
> >
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^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v3 4/8] drm/i915/tc/icl: Implement TC cold sequences
2020-04-07 22:20 ` Souza, Jose
@ 2020-04-07 22:43 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2020-04-07 22:43 UTC (permalink / raw)
To: Souza, Jose
Cc: Chiou, Cooper, intel-gfx@lists.freedesktop.org,
kai.heng.feng@canonical.com
On Wed, Apr 08, 2020 at 01:20:02AM +0300, Souza, Jose wrote:
> [...]
> > > + drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
> > > + "succeeded");
> >
> > You missed turning this to an error.
>
> Can we postpone this at least for ICL?
>
> The ICL machines in CI don't have the IFWI that have this PCODE
> command, so it is failing. I have asked to CI team do update but it
> is going to take a while. VLK-9040
Ah, yes it's ok. Please also add a FIXME: then.
--Imre
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v3 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
` (2 preceding siblings ...)
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 4/8] drm/i915/tc/icl: Implement TC cold sequences José Roberto de Souza
@ 2020-04-07 21:39 ` José Roberto de Souza
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 6/8] drm/i915/tc/tgl: Implement TC cold sequences José Roberto de Souza
` (6 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: José Roberto de Souza @ 2020-04-07 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: You-Sheng Yang
As part of ICL TC cold exit sequences we need to request aux power
well before lock the access to TC ports, so skiping the
intel_tc_port_ref_held() check for TC legacy ports.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2d7b2999561a..81b968b8c397 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -560,6 +560,9 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
if (drm_WARN_ON(&dev_priv->drm, !dig_port))
return;
+ if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
+ return;
+
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
}
--
2.26.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [Intel-gfx] [PATCH v3 6/8] drm/i915/tc/tgl: Implement TC cold sequences
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
` (3 preceding siblings ...)
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 5/8] drm/i915/tc: Skip ref held check for TC legacy aux power wells José Roberto de Souza
@ 2020-04-07 21:39 ` José Roberto de Souza
2020-04-07 22:12 ` Imre Deak
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux José Roberto de Souza
` (5 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: José Roberto de Souza @ 2020-04-07 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Cooper Chiou, Kai-Heng Feng
TC ports can enter in TCCOLD to save power and is required to request
to PCODE to exit this state before use or read to TC registers.
For TGL there is a new MBOX command to do that with a parameter to ask
PCODE to exit and block TCCOLD entry or unblock TCCOLD entry.
So adding a new power domain to reuse the refcount and only allow
TC cold when all TC ports are not in use.
v2:
- fixed missing case in intel_display_power_domain_str()
- moved tgl_tc_cold_request to intel_display_power.c
- renamed TGL_TC_COLD_OFF to TGL_TC_COLD_OFF_POWER_DOMAINS
- added all TC and TBT aux power domains to
TGL_TC_COLD_OFF_POWER_DOMAINS
v3:
- added one msec sleep when PCODE returns -EAGAIN
- added timeout of 5msec to not loop forever if
sandybridge_pcode_write_timeout() keeps returning -EAGAIN
BSpec: 49294
Cc: Imre Deak <imre.deak@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
.../drm/i915/display/intel_display_power.c | 104 ++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/display/intel_tc.c | 17 ++-
drivers/gpu/drm/i915/i915_reg.h | 4 +
4 files changed, 123 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 81b968b8c397..0be6757f797c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -151,6 +151,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "GT_IRQ";
case POWER_DOMAIN_DPLL_DC_OFF:
return "DPLL_DC_OFF";
+ case POWER_DOMAIN_TC_COLD_OFF:
+ return "TC_COLD_OFF";
default:
MISSING_CASE(domain);
return "?";
@@ -2860,6 +2862,21 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
+#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_AUX_G) | \
+ BIT_ULL(POWER_DOMAIN_AUX_H) | \
+ BIT_ULL(POWER_DOMAIN_AUX_I) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
+ BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -3962,6 +3979,87 @@ static const struct i915_power_well_desc ehl_power_wells[] = {
},
};
+static void
+tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
+{
+ const ktime_t timeout = ktime_add_ms(ktime_get_raw(), 5);
+ u8 tries = 0;
+ int ret;
+
+ do {
+ u32 low_val = 0, high_val;
+
+ if (block)
+ high_val = TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ;
+ else
+ high_val = TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ;
+
+ /*
+ * Spec states that we should timeout the request after 200us
+ * but the function below will timeout after 500us
+ */
+ ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
+ &high_val);
+ if (ret == 0) {
+ if (block &&
+ (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
+ ret = -EIO;
+ else
+ break;
+ }
+
+ if (ret == -EAGAIN)
+ msleep(1);
+ else
+ tries++;
+ } while (tries < 3 && ktime_compare(timeout, ktime_get_raw()) > 0);
+
+ drm_dbg_kms(&i915->drm, "TC cold %sblock %s\n", block ? "" : "un",
+ ret ? "failed" : "succeeded");
+}
+
+static void
+tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
+ struct i915_power_well *power_well)
+{
+ tgl_tc_cold_request(i915, true);
+}
+
+static void
+tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
+ struct i915_power_well *power_well)
+{
+ tgl_tc_cold_request(i915, false);
+}
+
+static void
+tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
+ struct i915_power_well *power_well)
+{
+ if (power_well->count > 0)
+ tgl_tc_cold_off_power_well_enable(i915, power_well);
+ else
+ tgl_tc_cold_off_power_well_disable(i915, power_well);
+}
+
+static bool
+tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ /*
+ * Not the correctly implementation but there is no way to just read it
+ * from PCODE, so returning count to avoid state mismatch errors
+ */
+ return power_well->count;
+}
+
+static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
+ .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
+ .enable = tgl_tc_cold_off_power_well_enable,
+ .disable = tgl_tc_cold_off_power_well_disable,
+ .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
+};
+
static const struct i915_power_well_desc tgl_power_wells[] = {
{
.name = "always-on",
@@ -4289,6 +4387,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.irq_pipe_mask = BIT(PIPE_D),
},
},
+ {
+ .name = "TC cold off",
+ .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
+ .ops = &tgl_tc_cold_off_ops,
+ .id = DISP_PW_ID_NONE,
+ },
};
static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..070457e7b948 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -76,6 +76,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
POWER_DOMAIN_DPLL_DC_OFF,
+ POWER_DOMAIN_TC_COLD_OFF,
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 74061bf9b2b9..ab87186b7e4b 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -53,16 +53,27 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
}
}
+static enum intel_display_power_domain
+tc_cold_get_power_domain(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ if (INTEL_GEN(i915) == 11)
+ return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+ else
+ return POWER_DOMAIN_TC_COLD_OFF;
+}
+
static intel_wakeref_t
tc_cold_block(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum intel_display_power_domain domain;
- if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
+ if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
return 0;
- domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+ domain = tc_cold_get_power_domain(dig_port);
return intel_display_power_get(i915, domain);
}
@@ -80,7 +91,7 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
if (wakeref == 0)
return;
- domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+ domain = tc_cold_get_power_domain(dig_port);
intel_display_power_put_async(i915, domain, wakeref);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0389afa2361f..4ae1b6dfa18e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9111,6 +9111,10 @@ enum {
#define ICL_PCODE_EXIT_TCCOLD 0x12
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
#define DISPLAY_IPS_CONTROL 0x19
+#define TGL_PCODE_TCCOLD 0x26
+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
+#define TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ 0
+#define TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ REG_BIT(0)
/* See also IPS_CTL */
#define IPS_PCODE_CONTROL (1 << 30)
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
--
2.26.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v3 6/8] drm/i915/tc/tgl: Implement TC cold sequences
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 6/8] drm/i915/tc/tgl: Implement TC cold sequences José Roberto de Souza
@ 2020-04-07 22:12 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2020-04-07 22:12 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: Cooper Chiou, intel-gfx, Kai-Heng Feng
On Tue, Apr 07, 2020 at 02:39:58PM -0700, José Roberto de Souza wrote:
> TC ports can enter in TCCOLD to save power and is required to request
> to PCODE to exit this state before use or read to TC registers.
>
> For TGL there is a new MBOX command to do that with a parameter to ask
> PCODE to exit and block TCCOLD entry or unblock TCCOLD entry.
>
> So adding a new power domain to reuse the refcount and only allow
> TC cold when all TC ports are not in use.
>
> v2:
> - fixed missing case in intel_display_power_domain_str()
> - moved tgl_tc_cold_request to intel_display_power.c
> - renamed TGL_TC_COLD_OFF to TGL_TC_COLD_OFF_POWER_DOMAINS
> - added all TC and TBT aux power domains to
> TGL_TC_COLD_OFF_POWER_DOMAINS
>
> v3:
> - added one msec sleep when PCODE returns -EAGAIN
> - added timeout of 5msec to not loop forever if
> sandybridge_pcode_write_timeout() keeps returning -EAGAIN
>
> BSpec: 49294
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 104 ++++++++++++++++++
> .../drm/i915/display/intel_display_power.h | 1 +
> drivers/gpu/drm/i915/display/intel_tc.c | 17 ++-
> drivers/gpu/drm/i915/i915_reg.h | 4 +
> 4 files changed, 123 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 81b968b8c397..0be6757f797c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -151,6 +151,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> return "GT_IRQ";
> case POWER_DOMAIN_DPLL_DC_OFF:
> return "DPLL_DC_OFF";
> + case POWER_DOMAIN_TC_COLD_OFF:
> + return "TC_COLD_OFF";
> default:
> MISSING_CASE(domain);
> return "?";
> @@ -2860,6 +2862,21 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> #define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
>
> +#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> + BIT_ULL(POWER_DOMAIN_AUX_G) | \
> + BIT_ULL(POWER_DOMAIN_AUX_H) | \
> + BIT_ULL(POWER_DOMAIN_AUX_I) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
> + BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> +
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> .enable = i9xx_always_on_power_well_noop,
> @@ -3962,6 +3979,87 @@ static const struct i915_power_well_desc ehl_power_wells[] = {
> },
> };
>
> +static void
> +tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
> +{
> + const ktime_t timeout = ktime_add_ms(ktime_get_raw(), 5);
> + u8 tries = 0;
> + int ret;
> +
> + do {
> + u32 low_val = 0, high_val;
> +
> + if (block)
> + high_val = TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ;
> + else
> + high_val = TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ;
> +
> + /*
> + * Spec states that we should timeout the request after 200us
> + * but the function below will timeout after 500us
> + */
> + ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
> + &high_val);
> + if (ret == 0) {
> + if (block &&
> + (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
> + ret = -EIO;
> + else
> + break;
> + }
> +
> + if (ret == -EAGAIN)
> + msleep(1);
> + else
> + tries++;
> + } while (tries < 3 && ktime_compare(timeout, ktime_get_raw()) > 0);
Similarly to ICL should be just:
while (1) {
...
if (!ret || ++tries == 3)
break;
if (ret == -EAGAIN)
msleep(1);
}
> +
> + drm_dbg_kms(&i915->drm, "TC cold %sblock %s\n", block ? "" : "un",
> + ret ? "failed" : "succeeded");
ret!=0 should be an error.
> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
> + struct i915_power_well *power_well)
> +{
> + tgl_tc_cold_request(i915, true);
> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
> + struct i915_power_well *power_well)
> +{
> + tgl_tc_cold_request(i915, false);
> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
> + struct i915_power_well *power_well)
> +{
> + if (power_well->count > 0)
> + tgl_tc_cold_off_power_well_enable(i915, power_well);
> + else
> + tgl_tc_cold_off_power_well_disable(i915, power_well);
> +}
> +
> +static bool
> +tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + /*
> + * Not the correctly implementation but there is no way to just read it
> + * from PCODE, so returning count to avoid state mismatch errors
> + */
> + return power_well->count;
> +}
> +
> +static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
> + .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
> + .enable = tgl_tc_cold_off_power_well_enable,
> + .disable = tgl_tc_cold_off_power_well_disable,
> + .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
> +};
> +
> static const struct i915_power_well_desc tgl_power_wells[] = {
> {
> .name = "always-on",
> @@ -4289,6 +4387,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> .hsw.irq_pipe_mask = BIT(PIPE_D),
> },
> },
> + {
> + .name = "TC cold off",
> + .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> + .ops = &tgl_tc_cold_off_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> };
>
> static int
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index da64a5edae7a..070457e7b948 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -76,6 +76,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> POWER_DOMAIN_DPLL_DC_OFF,
> + POWER_DOMAIN_TC_COLD_OFF,
> POWER_DOMAIN_INIT,
>
> POWER_DOMAIN_NUM,
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 74061bf9b2b9..ab87186b7e4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -53,16 +53,27 @@ tc_port_load_fia_params(struct drm_i915_private *i915,
> }
> }
>
> +static enum intel_display_power_domain
> +tc_cold_get_power_domain(struct intel_digital_port *dig_port)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +
> + if (INTEL_GEN(i915) == 11)
> + return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> + else
> + return POWER_DOMAIN_TC_COLD_OFF;
> +}
> +
> static intel_wakeref_t
> tc_cold_block(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> enum intel_display_power_domain domain;
>
> - if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port)
> + if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
> return 0;
>
> - domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> + domain = tc_cold_get_power_domain(dig_port);
> return intel_display_power_get(i915, domain);
> }
>
> @@ -80,7 +91,7 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
> if (wakeref == 0)
> return;
>
> - domain = intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> + domain = tc_cold_get_power_domain(dig_port);
> intel_display_power_put_async(i915, domain, wakeref);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0389afa2361f..4ae1b6dfa18e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9111,6 +9111,10 @@ enum {
> #define ICL_PCODE_EXIT_TCCOLD 0x12
> #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> #define DISPLAY_IPS_CONTROL 0x19
> +#define TGL_PCODE_TCCOLD 0x26
> +#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
> +#define TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ 0
> +#define TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ REG_BIT(0)
> /* See also IPS_CTL */
> #define IPS_PCODE_CONTROL (1 << 30)
> #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
> --
> 2.26.0
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v3 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
` (4 preceding siblings ...)
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 6/8] drm/i915/tc/tgl: Implement TC cold sequences José Roberto de Souza
@ 2020-04-07 21:39 ` José Roberto de Souza
2020-04-07 21:40 ` [Intel-gfx] [PATCH v3 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout José Roberto de Souza
` (4 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: José Roberto de Souza @ 2020-04-07 21:39 UTC (permalink / raw)
To: intel-gfx; +Cc: You-Sheng Yang
As described in "drm/i915/tc/icl: Implement TC cold sequences" users
of TC functions should held aux power well during access to avoid
read garbage due HW in TC cold state.
v3:
- renamed is_tc_cold_blocked() to assert_tc_cold_blocked()
- restored the removed 0xffffffff checks
Reviewed-by: Imre Deak <imre.deak@intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index ab87186b7e4b..a71de48b053f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -95,6 +95,20 @@ tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
intel_display_power_put_async(i915, domain, wakeref);
}
+static void
+assert_tc_cold_blocked(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ bool enabled;
+
+ if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
+ return;
+
+ enabled = intel_display_power_is_enabled(i915,
+ tc_cold_get_power_domain(dig_port));
+ drm_WARN_ON(&i915->drm, !enabled);
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -105,6 +119,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
+ assert_tc_cold_blocked(dig_port);
lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
@@ -120,6 +135,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
+ assert_tc_cold_blocked(dig_port);
return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
@@ -134,6 +150,8 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
if (dig_port->tc_mode != TC_PORT_DP_ALT)
return 4;
+ assert_tc_cold_blocked(dig_port);
+
lane_mask = 0;
with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
lane_mask = intel_tc_port_get_lane_mask(dig_port);
@@ -166,6 +184,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
drm_WARN_ON(&i915->drm,
lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
+ assert_tc_cold_blocked(dig_port);
+
val = intel_uncore_read(uncore,
PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
--
2.26.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Intel-gfx] [PATCH v3 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
` (5 preceding siblings ...)
2020-04-07 21:39 ` [Intel-gfx] [PATCH v3 7/8] drm/i915/tc: Catch TC users accessing FIA registers without enable aux José Roberto de Souza
@ 2020-04-07 21:40 ` José Roberto de Souza
2020-04-07 22:31 ` Imre Deak
2020-04-07 21:58 ` [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch Imre Deak
` (3 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: José Roberto de Souza @ 2020-04-07 21:40 UTC (permalink / raw)
To: intel-gfx
This is a expected timeout of static TC ports not conneceted, so
not throwing warnings that would taint CI.
v3:
- moved checks to tc_phy_aux_timeout_expected()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
.../drm/i915/display/intel_display_power.c | 50 +++++++++++++------
1 file changed, 34 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0be6757f797c..fa7521f7680d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -284,6 +284,21 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
}
+#define ICL_AUX_PW_TO_CH(pw_idx) \
+ ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
+
+#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
+ ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
+
+static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ int pw_idx = power_well->desc->hsw.idx;
+
+ return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
+ ICL_AUX_PW_TO_CH(pw_idx);
+}
+
static struct intel_digital_port *
aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
enum aux_ch aux_ch)
@@ -311,6 +326,22 @@ aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
return dig_port;
}
+static bool tc_phy_aux_timeout_expected(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (power_well->desc->hsw.is_tc_tbt)
+ return true;
+
+ if (INTEL_GEN(dev_priv) == 11) {
+ enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
+ struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
+
+ return dig_port->tc_legacy_port;
+ }
+
+ return false;
+}
+
static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -324,7 +355,9 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
power_well->desc->name);
/* An AUX timeout is expected if the TBT DP tunnel is down. */
- drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt);
+ drm_WARN_ON(&dev_priv->drm,
+ !tc_phy_aux_timeout_expected(dev_priv, power_well));
+
}
}
@@ -520,21 +553,6 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
hsw_wait_for_power_well_disable(dev_priv, power_well);
}
-#define ICL_AUX_PW_TO_CH(pw_idx) \
- ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
-
-#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
- ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
-
-static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- int pw_idx = power_well->desc->hsw.idx;
-
- return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
- ICL_AUX_PW_TO_CH(pw_idx);
-}
-
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
--
2.26.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v3 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout
2020-04-07 21:40 ` [Intel-gfx] [PATCH v3 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout José Roberto de Souza
@ 2020-04-07 22:31 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2020-04-07 22:31 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Apr 07, 2020 at 02:40:00PM -0700, José Roberto de Souza wrote:
> This is a expected timeout of static TC ports not conneceted, so
> not throwing warnings that would taint CI.
>
> v3:
> - moved checks to tc_phy_aux_timeout_expected()
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 50 +++++++++++++------
> 1 file changed, 34 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0be6757f797c..fa7521f7680d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -284,6 +284,21 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
> gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
> }
>
> +#define ICL_AUX_PW_TO_CH(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> +
> +#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> +
> +static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + int pw_idx = power_well->desc->hsw.idx;
> +
> + return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> + ICL_AUX_PW_TO_CH(pw_idx);
> +}
> +
> static struct intel_digital_port *
> aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> enum aux_ch aux_ch)
> @@ -311,6 +326,22 @@ aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> return dig_port;
> }
>
> +static bool tc_phy_aux_timeout_expected(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + if (power_well->desc->hsw.is_tc_tbt)
> + return true;
> +
> + if (INTEL_GEN(dev_priv) == 11) {
if (GEN==11 && power_well->desc->ops == &icl_tc_phy_aux_power_well_ops) {
> + enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> + struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
> +
> + return dig_port->tc_legacy_port;
> + }
> +
> + return false;
> +}
> +
> static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> @@ -324,7 +355,9 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> power_well->desc->name);
>
> /* An AUX timeout is expected if the TBT DP tunnel is down. */
The comment is now misplaced.
> - drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt);
> + drm_WARN_ON(&dev_priv->drm,
> + !tc_phy_aux_timeout_expected(dev_priv, power_well));
> +
> }
> }
>
> @@ -520,21 +553,6 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>
> -#define ICL_AUX_PW_TO_CH(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> -
> -#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> -
> -static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - int pw_idx = power_well->desc->hsw.idx;
> -
> - return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> - ICL_AUX_PW_TO_CH(pw_idx);
> -}
> -
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
>
> static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
> --
> 2.26.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
` (6 preceding siblings ...)
2020-04-07 21:40 ` [Intel-gfx] [PATCH v3 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout José Roberto de Souza
@ 2020-04-07 21:58 ` Imre Deak
2020-04-07 22:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/8] " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2020-04-07 21:58 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: You-Sheng Yang, intel-gfx, You-Sheng Yang
On Tue, Apr 07, 2020 at 02:39:53PM -0700, José Roberto de Souza wrote:
> Moving the code to return the digital port of the aux channel also
> removing the intel_phy_is_tc() to make it generic.
> digital_port will be needed in icl_tc_phy_aux_power_well_enable()
> so adding it as a parameter to icl_tc_port_assert_ref_held().
>
> While at at removing the duplicated call to icl_tc_phy_aux_ch() in
> icl_tc_port_assert_ref_held().
>
> v2:
> - fixed build when DRM_I915_DEBUG_RUNTIME_PM is not set
> - moved to before hsw_wait_for_power_well_enable() as it will be
> needed by hsw_wait_for_power_well_enable() in a future patch
>
> Cc: You-Sheng Yang <vicamo@gmail.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 69 ++++++++++---------
> 1 file changed, 37 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 433e5a81dd4d..5a8b94d9a10f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -282,6 +282,33 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
> gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
> }
>
> +static struct intel_digital_port *
> +aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> + enum aux_ch aux_ch)
> +{
> + struct intel_digital_port *dig_port = NULL;
> + struct intel_encoder *encoder;
> +
> + for_each_intel_encoder(&dev_priv->drm, encoder) {
> + /* We'll check the MST primary port */
> + if (encoder->type == INTEL_OUTPUT_DP_MST)
> + continue;
> +
> + dig_port = enc_to_dig_port(encoder);
> + if (!dig_port)
> + return NULL;
continue;
> +
> + if (dig_port->aux_ch != aux_ch) {
> + dig_port = NULL;
> + continue;
> + }
> +
> + break;
> + }
> +
> + return dig_port;
> +}
> +
> static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> @@ -501,41 +528,14 @@ static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
> }
>
> static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> + struct i915_power_well *power_well,
> + struct intel_digital_port *dig_port)
> {
> - enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> - struct intel_digital_port *dig_port = NULL;
> - struct intel_encoder *encoder;
> -
> /* Bypass the check if all references are released asynchronously */
> if (power_well_async_ref_count(dev_priv, power_well) ==
> power_well->count)
> return;
>
> - aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> -
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> - enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -
> - if (!intel_phy_is_tc(dev_priv, phy))
> - continue;
> -
> - /* We'll check the MST primary port */
> - if (encoder->type == INTEL_OUTPUT_DP_MST)
> - continue;
> -
> - dig_port = enc_to_dig_port(encoder);
> - if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> - continue;
> -
> - if (dig_port->aux_ch != aux_ch) {
> - dig_port = NULL;
> - continue;
> - }
> -
> - break;
> - }
> -
> if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> return;
>
> @@ -545,7 +545,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> #else
>
> static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> + struct i915_power_well *power_well,
> + struct intel_digital_port *dig_port)
> {
> }
>
> @@ -558,9 +559,10 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> + struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
> u32 val;
>
> - icl_tc_port_assert_ref_held(dev_priv, power_well);
> + icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
>
> val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
> val &= ~DP_AUX_CH_CTL_TBT_IO;
> @@ -588,7 +590,10 @@ static void
> icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - icl_tc_port_assert_ref_held(dev_priv, power_well);
> + enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> + struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
> +
> + icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
>
> hsw_power_well_disable(dev_priv, power_well);
> }
> --
> 2.26.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
` (7 preceding siblings ...)
2020-04-07 21:58 ` [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch Imre Deak
@ 2020-04-07 22:24 ` Patchwork
2020-04-07 22:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-08 8:01 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-04-07 22:24 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
URL : https://patchwork.freedesktop.org/series/75634/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
22b6e464a90d drm/i915/display: Move out code to return the digital_port of the aux ch
9c3fa6a23124 drm/i915/display: Add intel_legacy_aux_to_power_domain()
4dbbf93cee79 drm/i915/display: Split hsw_power_well_enable() into two
347c828f0667 drm/i915/tc/icl: Implement TC cold sequences
-:70: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#70: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:588:
+ msleep(1);
-:75: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#75: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:593:
+ msleep(1);
total: 0 errors, 2 warnings, 0 checks, 156 lines checked
ea6e310ec8f8 drm/i915/tc: Skip ref held check for TC legacy aux power wells
5669e5b93c7d drm/i915/tc/tgl: Implement TC cold sequences
-:105: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#105: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:4012:
+ msleep(1);
total: 0 errors, 1 warnings, 0 checks, 182 lines checked
dd02c59c32fa drm/i915/tc: Catch TC users accessing FIA registers without enable aux
ac28d19b74b5 drm/i915/tc: Do not warn when aux power well of static TC ports timeout
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
` (8 preceding siblings ...)
2020-04-07 22:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/8] " Patchwork
@ 2020-04-07 22:48 ` Patchwork
2020-04-08 8:01 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-04-07 22:48 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
URL : https://patchwork.freedesktop.org/series/75634/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8269 -> Patchwork_17240
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/index.html
Known issues
------------
Here are the changes found in Patchwork_17240 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][1] ([i915#203]) -> [PASS][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-skl-6770hq: [SKIP][3] ([fdo#109271]) -> [PASS][4] +5 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-skl-6770hq: [DMESG-WARN][5] ([i915#106]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [DMESG-FAIL][7] ([i915#62] / [i915#95]) -> [SKIP][8] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +11 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106
[i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (53 -> 46)
------------------------------
Additional (1): fi-kbl-r
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8269 -> Patchwork_17240
CI-20190529: 20190529
CI_DRM_8269: 301d0427e2e3108839bf6c36f58dd0b2b5258c25 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5577: 7ee7e86fd79e4dbb6300ef4c23e50cb699216ae2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17240: ac28d19b74b57a30e2b16df66210bbf404f51a40 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ac28d19b74b5 drm/i915/tc: Do not warn when aux power well of static TC ports timeout
dd02c59c32fa drm/i915/tc: Catch TC users accessing FIA registers without enable aux
5669e5b93c7d drm/i915/tc/tgl: Implement TC cold sequences
ea6e310ec8f8 drm/i915/tc: Skip ref held check for TC legacy aux power wells
347c828f0667 drm/i915/tc/icl: Implement TC cold sequences
4dbbf93cee79 drm/i915/display: Split hsw_power_well_enable() into two
9c3fa6a23124 drm/i915/display: Add intel_legacy_aux_to_power_domain()
22b6e464a90d drm/i915/display: Move out code to return the digital_port of the aux ch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
2020-04-07 21:39 [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Move out code to return the digital_port of the aux ch José Roberto de Souza
` (9 preceding siblings ...)
2020-04-07 22:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-04-08 8:01 ` Patchwork
10 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2020-04-08 8:01 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
URL : https://patchwork.freedesktop.org/series/75634/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8269_full -> Patchwork_17240_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17240_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_params@invalid-bsd-ring:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb4/igt@gem_exec_params@invalid-bsd-ring.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-iclb5/igt@gem_exec_params@invalid-bsd-ring.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#1119])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-glk9/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-glk6/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#1188])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-iclb1/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#69])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-skl8/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
#### Possible fixes ####
* igt@kms_cursor_crc@pipe-a-cursor-alpha-transparent:
- shard-snb: [SKIP][17] ([fdo#109271]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-snb7/igt@kms_cursor_crc@pipe-a-cursor-alpha-transparent.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-snb6/igt@kms_cursor_crc@pipe-a-cursor-alpha-transparent.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20] +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [FAIL][21] ([i915#79]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][23] ([i915#180] / [i915#95]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][25] ([i915#1188]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl6/igt@kms_hdr@bpc-switch.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-skl4/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][27] ([fdo#108145] / [i915#265]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][29] ([i915#173]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb1/igt@kms_psr@no_drrs.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-iclb8/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb6/igt@kms_psr@psr2_sprite_mmap_gtt.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][33] ([i915#31]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-apl1/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-apl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][35] ([i915#69]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl6/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-skl6/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][37] ([i915#588]) -> [SKIP][38] ([i915#658])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
- shard-snb: [SKIP][39] ([fdo#109271]) -> [INCOMPLETE][40] ([i915#82])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-snb1/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-snb1/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: [FAIL][41] ([fdo#108145] / [i915#265]) -> [FAIL][42] ([fdo#108145] / [i915#265] / [i915#95])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][43] ([fdo#109642] / [fdo#111068]) -> [FAIL][44] ([i915#608])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb3/igt@kms_psr2_su@page_flip.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/shard-iclb2/igt@kms_psr2_su@page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8269 -> Patchwork_17240
CI-20190529: 20190529
CI_DRM_8269: 301d0427e2e3108839bf6c36f58dd0b2b5258c25 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5577: 7ee7e86fd79e4dbb6300ef4c23e50cb699216ae2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17240: ac28d19b74b57a30e2b16df66210bbf404f51a40 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17240/index.html
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Intel-gfx@lists.freedesktop.org
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