From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/6] drm/i915/dp_mst: Move clearing the ACT sent flag closer to its polling
Date: Tue, 16 Jun 2020 18:47:02 +0300 [thread overview]
Message-ID: <20200616154702.GA6112@intel.com> (raw)
In-Reply-To: <20200616141855.746-3-imre.deak@intel.com>
On Tue, Jun 16, 2020 at 05:18:52PM +0300, Imre Deak wrote:
> During transcoder enabling we'll configure the transcoder in MST mode
> and enable the VC payload allocation, which will start the ACT sequence.
> Before waiting for the ACT sequence completion, we need to clear the ACT
> sent flag, but based on the above we can do this right before enabling
> the transcoder.
>
> For clarity, move the flag clearing closer to where we wait for it.
>
> While at it also factor out some common code.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 36 +++++++++++++--------
> 1 file changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2e6c6375a23b..3977ee4f7176 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -317,6 +317,25 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
> return ret;
> }
>
> +static void clear_act_sent(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + intel_de_write(i915, intel_dp->regs.dp_tp_status,
> + intel_de_read(i915, intel_dp->regs.dp_tp_status));
> +}
> +
> +static void wait_for_act_sent(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + if (intel_de_wait_for_set(i915, intel_dp->regs.dp_tp_status,
> + DP_TP_STATUS_ACT_SENT, 1))
> + drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
> +
> + drm_dp_check_act_status(&intel_dp->mst_mgr);
> +}
> +
> static void intel_mst_disable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state,
> @@ -377,11 +396,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
> TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
> val);
>
> - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
> - DP_TP_STATUS_ACT_SENT, 1))
> - drm_err(&dev_priv->drm,
> - "Timed out waiting for ACT sent when disabling\n");
> - drm_dp_check_act_status(&intel_dp->mst_mgr);
> + wait_for_act_sent(intel_dp);
>
> drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
>
> @@ -452,7 +467,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> int ret;
> - u32 temp;
> bool first_mst_stream;
>
> /* MST encoders are bound to a crtc, not to a connector,
> @@ -485,8 +499,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
> drm_err(&dev_priv->drm, "failed to allocate vcpi\n");
>
> intel_dp->active_mst_links++;
> - temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status);
> - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp);
>
> ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
>
> @@ -517,16 +529,14 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>
> drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
>
> + clear_act_sent(intel_dp);
> +
> intel_ddi_enable_transcoder_func(encoder, pipe_config);
>
> drm_dbg_kms(&dev_priv->drm, "active links %d\n",
> intel_dp->active_mst_links);
>
> - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
> - DP_TP_STATUS_ACT_SENT, 1))
> - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n");
> -
> - drm_dp_check_act_status(&intel_dp->mst_mgr);
> + wait_for_act_sent(intel_dp);
>
> drm_dp_update_payload_part2(&intel_dp->mst_mgr);
>
> --
> 2.23.1
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2020-06-16 15:47 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 14:18 [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders Imre Deak
2020-06-16 14:18 ` [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links Imre Deak
2020-06-16 15:22 ` Ville Syrjälä
2020-06-16 15:30 ` Imre Deak
2020-06-16 15:39 ` Ville Syrjälä
2020-06-16 15:49 ` Imre Deak
2020-06-16 16:20 ` Ville Syrjälä
2020-06-16 21:11 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-06-16 14:18 ` [Intel-gfx] [PATCH 3/6] drm/i915/dp_mst: Move clearing the ACT sent flag closer to its polling Imre Deak
2020-06-16 15:47 ` Ville Syrjälä [this message]
2020-06-16 14:18 ` [Intel-gfx] [PATCH 4/6] drm/i915/dp_mst: Clear only the ACT sent flag from DP_TP_STATUS Imre Deak
2020-06-16 15:47 ` Ville Syrjälä
2020-06-16 14:18 ` [Intel-gfx] [PATCH 5/6] drm/i915/dp_mst: Clear the ACT sent flag during encoder disabling too Imre Deak
2020-06-16 15:47 ` Ville Syrjälä
2020-06-16 14:18 ` [Intel-gfx] [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it Imre Deak
2020-06-16 15:45 ` Ville Syrjälä
2020-06-16 15:54 ` Imre Deak
2020-06-16 16:23 ` Ville Syrjälä
2020-06-16 16:40 ` Ville Syrjälä
2020-06-16 16:47 ` Imre Deak
2020-06-16 21:11 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-06-17 15:27 ` Lyude Paul
2020-06-23 7:30 ` Imre Deak
2020-06-16 15:46 ` [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders Ville Syrjälä
2020-06-16 16:32 ` Souza, Jose
2020-06-16 16:42 ` Imre Deak
2020-06-16 17:02 ` Souza, Jose
2020-06-16 17:32 ` Imre Deak
2020-06-16 19:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] " Patchwork
2020-06-16 21:11 ` [Intel-gfx] [PATCH v2 1/6] " Imre Deak
2020-06-16 22:38 ` Souza, Jose
2020-06-16 22:16 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] " Patchwork
2020-06-23 7:21 ` Imre Deak
2020-06-16 23:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders (rev4) Patchwork
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