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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915/dp_mst: Clear the ACT sent flag during encoder disabling too
Date: Tue, 16 Jun 2020 18:47:44 +0300	[thread overview]
Message-ID: <20200616154744.GC6112@intel.com> (raw)
In-Reply-To: <20200616141855.746-5-imre.deak@intel.com>

On Tue, Jun 16, 2020 at 05:18:54PM +0300, Imre Deak wrote:
> During encoder enabling we clear the flag before starting the ACT
> sequence and wait for the flag, but the clearing is missing during
> encoder disabling, add it there too. Since nothing cleared the flag
> automatically we could've run subsequent disabling steps too early.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index b66b56a070e5..9308b5920780 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -389,6 +389,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
>  
>  	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
>  
> +	clear_act_sent(intel_dp);
> +
>  	val = intel_de_read(dev_priv,
>  			    TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder));
>  	val &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> -- 
> 2.23.1

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-06-16 15:47 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-16 14:18 [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders Imre Deak
2020-06-16 14:18 ` [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links Imre Deak
2020-06-16 15:22   ` Ville Syrjälä
2020-06-16 15:30     ` Imre Deak
2020-06-16 15:39       ` Ville Syrjälä
2020-06-16 15:49         ` Imre Deak
2020-06-16 16:20           ` Ville Syrjälä
2020-06-16 21:11   ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-06-16 14:18 ` [Intel-gfx] [PATCH 3/6] drm/i915/dp_mst: Move clearing the ACT sent flag closer to its polling Imre Deak
2020-06-16 15:47   ` Ville Syrjälä
2020-06-16 14:18 ` [Intel-gfx] [PATCH 4/6] drm/i915/dp_mst: Clear only the ACT sent flag from DP_TP_STATUS Imre Deak
2020-06-16 15:47   ` Ville Syrjälä
2020-06-16 14:18 ` [Intel-gfx] [PATCH 5/6] drm/i915/dp_mst: Clear the ACT sent flag during encoder disabling too Imre Deak
2020-06-16 15:47   ` Ville Syrjälä [this message]
2020-06-16 14:18 ` [Intel-gfx] [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it Imre Deak
2020-06-16 15:45   ` Ville Syrjälä
2020-06-16 15:54     ` Imre Deak
2020-06-16 16:23       ` Ville Syrjälä
2020-06-16 16:40         ` Ville Syrjälä
2020-06-16 16:47           ` Imre Deak
2020-06-16 21:11   ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-06-17 15:27     ` Lyude Paul
2020-06-23  7:30     ` Imre Deak
2020-06-16 15:46 ` [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders Ville Syrjälä
2020-06-16 16:32 ` Souza, Jose
2020-06-16 16:42   ` Imre Deak
2020-06-16 17:02     ` Souza, Jose
2020-06-16 17:32       ` Imre Deak
2020-06-16 19:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] " Patchwork
2020-06-16 21:11 ` [Intel-gfx] [PATCH v2 1/6] " Imre Deak
2020-06-16 22:38   ` Souza, Jose
2020-06-16 22:16 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] " Patchwork
2020-06-23  7:21   ` Imre Deak
2020-06-16 23:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders (rev4) Patchwork

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