From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 29/61] drm/i915: Fix pread/pwrite to work with new locking rules.
Date: Fri, 2 Oct 2020 14:59:07 +0200 [thread overview]
Message-ID: <20201002125939.50817-30-maarten.lankhorst@linux.intel.com> (raw)
In-Reply-To: <20201002125939.50817-1-maarten.lankhorst@linux.intel.com>
We are removing obj->mm.lock, and need to take the reservation lock
before we can pin pages. Move the pinning pages into the helper, and
merge gtt pwrite/pread preparation and cleanup paths.
The fence lock is also removed; it will conflict with fence annotations,
because of memory allocations done when pagefaulting inside copy_*_user.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/gem/i915_gem_fence.c | 95 --------
drivers/gpu/drm/i915/gem/i915_gem_object.h | 5 -
drivers/gpu/drm/i915/i915_gem.c | 247 +++++++++++----------
4 files changed, 133 insertions(+), 215 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gem/i915_gem_fence.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..58d129b5a65a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -134,7 +134,6 @@ gem-y += \
gem/i915_gem_dmabuf.o \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer.o \
- gem/i915_gem_fence.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_object_blt.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_fence.c b/drivers/gpu/drm/i915/gem/i915_gem_fence.c
deleted file mode 100644
index 8ab842c80f99..000000000000
--- a/drivers/gpu/drm/i915/gem/i915_gem_fence.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * SPDX-License-Identifier: MIT
- *
- * Copyright © 2019 Intel Corporation
- */
-
-#include "i915_drv.h"
-#include "i915_gem_object.h"
-
-struct stub_fence {
- struct dma_fence dma;
- struct i915_sw_fence chain;
-};
-
-static int __i915_sw_fence_call
-stub_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
-{
- struct stub_fence *stub = container_of(fence, typeof(*stub), chain);
-
- switch (state) {
- case FENCE_COMPLETE:
- dma_fence_signal(&stub->dma);
- break;
-
- case FENCE_FREE:
- dma_fence_put(&stub->dma);
- break;
- }
-
- return NOTIFY_DONE;
-}
-
-static const char *stub_driver_name(struct dma_fence *fence)
-{
- return DRIVER_NAME;
-}
-
-static const char *stub_timeline_name(struct dma_fence *fence)
-{
- return "object";
-}
-
-static void stub_release(struct dma_fence *fence)
-{
- struct stub_fence *stub = container_of(fence, typeof(*stub), dma);
-
- i915_sw_fence_fini(&stub->chain);
-
- BUILD_BUG_ON(offsetof(typeof(*stub), dma));
- dma_fence_free(&stub->dma);
-}
-
-static const struct dma_fence_ops stub_fence_ops = {
- .get_driver_name = stub_driver_name,
- .get_timeline_name = stub_timeline_name,
- .release = stub_release,
-};
-
-struct dma_fence *
-i915_gem_object_lock_fence(struct drm_i915_gem_object *obj)
-{
- struct stub_fence *stub;
-
- assert_object_held(obj);
-
- stub = kmalloc(sizeof(*stub), GFP_KERNEL);
- if (!stub)
- return NULL;
-
- i915_sw_fence_init(&stub->chain, stub_notify);
- dma_fence_init(&stub->dma, &stub_fence_ops, &stub->chain.wait.lock,
- 0, 0);
-
- if (i915_sw_fence_await_reservation(&stub->chain,
- obj->base.resv, NULL, true,
- i915_fence_timeout(to_i915(obj->base.dev)),
- I915_FENCE_GFP) < 0)
- goto err;
-
- dma_resv_add_excl_fence(obj->base.resv, &stub->dma);
-
- return &stub->dma;
-
-err:
- stub_release(&stub->dma);
- return NULL;
-}
-
-void i915_gem_object_unlock_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence)
-{
- struct stub_fence *stub = container_of(fence, typeof(*stub), dma);
-
- i915_sw_fence_commit(&stub->chain);
-}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index c48df27d66f6..107b98a82e44 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -157,11 +157,6 @@ static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj)
dma_resv_unlock(obj->base.resv);
}
-struct dma_fence *
-i915_gem_object_lock_fence(struct drm_i915_gem_object *obj);
-void i915_gem_object_unlock_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence);
-
static inline void
i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 929a8f20cca4..4b5afb85efd1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,23 +184,38 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
struct drm_i915_gem_pwrite *args,
struct drm_file *file)
{
- void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
+ void *vaddr;
char __user *user_data = u64_to_user_ptr(args->data_ptr);
+ int ret;
+
+ ret = i915_gem_object_lock_interruptible(obj, NULL);
+ if (ret)
+ return ret;
+ ret = i915_gem_object_pin_pages(obj);
+ i915_gem_object_unlock(obj);
+ if (ret)
+ return ret;
+
+ vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
/*
* We manually control the domain here and pretend that it
* remains coherent i.e. in the GTT domain, like shmem_pwrite.
*/
i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
- if (copy_from_user(vaddr, user_data, args->size))
- return -EFAULT;
+ if (copy_from_user(vaddr, user_data, args->size)) {
+ ret = -EFAULT;
+ goto err;
+ }
drm_clflush_virt_range(vaddr, args->size);
intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
- return 0;
+err:
+ i915_gem_object_unpin_pages(obj);
+ return ret;
}
static int
@@ -330,7 +345,6 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
{
unsigned int needs_clflush;
unsigned int idx, offset;
- struct dma_fence *fence;
char __user *user_data;
u64 remain;
int ret;
@@ -339,19 +353,17 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
if (ret)
return ret;
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ goto err_unlock;
+
ret = i915_gem_object_prepare_read(obj, &needs_clflush);
- if (ret) {
- i915_gem_object_unlock(obj);
- return ret;
- }
+ if (ret)
+ goto err_unpin;
- fence = i915_gem_object_lock_fence(obj);
i915_gem_object_finish_access(obj);
i915_gem_object_unlock(obj);
- if (!fence)
- return -ENOMEM;
-
remain = args->size;
user_data = u64_to_user_ptr(args->data_ptr);
offset = offset_in_page(args->offset);
@@ -369,7 +381,13 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
offset = 0;
}
- i915_gem_object_unlock_fence(obj, fence);
+ i915_gem_object_unpin_pages(obj);
+ return ret;
+
+err_unpin:
+ i915_gem_object_unpin_pages(obj);
+err_unlock:
+ i915_gem_object_unlock(obj);
return ret;
}
@@ -397,52 +415,102 @@ gtt_user_read(struct io_mapping *mapping,
return unwritten;
}
-static int
-i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
- const struct drm_i915_gem_pread *args)
+static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
+ struct drm_mm_node *node,
+ bool write)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct i915_ggtt *ggtt = &i915->ggtt;
- intel_wakeref_t wakeref;
- struct drm_mm_node node;
- struct dma_fence *fence;
- void __user *user_data;
struct i915_vma *vma;
- u64 remain, offset;
+ struct i915_gem_ww_ctx ww;
int ret;
- wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+ i915_gem_ww_ctx_init(&ww, true);
+retry:
vma = ERR_PTR(-ENODEV);
+ ret = i915_gem_object_lock(obj, &ww);
+ if (ret)
+ goto err_ww;
+
+ ret = i915_gem_object_set_to_gtt_domain(obj, write);
+ if (ret)
+ goto err_ww;
+
if (!i915_gem_object_is_tiled(obj))
- vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
- PIN_MAPPABLE |
- PIN_NONBLOCK /* NOWARN */ |
- PIN_NOEVICT);
- if (!IS_ERR(vma)) {
- node.start = i915_ggtt_offset(vma);
- node.flags = 0;
+ vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0,
+ PIN_MAPPABLE |
+ PIN_NONBLOCK /* NOWARN */ |
+ PIN_NOEVICT);
+ if (vma == ERR_PTR(-EDEADLK)) {
+ ret = -EDEADLK;
+ goto err_ww;
+ } else if (!IS_ERR(vma)) {
+ node->start = i915_ggtt_offset(vma);
+ node->flags = 0;
} else {
- ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
+ ret = insert_mappable_node(ggtt, node, PAGE_SIZE);
if (ret)
- goto out_rpm;
- GEM_BUG_ON(!drm_mm_node_allocated(&node));
+ goto err_ww;
+ GEM_BUG_ON(!drm_mm_node_allocated(node));
+ vma = NULL;
}
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- goto out_unpin;
-
- ret = i915_gem_object_set_to_gtt_domain(obj, false);
+ ret = i915_gem_object_pin_pages(obj);
if (ret) {
- i915_gem_object_unlock(obj);
- goto out_unpin;
+ if (drm_mm_node_allocated(node)) {
+ ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
+ remove_mappable_node(ggtt, node);
+ } else {
+ i915_vma_unpin(vma);
+ }
}
- fence = i915_gem_object_lock_fence(obj);
- i915_gem_object_unlock(obj);
- if (!fence) {
- ret = -ENOMEM;
- goto out_unpin;
+err_ww:
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff(&ww);
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
+
+ return ret ? ERR_PTR(ret) : vma;
+}
+
+static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
+ struct drm_mm_node *node,
+ struct i915_vma *vma)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct i915_ggtt *ggtt = &i915->ggtt;
+
+ i915_gem_object_unpin_pages(obj);
+ if (drm_mm_node_allocated(node)) {
+ ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
+ remove_mappable_node(ggtt, node);
+ } else {
+ i915_vma_unpin(vma);
+ }
+}
+
+static int
+i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *args)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct i915_ggtt *ggtt = &i915->ggtt;
+ intel_wakeref_t wakeref;
+ struct drm_mm_node node;
+ void __user *user_data;
+ struct i915_vma *vma;
+ u64 remain, offset;
+ int ret = 0;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ vma = i915_gem_gtt_prepare(obj, &node, false);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto out_rpm;
}
user_data = u64_to_user_ptr(args->data_ptr);
@@ -479,14 +547,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
offset += page_length;
}
- i915_gem_object_unlock_fence(obj, fence);
-out_unpin:
- if (drm_mm_node_allocated(&node)) {
- ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
- remove_mappable_node(ggtt, &node);
- } else {
- i915_vma_unpin(vma);
- }
+ i915_gem_gtt_cleanup(obj, &node, vma);
out_rpm:
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
return ret;
@@ -538,15 +599,10 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
if (ret)
goto out;
- ret = i915_gem_object_pin_pages(obj);
- if (ret)
- goto out;
-
ret = i915_gem_shmem_pread(obj, args);
if (ret == -EFAULT || ret == -ENODEV)
ret = i915_gem_gtt_pread(obj, args);
- i915_gem_object_unpin_pages(obj);
out:
i915_gem_object_put(obj);
return ret;
@@ -594,11 +650,10 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
struct intel_runtime_pm *rpm = &i915->runtime_pm;
intel_wakeref_t wakeref;
struct drm_mm_node node;
- struct dma_fence *fence;
struct i915_vma *vma;
u64 remain, offset;
void __user *user_data;
- int ret;
+ int ret = 0;
if (i915_gem_object_has_struct_page(obj)) {
/*
@@ -616,37 +671,10 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
wakeref = intel_runtime_pm_get(rpm);
}
- vma = ERR_PTR(-ENODEV);
- if (!i915_gem_object_is_tiled(obj))
- vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
- PIN_MAPPABLE |
- PIN_NONBLOCK /* NOWARN */ |
- PIN_NOEVICT);
- if (!IS_ERR(vma)) {
- node.start = i915_ggtt_offset(vma);
- node.flags = 0;
- } else {
- ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
- if (ret)
- goto out_rpm;
- GEM_BUG_ON(!drm_mm_node_allocated(&node));
- }
-
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- goto out_unpin;
-
- ret = i915_gem_object_set_to_gtt_domain(obj, true);
- if (ret) {
- i915_gem_object_unlock(obj);
- goto out_unpin;
- }
-
- fence = i915_gem_object_lock_fence(obj);
- i915_gem_object_unlock(obj);
- if (!fence) {
- ret = -ENOMEM;
- goto out_unpin;
+ vma = i915_gem_gtt_prepare(obj, &node, true);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto out_rpm;
}
i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
@@ -695,14 +723,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
- i915_gem_object_unlock_fence(obj, fence);
-out_unpin:
- if (drm_mm_node_allocated(&node)) {
- ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
- remove_mappable_node(ggtt, &node);
- } else {
- i915_vma_unpin(vma);
- }
+ i915_gem_gtt_cleanup(obj, &node, vma);
out_rpm:
intel_runtime_pm_put(rpm, wakeref);
return ret;
@@ -742,7 +763,6 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
unsigned int partial_cacheline_write;
unsigned int needs_clflush;
unsigned int offset, idx;
- struct dma_fence *fence;
void __user *user_data;
u64 remain;
int ret;
@@ -751,19 +771,17 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
if (ret)
return ret;
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ goto err_unlock;
+
ret = i915_gem_object_prepare_write(obj, &needs_clflush);
- if (ret) {
- i915_gem_object_unlock(obj);
- return ret;
- }
+ if (ret)
+ goto err_unpin;
- fence = i915_gem_object_lock_fence(obj);
i915_gem_object_finish_access(obj);
i915_gem_object_unlock(obj);
- if (!fence)
- return -ENOMEM;
-
/* If we don't overwrite a cacheline completely we need to be
* careful to have up-to-date data by first clflushing. Don't
* overcomplicate things and flush the entire patch.
@@ -791,8 +809,14 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
}
i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
- i915_gem_object_unlock_fence(obj, fence);
+ i915_gem_object_unpin_pages(obj);
+ return ret;
+
+err_unpin:
+ i915_gem_object_unpin_pages(obj);
+err_unlock:
+ i915_gem_object_unlock(obj);
return ret;
}
@@ -849,10 +873,6 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
if (ret)
goto err;
- ret = i915_gem_object_pin_pages(obj);
- if (ret)
- goto err;
-
ret = -EFAULT;
/* We can only do the GTT pwrite on untiled buffers, as otherwise
* it would end up going through the fenced access, and we'll get
@@ -875,7 +895,6 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
ret = i915_gem_phys_pwrite(obj, args, file);
}
- i915_gem_object_unpin_pages(obj);
err:
i915_gem_object_put(obj);
return ret;
--
2.28.0
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next prev parent reply other threads:[~2020-10-02 13:00 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-02 12:58 [Intel-gfx] [PATCH 00/61] drm/i915: Remove obj->mm.lock! Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 01/61] drm/i915: Move cmd parser pinning to execbuffer Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 02/61] drm/i915: Add missing -EDEADLK handling to execbuf pinning Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 03/61] drm/i915: Do not share hwsp across contexts any more, v2 Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 04/61] drm/i915: Ensure we hold the object mutex in pin correctly Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 05/61] drm/i915: Add gem object locking to madvise Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 06/61] drm/i915: Move HAS_STRUCT_PAGE to obj->flags Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 07/61] drm/i915: Rework struct phys attachment handling Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 08/61] drm/i915: Convert i915_gem_object_attach_phys() to ww locking Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 09/61] drm/i915: make lockdep slightly happier about execbuf Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 10/61] drm/i915: Disable userptr pread/pwrite support Maarten Lankhorst
2020-10-02 20:14 ` Ruhl, Michael J
2020-10-12 14:13 ` Maarten Lankhorst
2020-10-19 17:54 ` Ruhl, Michael J
2020-10-02 12:58 ` [Intel-gfx] [PATCH 11/61] drm/i915: No longer allow exporting userptr through dma-buf Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 12/61] drm/i915: Reject more ioctls for userptr Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 13/61] drm/i915: Reject UNSYNCHRONIZED " Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 14/61] drm/i915: Fix userptr so we do not have to worry about obj->mm.lock Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 15/61] drm/i915: Flatten obj->mm.lock Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 16/61] drm/i915: Pin timeline map after first timeline pin Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 17/61] drm/i915: Populate logical context during first pin Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 18/61] drm/i915: Make ring submission compatible with obj->mm.lock removal Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 19/61] drm/i915: Handle ww locking in init_status_page Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 20/61] drm/i915: Rework clflush to work correctly without obj->mm.lock Maarten Lankhorst
2020-10-02 12:58 ` [Intel-gfx] [PATCH 21/61] drm/i915: Pass ww ctx to intel_pin_to_display_plane Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 22/61] drm/i915: Add object locking to vm_fault_cpu Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 23/61] drm/i915: Move pinning to inside engine_wa_list_verify() Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 24/61] drm/i915: Take reservation lock around i915_vma_pin Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 25/61] drm/i915: Make intel_init_workaround_bb more compatible with ww locking Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 26/61] drm/i915: Make __engine_unpark() " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 27/61] drm/i915: Take obj lock around set_domain ioctl Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 28/61] drm/i915: Defer pin calls in buffer pool until first use by caller Maarten Lankhorst
2020-10-02 12:59 ` Maarten Lankhorst [this message]
2020-10-02 12:59 ` [Intel-gfx] [PATCH 30/61] drm/i915: Fix workarounds selftest, part 1 Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 31/61] drm/i915: Prepare for obj->mm.lock removal Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 32/61] drm/i915: Add igt_spinner_pin() to allow for ww locking around spinner Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 33/61] drm/i915: Add ww locking around vm_access() Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 34/61] drm/i915: Increase ww locking for perf Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 35/61] drm/i915: Lock ww in ucode objects correctly Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 36/61] drm/i915: Add ww locking to dma-buf ops Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 37/61] drm/i915: Add missing ww lock in intel_dsb_prepare Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 38/61] drm/i915: Fix ww locking in shmem_create_from_object Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 39/61] drm/i915: Use a single page table lock for each gtt Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 40/61] drm/i915/selftests: Prepare huge_pages testcases for obj->mm.lock removal Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 41/61] drm/i915/selftests: Prepare client blit " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 42/61] drm/i915/selftests: Prepare coherency tests " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 43/61] drm/i915/selftests: Prepare context " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 44/61] drm/i915/selftests: Prepare dma-buf " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 45/61] drm/i915/selftests: Prepare execbuf " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 46/61] drm/i915/selftests: Prepare mman testcases " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 47/61] drm/i915/selftests: Prepare object tests " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 48/61] drm/i915/selftests: Prepare object blit " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 49/61] drm/i915/selftests: Prepare igt_gem_utils " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 50/61] drm/i915/selftests: Prepare context selftest " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 51/61] drm/i915/selftests: Prepare hangcheck " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 52/61] drm/i915/selftests: Prepare execlists " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 53/61] drm/i915/selftests: Prepare mocs tests " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 54/61] drm/i915/selftests: Prepare ring submission " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 55/61] drm/i915/selftests: Prepare timeline tests " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 56/61] drm/i915/selftests: Prepare i915_request " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 57/61] drm/i915/selftests: Prepare memory region " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 58/61] drm/i915/selftests: Prepare cs engine " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 59/61] drm/i915/selftests: Prepare gtt " Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 60/61] drm/i915: Finally remove obj->mm.lock Maarten Lankhorst
2020-10-02 12:59 ` [Intel-gfx] [PATCH 61/61] drm/i915: Keep userpointer bindings if seqcount is unchanged Maarten Lankhorst
2020-10-02 13:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove obj->mm.lock! Patchwork
2020-10-02 18:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-02 18:38 ` [Intel-gfx] [PATCH 00/61] " Chris Wilson
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