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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [v8 10/12] drm/i915/lspcon: Create separate infoframe_enabled helper
Date: Fri, 16 Oct 2020 05:19:00 +0530	[thread overview]
Message-ID: <20201015234902.7134-11-uma.shankar@intel.com> (raw)
In-Reply-To: <20201015234902.7134-1-uma.shankar@intel.com>

Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe).
Create a separate mechanism for lspcon compared to HDMI in order to
address the same and ensure future scalability.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c    | 10 +++++++---
 drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lspcon.h |  2 ++
 3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 35edbd826443..ca99b94b4cbf 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4402,6 +4402,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	u32 temp, flags = 0;
 
 	/* XXX: DSI transcoder paranoia */
@@ -4482,9 +4483,12 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 				    pipe_config->fec_enable);
 		}
 
-		pipe_config->infoframes.enable |=
-			intel_hdmi_infoframes_enabled(encoder, pipe_config);
-
+		if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
+			pipe_config->infoframes.enable |=
+				intel_lspcon_infoframes_enabled(encoder, pipe_config);
+		else
+			pipe_config->infoframes.enable |=
+				intel_hdmi_infoframes_enabled(encoder, pipe_config);
 		break;
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d81a615ff9ac..737bfae6d0ce 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -30,6 +30,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_lspcon.h"
+#include "intel_hdmi.h"
 
 /* LSPCON OUI Vendor ID(signatures) */
 #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
@@ -677,6 +678,23 @@ bool lspcon_init(struct intel_digital_port *dig_port)
 	return true;
 }
 
+u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *pipe_config)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	u32 val, enabled = 0;
+
+	val = dig_port->infoframes_enabled(encoder, pipe_config);
+
+	if (val & VIDEO_DIP_ENABLE_AVI_HSW)
+		enabled |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
+
+	if (val & VIDEO_DIP_ENABLE_GMP_HSW)
+		enabled |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+
+	return enabled;
+}
+
 void lspcon_resume(struct intel_digital_port *dig_port)
 {
 	struct intel_lspcon *lspcon = &dig_port->lspcon;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 15965c77b43a..d69056f12a8b 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -43,5 +43,7 @@ void hsw_read_infoframe(struct intel_encoder *encoder,
 			const struct intel_crtc_state *crtc_state,
 			unsigned int type,
 			void *frame, ssize_t len);
+u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *pipe_config);
 
 #endif /* __INTEL_LSPCON_H__ */
-- 
2.26.2

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  parent reply	other threads:[~2020-10-15 23:15 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-15 23:48 [Intel-gfx] [v8 00/12] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-10-15 23:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev8) Patchwork
2020-10-15 23:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-15 23:48 ` [Intel-gfx] [v8 01/12] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 02/12] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 03/12] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 04/12] drm/i915/display: Attach content type property for LSPCON Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 05/12] drm/i915/display: Nuke bogus lspcon check Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 06/12] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 07/12] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 08/12] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 09/12] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-10-15 23:49 ` Uma Shankar [this message]
2020-10-15 23:49 ` [Intel-gfx] [v8 11/12] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks Uma Shankar
2020-10-15 23:49 ` [Intel-gfx] [v8 12/12] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-10-16  0:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable HDR on MCA LSPCON based Gen9 devices (rev8) Patchwork

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