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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Vipin Anand <vipin.anand@intel.com>
Subject: [Intel-gfx] [v8 07/12] drm/i915/display: Enable HDR for Parade based lspcon
Date: Fri, 16 Oct 2020 05:18:57 +0530	[thread overview]
Message-ID: <20201015234902.7134-8-uma.shankar@intel.com> (raw)
In-Reply-To: <20201015234902.7134-1-uma.shankar@intel.com>

Enable HDR for LSPCON based on Parade along with MCA.

v2: Added a helper for status reg as suggested by Ville.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vipin Anand <vipin.anand@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lspcon.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 2467e3e95985..be59cbde9413 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -36,6 +36,7 @@
 #define LSPCON_VENDOR_MCA_OUI 0x0060AD
 
 #define DPCD_MCA_LSPCON_HDR_STATUS	0x70003
+#define DPCD_PARADE_LSPCON_HDR_STATUS	0x00511
 
 /* AUX addresses to write MCA AVI IF */
 #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
@@ -106,21 +107,27 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
 	return true;
 }
 
+static u32 get_hdr_status_reg(struct intel_lspcon *lspcon)
+{
+	if (lspcon->vendor == LSPCON_VENDOR_MCA)
+		return DPCD_MCA_LSPCON_HDR_STATUS;
+	else
+		return DPCD_PARADE_LSPCON_HDR_STATUS;
+}
+
 void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
 {
 	struct intel_digital_port *dig_port =
 		container_of(lspcon, struct intel_digital_port, lspcon);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+	u32 lspcon_hdr_status_reg;
 	u8 hdr_caps;
 	int ret;
 
-	/* Enable HDR for MCA based LSPCON devices */
-	if (lspcon->vendor == LSPCON_VENDOR_MCA)
-		ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS,
-				       &hdr_caps, 1);
-	else
-		return;
+	lspcon_hdr_status_reg = get_hdr_status_reg(lspcon);
+	ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg,
+			       &hdr_caps, 1);
 
 	if (ret < 0) {
 		drm_dbg_kms(dev, "hdr capability detection failed\n");
-- 
2.26.2

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  parent reply	other threads:[~2020-10-15 23:15 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-15 23:48 [Intel-gfx] [v8 00/12] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-10-15 23:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev8) Patchwork
2020-10-15 23:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-15 23:48 ` [Intel-gfx] [v8 01/12] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 02/12] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 03/12] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 04/12] drm/i915/display: Attach content type property for LSPCON Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 05/12] drm/i915/display: Nuke bogus lspcon check Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 06/12] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-10-15 23:48 ` Uma Shankar [this message]
2020-10-15 23:48 ` [Intel-gfx] [v8 08/12] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-10-15 23:48 ` [Intel-gfx] [v8 09/12] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-10-15 23:49 ` [Intel-gfx] [v8 10/12] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
2020-10-15 23:49 ` [Intel-gfx] [v8 11/12] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks Uma Shankar
2020-10-15 23:49 ` [Intel-gfx] [v8 12/12] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-10-16  0:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable HDR on MCA LSPCON based Gen9 devices (rev8) Patchwork

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