From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 00/18] Introduce Alderlake-S
Date: Wed, 21 Oct 2020 06:31:55 -0700 [thread overview]
Message-ID: <20201021133213.328994-1-aditya.swarup@intel.com> (raw)
Alder Lake-S (ADL-S) is another gen12 platform and a TGL variant, with
5 combo phy outputs with the following port/phy assignment:
DDI-A (port A) <-> PHY-A
DDI-TC1 (port D) <-> PHY-B
DDI-TC2 (port E) <-> PHY-C
DDI-TC3 (port F) <-> PHY-D
DDI-TC4 (port G) <-> PHY-E
It has 1 eDP, 2 HDMI and 2 DP++ display outputs.
Aditya Swarup (5):
drm/i915/adl_s: Configure DPLL for ADL-S
drm/i915/adl_s: Configure Port clock registers for ADL-S
drm/i915/adl_s: Setup display outputs and HTI support for ADL-S
drm/i915/adl_s: Add adl-s ddc pin mapping
drm/i915/adl_s: Add vbt port and aux channel settings for adls
Anusha Srivatsa (5):
drm/i915/adl_s: Add PCH support
drm/i915/adl_s: Add Interrupt Support
drm/i915/adl_s: Add PHYs for Alderlake S
drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA
drm/i915/adl_s: Load DMC
Caz Yokoyama (2):
drm/i915/adl_s: Add ADL-S platform info and PCI ids
x86/gpu: add ADL_S stolen memory support
José Roberto de Souza (1):
drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
Matt Roper (3):
drm/i915/adl_s: Update combo PHY master/slave relationships
drm/i915/adl_s: Update PHY_MISC programming
drm/i915/adl_s: Re-use TGL GuC/HuC firmware
Tejas Upadhyay (1):
drm/i915/adl_s: Update memory bandwidth parameters
Yokoyama, Caz (1):
drm/i915/adl_s: MCHBAR memory info registers are moved
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/display/intel_bios.c | 55 +++++++++++++---
drivers/gpu/drm/i915/display/intel_bw.c | 8 +++
.../gpu/drm/i915/display/intel_combo_phy.c | 23 +++++--
drivers/gpu/drm/i915/display/intel_csr.c | 10 ++-
drivers/gpu/drm/i915/display/intel_ddi.c | 64 +++++++++++++------
drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++--
.../drm/i915/display/intel_display_power.c | 7 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++++-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 29 ++++++++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 12 ++++
drivers/gpu/drm/i915/i915_irq.c | 24 +++++--
drivers/gpu/drm/i915/i915_pci.c | 13 ++++
drivers/gpu/drm/i915/i915_reg.h | 59 +++++++++++++++--
drivers/gpu/drm/i915/intel_device_info.c | 9 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_dram.c | 18 +++++-
drivers/gpu/drm/i915/intel_pch.c | 8 ++-
drivers/gpu/drm/i915/intel_pch.h | 3 +
include/drm/i915_pciids.h | 13 ++++
24 files changed, 392 insertions(+), 69 deletions(-)
--
2.27.0
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next reply other threads:[~2020-10-21 13:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-21 13:31 Aditya Swarup [this message]
2020-10-21 13:31 ` [Intel-gfx] [PATCH 01/18] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2020-10-23 18:05 ` Matt Roper
2020-10-21 13:31 ` [Intel-gfx] [PATCH 02/18] x86/gpu: add ADL_S stolen memory support Aditya Swarup
2020-10-21 20:43 ` Matt Roper
2020-10-21 20:57 ` Lucas De Marchi
2020-10-21 13:31 ` [Intel-gfx] [PATCH 03/18] drm/i915/adl_s: Add PCH support Aditya Swarup
2020-10-21 14:17 ` Jani Nikula
2020-10-21 13:31 ` [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2020-10-21 17:28 ` Lucas De Marchi
2020-10-22 23:26 ` Aditya Swarup
2020-10-23 0:40 ` Lucas De Marchi
2020-10-21 13:32 ` [Intel-gfx] [PATCH 05/18] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
2020-10-23 18:11 ` Matt Roper
2020-10-21 13:32 ` [Intel-gfx] [PATCH 06/18] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 07/18] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2020-10-21 14:21 ` Jani Nikula
2020-10-21 13:32 ` [Intel-gfx] [PATCH 08/18] drm/i915/adl_s: Setup display outputs and HTI support " Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 09/18] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 10/18] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 11/18] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 12/18] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA Aditya Swarup
2020-11-04 10:38 ` Joonas Lahtinen
2020-11-04 14:07 ` Rodrigo Vivi
2020-10-21 13:32 ` [Intel-gfx] [PATCH 14/18] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 15/18] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 16/18] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 17/18] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 18/18] drm/i915/adl_s: Load DMC Aditya Swarup
2020-10-21 14:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S Patchwork
2020-10-21 14:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-21 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-21 16:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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