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From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Yokoyama@freedesktop.org
Subject: [Intel-gfx] [PATCH 14/18] drm/i915/adl_s: MCHBAR memory info registers are moved
Date: Wed, 21 Oct 2020 06:32:09 -0700	[thread overview]
Message-ID: <20201021133213.328994-15-aditya.swarup@intel.com> (raw)
In-Reply-To: <20201021133213.328994-1-aditya.swarup@intel.com>

From: "Yokoyama, Caz" <caz.yokoyama@intel.com>

The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
 drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 267e6602a05b..067e3710d38d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10836,6 +10836,8 @@ enum skl_power_gate {
 #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
 #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
 
+#define  ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
+
 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
 #define  SKL_DRAM_S_SHIFT			16
@@ -10863,6 +10865,9 @@ enum skl_power_gate {
 #define  CNL_DRAM_RANK_3			(0x2 << 9)
 #define  CNL_DRAM_RANK_4			(0x3 << 9)
 
+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
+
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..e7427e5f4130 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
 	u32 val;
 	int ret;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
 	if (ret == 0)
 		dram_info->num_channels++;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
 	if (ret == 0)
@@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915)
 {
 	u32 val;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 
 	switch (val & SKL_DRAM_DDR_TYPE_MASK) {
-- 
2.27.0

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  parent reply	other threads:[~2020-10-21 13:32 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-21 13:31 [Intel-gfx] [PATCH 00/18] Introduce Alderlake-S Aditya Swarup
2020-10-21 13:31 ` [Intel-gfx] [PATCH 01/18] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2020-10-23 18:05   ` Matt Roper
2020-10-21 13:31 ` [Intel-gfx] [PATCH 02/18] x86/gpu: add ADL_S stolen memory support Aditya Swarup
2020-10-21 20:43   ` Matt Roper
2020-10-21 20:57     ` Lucas De Marchi
2020-10-21 13:31 ` [Intel-gfx] [PATCH 03/18] drm/i915/adl_s: Add PCH support Aditya Swarup
2020-10-21 14:17   ` Jani Nikula
2020-10-21 13:31 ` [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2020-10-21 17:28   ` Lucas De Marchi
2020-10-22 23:26     ` Aditya Swarup
2020-10-23  0:40       ` Lucas De Marchi
2020-10-21 13:32 ` [Intel-gfx] [PATCH 05/18] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
2020-10-23 18:11   ` Matt Roper
2020-10-21 13:32 ` [Intel-gfx] [PATCH 06/18] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 07/18] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2020-10-21 14:21   ` Jani Nikula
2020-10-21 13:32 ` [Intel-gfx] [PATCH 08/18] drm/i915/adl_s: Setup display outputs and HTI support " Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 09/18] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 10/18] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 11/18] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 12/18] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA Aditya Swarup
2020-11-04 10:38   ` Joonas Lahtinen
2020-11-04 14:07     ` Rodrigo Vivi
2020-10-21 13:32 ` Aditya Swarup [this message]
2020-10-21 13:32 ` [Intel-gfx] [PATCH 15/18] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 16/18] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 17/18] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 18/18] drm/i915/adl_s: Load DMC Aditya Swarup
2020-10-21 14:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S Patchwork
2020-10-21 14:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-21 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-21 16:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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