From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 10/18] drm/i915/adl_s: Add vbt port and aux channel settings for adls
Date: Wed, 21 Oct 2020 06:32:05 -0700 [thread overview]
Message-ID: <20201021133213.328994-11-aditya.swarup@intel.com> (raw)
In-Reply-To: <20201021133213.328994-1-aditya.swarup@intel.com>
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 42 +++++++++++++++++++----
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f602013a764a..36e0a7a5c52b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1711,8 +1711,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
+ /*
+ * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
+ * PORT_F and PORT_G, we need to map that to correct VBT sections.
+ */
+ static const int adls_port_mapping[][3] = {
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+ [PORT_B] = { -1 },
+ [PORT_C] = { -1 },
+ [PORT_D] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+ [PORT_E] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_F] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_G] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+ };
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
+ ARRAY_SIZE(adls_port_mapping[0]),
+ adls_port_mapping,
+ dvo_port);
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2674,18 +2692,28 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
aux_ch = AUX_CH_A;
break;
case DP_AUX_B:
- aux_ch = AUX_CH_B;
+ aux_ch = (IS_ALDERLAKE_S(dev_priv)) ?
+ AUX_CH_D : AUX_CH_B;
break;
case DP_AUX_C:
- aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
- AUX_CH_D : AUX_CH_C;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_E;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ aux_ch = AUX_CH_D;
+ else
+ aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
- AUX_CH_E : AUX_CH_D;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_F;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ aux_ch = AUX_CH_E;
+ else
+ aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- aux_ch = AUX_CH_E;
+ aux_ch = (IS_ALDERLAKE_S(dev_priv)) ?
+ AUX_CH_G : AUX_CH_E;
break;
case DP_AUX_F:
aux_ch = AUX_CH_F;
--
2.27.0
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next prev parent reply other threads:[~2020-10-21 13:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-21 13:31 [Intel-gfx] [PATCH 00/18] Introduce Alderlake-S Aditya Swarup
2020-10-21 13:31 ` [Intel-gfx] [PATCH 01/18] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2020-10-23 18:05 ` Matt Roper
2020-10-21 13:31 ` [Intel-gfx] [PATCH 02/18] x86/gpu: add ADL_S stolen memory support Aditya Swarup
2020-10-21 20:43 ` Matt Roper
2020-10-21 20:57 ` Lucas De Marchi
2020-10-21 13:31 ` [Intel-gfx] [PATCH 03/18] drm/i915/adl_s: Add PCH support Aditya Swarup
2020-10-21 14:17 ` Jani Nikula
2020-10-21 13:31 ` [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2020-10-21 17:28 ` Lucas De Marchi
2020-10-22 23:26 ` Aditya Swarup
2020-10-23 0:40 ` Lucas De Marchi
2020-10-21 13:32 ` [Intel-gfx] [PATCH 05/18] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
2020-10-23 18:11 ` Matt Roper
2020-10-21 13:32 ` [Intel-gfx] [PATCH 06/18] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 07/18] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2020-10-21 14:21 ` Jani Nikula
2020-10-21 13:32 ` [Intel-gfx] [PATCH 08/18] drm/i915/adl_s: Setup display outputs and HTI support " Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 09/18] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2020-10-21 13:32 ` Aditya Swarup [this message]
2020-10-21 13:32 ` [Intel-gfx] [PATCH 11/18] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 12/18] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA Aditya Swarup
2020-11-04 10:38 ` Joonas Lahtinen
2020-11-04 14:07 ` Rodrigo Vivi
2020-10-21 13:32 ` [Intel-gfx] [PATCH 14/18] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 15/18] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 16/18] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 17/18] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2020-10-21 13:32 ` [Intel-gfx] [PATCH 18/18] drm/i915/adl_s: Load DMC Aditya Swarup
2020-10-21 14:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S Patchwork
2020-10-21 14:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-21 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-21 16:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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