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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 01/10] drm/i915: s/USHRT_MAX/U16_MAX/
Date: Fri, 30 Oct 2020 18:50:36 +0200	[thread overview]
Message-ID: <20201030165045.5000-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20201030165045.5000-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We use u16 for the watermarks so let's switch from
USHRT_MAX to U16_MAX for consistency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f54375b11964..75d2322cd456 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1141,7 +1141,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 	unsigned int clock, htotal, cpp, width, wm;
 
 	if (latency == 0)
-		return USHRT_MAX;
+		return U16_MAX;
 
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
@@ -1187,7 +1187,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 
 	wm = DIV_ROUND_UP(wm, 64) + 2;
 
-	return min_t(unsigned int, wm, USHRT_MAX);
+	return min_t(unsigned int, wm, U16_MAX);
 }
 
 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
@@ -1272,17 +1272,17 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
 		 * can always just disable its use.
 		 */
 		if (wm > max_wm)
-			wm = USHRT_MAX;
+			wm = U16_MAX;
 
 		dirty |= raw->fbc != wm;
 		raw->fbc = wm;
 	}
 
 	/* mark watermarks as invalid */
-	dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
+	dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, U16_MAX);
 
 	if (plane_id == PLANE_PRIMARY)
-		dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
+		dirty |= g4x_raw_fbc_wm_set(crtc_state, level, U16_MAX);
 
  out:
 	if (dirty) {
@@ -1332,21 +1332,21 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
 		enum plane_id plane_id;
 
 		for_each_plane_id_on_crtc(crtc, plane_id)
-			wm_state->wm.plane[plane_id] = USHRT_MAX;
+			wm_state->wm.plane[plane_id] = U16_MAX;
 	}
 
 	if (level <= G4X_WM_LEVEL_SR) {
 		wm_state->cxsr = false;
-		wm_state->sr.cursor = USHRT_MAX;
-		wm_state->sr.plane = USHRT_MAX;
-		wm_state->sr.fbc = USHRT_MAX;
+		wm_state->sr.cursor = U16_MAX;
+		wm_state->sr.plane = U16_MAX;
+		wm_state->sr.fbc = U16_MAX;
 	}
 
 	if (level <= G4X_WM_LEVEL_HPLL) {
 		wm_state->hpll_en = false;
-		wm_state->hpll.cursor = USHRT_MAX;
-		wm_state->hpll.plane = USHRT_MAX;
-		wm_state->hpll.fbc = USHRT_MAX;
+		wm_state->hpll.cursor = U16_MAX;
+		wm_state->hpll.plane = U16_MAX;
+		wm_state->hpll.fbc = U16_MAX;
 	}
 }
 
@@ -1665,7 +1665,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 	unsigned int clock, htotal, cpp, width, wm;
 
 	if (dev_priv->wm.pri_latency[level] == 0)
-		return USHRT_MAX;
+		return U16_MAX;
 
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
@@ -1688,7 +1688,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 				    dev_priv->wm.pri_latency[level] * 10);
 	}
 
-	return min_t(unsigned int, wm, USHRT_MAX);
+	return min_t(unsigned int, wm, U16_MAX);
 }
 
 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
@@ -1790,17 +1790,17 @@ static void vlv_invalidate_wms(struct intel_crtc *crtc,
 		enum plane_id plane_id;
 
 		for_each_plane_id_on_crtc(crtc, plane_id)
-			wm_state->wm[level].plane[plane_id] = USHRT_MAX;
+			wm_state->wm[level].plane[plane_id] = U16_MAX;
 
-		wm_state->sr[level].cursor = USHRT_MAX;
-		wm_state->sr[level].plane = USHRT_MAX;
+		wm_state->sr[level].cursor = U16_MAX;
+		wm_state->sr[level].plane = U16_MAX;
 	}
 }
 
 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
 {
 	if (wm > fifo_size)
-		return USHRT_MAX;
+		return U16_MAX;
 	else
 		return fifo_size - wm;
 }
@@ -1854,7 +1854,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
 	}
 
 	/* mark all higher levels as invalid */
-	dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
+	dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, U16_MAX);
 
 out:
 	if (dirty)
@@ -6492,8 +6492,8 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
 	out:
 		for_each_plane_id_on_crtc(crtc, plane_id)
 			g4x_raw_plane_wm_set(crtc_state, level,
-					     plane_id, USHRT_MAX);
-		g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
+					     plane_id, U16_MAX);
+		g4x_raw_fbc_wm_set(crtc_state, level, U16_MAX);
 
 		crtc_state->wm.g4x.optimal = *active;
 		crtc_state->wm.g4x.intermediate = *active;
@@ -6652,7 +6652,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
 
 		for_each_plane_id_on_crtc(crtc, plane_id)
 			vlv_raw_plane_wm_set(crtc_state, level,
-					     plane_id, USHRT_MAX);
+					     plane_id, U16_MAX);
 		vlv_invalidate_wms(crtc, active, level);
 
 		crtc_state->wm.vlv.optimal = *active;
-- 
2.26.2

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  reply	other threads:[~2020-10-30 16:50 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
2020-10-30 16:50 ` Ville Syrjala [this message]
2020-10-30 16:50 ` [Intel-gfx] [PATCH 02/10] drm/i915: Shrink ilk-bdw wm storage by using u16 Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 03/10] drm/i915: Rename ilk watermark structs/enums Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 04/10] drm/i915: s/dev_priv->wm.hw/&dev_priv->wm.ilk/ Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 05/10] drm/i915: s/ilk_pipe_wm/ilk_wm_state/ Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 06/10] drm/i915: Stash away the original SSKPD latency values Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 07/10] drm/i915: Remove gen6_check_mch_setup() Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 08/10] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64() Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines Ville Syrjala
2020-10-30 20:52   ` kernel test robot
2020-11-15 10:54   ` kernel test robot
2020-10-30 16:50 ` [Intel-gfx] [PATCH 10/10] drm/i915: Polish ilk+ wm regidster bits Ville Syrjala
2020-10-30 17:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ilk+ wm cleanups Patchwork
2020-10-30 18:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-30 18:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2020-10-30 22:21 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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