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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 07/10] drm/i915: Remove gen6_check_mch_setup()
Date: Fri, 30 Oct 2020 18:50:42 +0200	[thread overview]
Message-ID: <20201030165045.5000-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20201030165045.5000-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

snb_wm_latency_quirk() already boosts up the latency values
so the extra warning about the SSKPD value being insufficient
is now redundant. Drop it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  2 --
 drivers/gpu/drm/i915/intel_pm.c | 15 ---------------
 2 files changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb0656875697..89f5204508fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3791,8 +3791,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 /* snb MCH registers for priority tuning */
 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
-#define   MCH_SSKPD_WM0_MASK		0x3f
-#define   MCH_SSKPD_WM0_VAL		0xc
 
 /* Clocking configuration register */
 #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5db20bf36302..d4cbc16441d7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6982,17 +6982,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
-{
-	u32 tmp;
-
-	tmp = I915_READ(MCH_SSKPD);
-	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
-		drm_dbg_kms(&dev_priv->drm,
-			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
-			    tmp);
-}
-
 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
@@ -7050,8 +7039,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 	g4x_disable_trickle_feed(dev_priv);
 
 	cpt_init_clock_gating(dev_priv);
-
-	gen6_check_mch_setup(dev_priv);
 }
 
 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7420,8 +7407,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
 
 	if (!HAS_PCH_NOP(dev_priv))
 		cpt_init_clock_gating(dev_priv);
-
-	gen6_check_mch_setup(dev_priv);
 }
 
 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.26.2

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  parent reply	other threads:[~2020-10-30 16:51 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 01/10] drm/i915: s/USHRT_MAX/U16_MAX/ Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 02/10] drm/i915: Shrink ilk-bdw wm storage by using u16 Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 03/10] drm/i915: Rename ilk watermark structs/enums Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 04/10] drm/i915: s/dev_priv->wm.hw/&dev_priv->wm.ilk/ Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 05/10] drm/i915: s/ilk_pipe_wm/ilk_wm_state/ Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 06/10] drm/i915: Stash away the original SSKPD latency values Ville Syrjala
2020-10-30 16:50 ` Ville Syrjala [this message]
2020-10-30 16:50 ` [Intel-gfx] [PATCH 08/10] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64() Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines Ville Syrjala
2020-10-30 20:52   ` kernel test robot
2020-11-15 10:54   ` kernel test robot
2020-10-30 16:50 ` [Intel-gfx] [PATCH 10/10] drm/i915: Polish ilk+ wm regidster bits Ville Syrjala
2020-10-30 17:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ilk+ wm cleanups Patchwork
2020-10-30 18:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-30 18:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2020-10-30 22:21 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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