From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 13/18] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
Date: Thu, 28 Jan 2021 11:24:08 -0800 [thread overview]
Message-ID: <20210128192413.1715802-14-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210128192413.1715802-1-matthew.d.roper@intel.com>
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c12d5375607..a531103fb0b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1212,10 +1212,18 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
u8 dsc_bpc[3] = {0};
+ u8 dsc_max_bpc;
+
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (INTEL_GEN(i915) >= 12)
+ dsc_max_bpc = min_t(u8, 12, max_req_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1303,7 +1311,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- u8 dsc_max_bpc;
int pipe_bpp;
int ret;
@@ -1313,14 +1320,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (INTEL_GEN(dev_priv) >= 12)
- dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
- else
- dsc_max_bpc = min_t(u8, 10,
- conn_state->max_requested_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
/* Min Input BPC for ICL+ is 8 */
if (pipe_bpp < 8 * 3) {
--
2.25.4
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next prev parent reply other threads:[~2021-01-28 19:24 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-28 19:23 [Intel-gfx] [PATCH 00/18] Preliminary Display13 support Matt Roper
2021-01-28 19:23 ` [Intel-gfx] [PATCH 01/18] drm/i915/display13: add Display13 characteristics Matt Roper
2021-02-11 0:03 ` Lucas De Marchi
2021-01-28 19:23 ` [Intel-gfx] [PATCH 02/18] drm/i915/display13: Handle proper AUX interrupt bits Matt Roper
2021-02-11 0:10 ` Lucas De Marchi
2021-01-28 19:23 ` [Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting Matt Roper
2021-02-11 0:31 ` Lucas De Marchi
2021-02-11 12:25 ` Ville Syrjälä
2021-01-28 19:23 ` [Intel-gfx] [PATCH 04/18] drm/i915/display13: Define plane capabilities Matt Roper
2021-02-11 1:05 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 05/18] drm/i915/display13: Support 128k plane stride Matt Roper
2021-02-11 1:17 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 06/18] drm/i915/display13: Only enable legacy gamma for now Matt Roper
2021-02-11 1:19 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells Matt Roper
2021-02-11 1:33 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 08/18] drm/i915/display13: Handle LPSP for Display 13 Matt Roper
2021-02-11 1:36 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 09/18] drm/i915/display13: Handle new location of outputs D and E Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 10/18] drm/i915/display13: Increase maximum watermark lines to 255 Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 11/18] drm/i915/display13: Required bandwidth increases when VT-d is active Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 12/18] drm/i915/display13: Add Wa_14011503030:d13 Matt Roper
2021-01-28 19:24 ` Matt Roper [this message]
2021-01-28 19:24 ` [Intel-gfx] [PATCH 14/18] drm/i915/display13: Support DP1.4 compression BPPs Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 15/18] drm/i915/display13: Get slice height before computing rc params Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 16/18] drm/i915/display13: Calculate VDSC RC parameters Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation Matt Roper
2021-01-29 11:12 ` Jani Nikula
2021-01-29 11:15 ` Chris Wilson
2021-01-29 12:01 ` Jani Nikula
2021-02-10 22:24 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 18/18] drm/i915/display13: Enabling dithering after the CC1 pipe Matt Roper
2021-02-11 12:29 ` Ville Syrjälä
2021-02-19 3:22 ` Mario Kleiner
2021-02-19 5:44 ` Mario Kleiner
2021-03-01 4:57 ` Varide, Nischal
2021-03-01 5:43 ` Ilia Mirkin
2021-01-28 19:25 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Preliminary Display13 support Patchwork
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