From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 06/18] drm/i915/display13: Only enable legacy gamma for now
Date: Thu, 28 Jan 2021 11:24:01 -0800 [thread overview]
Message-ID: <20210128192413.1715802-7-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210128192413.1715802-1-matthew.d.roper@intel.com>
The multi-segment gamma used on past platforms is gone and replaced by a
logarithmic LUT. Until logarithmic LUT is enabled, let's just turn off
uapi color management (aside from legacy gamma) since it doesn't really
make sense to expose the full degamma and CTM when we only have limited
legacy gamma support to go with them. Note that the hardware
programming of the degamma and CTM is unchanged except that the degamma
table now has 128 entries instead of just 33.
The output CSC used implicitly for RGB->YUV conversions is also
unchanged and will continue to function as expected.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e5e10484bf8d..fb28f3b24dd8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -945,7 +945,18 @@ static const struct intel_device_info adl_s_info = {
BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
.ddb_size = 4096, \
.mbus_size = 2048, \
- .num_supported_dbuf_slices = 4,
+ .num_supported_dbuf_slices = 4, \
+ /* \
+ * FIXME: Just enable legacy gamma (and no degamma/csc) until \
+ * logarithmic LUT is implemented. \
+ * \
+ * LEGACY_LUT_LENGTH = 256 entries \
+ * \
+ * Note that once logarithmic LUT is enabled and we re-enable \
+ * real color management, degamma_lut_size here should be set \
+ * to 128. \
+ */ \
+ .color = { .degamma_lut_size = 0, .gamma_lut_size = 256 }
#undef GEN
#undef PLATFORM
--
2.25.4
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next prev parent reply other threads:[~2021-01-28 19:24 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-28 19:23 [Intel-gfx] [PATCH 00/18] Preliminary Display13 support Matt Roper
2021-01-28 19:23 ` [Intel-gfx] [PATCH 01/18] drm/i915/display13: add Display13 characteristics Matt Roper
2021-02-11 0:03 ` Lucas De Marchi
2021-01-28 19:23 ` [Intel-gfx] [PATCH 02/18] drm/i915/display13: Handle proper AUX interrupt bits Matt Roper
2021-02-11 0:10 ` Lucas De Marchi
2021-01-28 19:23 ` [Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting Matt Roper
2021-02-11 0:31 ` Lucas De Marchi
2021-02-11 12:25 ` Ville Syrjälä
2021-01-28 19:23 ` [Intel-gfx] [PATCH 04/18] drm/i915/display13: Define plane capabilities Matt Roper
2021-02-11 1:05 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 05/18] drm/i915/display13: Support 128k plane stride Matt Roper
2021-02-11 1:17 ` Lucas De Marchi
2021-01-28 19:24 ` Matt Roper [this message]
2021-02-11 1:19 ` [Intel-gfx] [PATCH 06/18] drm/i915/display13: Only enable legacy gamma for now Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells Matt Roper
2021-02-11 1:33 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 08/18] drm/i915/display13: Handle LPSP for Display 13 Matt Roper
2021-02-11 1:36 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 09/18] drm/i915/display13: Handle new location of outputs D and E Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 10/18] drm/i915/display13: Increase maximum watermark lines to 255 Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 11/18] drm/i915/display13: Required bandwidth increases when VT-d is active Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 12/18] drm/i915/display13: Add Wa_14011503030:d13 Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 13/18] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 14/18] drm/i915/display13: Support DP1.4 compression BPPs Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 15/18] drm/i915/display13: Get slice height before computing rc params Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 16/18] drm/i915/display13: Calculate VDSC RC parameters Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation Matt Roper
2021-01-29 11:12 ` Jani Nikula
2021-01-29 11:15 ` Chris Wilson
2021-01-29 12:01 ` Jani Nikula
2021-02-10 22:24 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 18/18] drm/i915/display13: Enabling dithering after the CC1 pipe Matt Roper
2021-02-11 12:29 ` Ville Syrjälä
2021-02-19 3:22 ` Mario Kleiner
2021-02-19 5:44 ` Mario Kleiner
2021-03-01 4:57 ` Varide, Nischal
2021-03-01 5:43 ` Ilia Mirkin
2021-01-28 19:25 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Preliminary Display13 support Patchwork
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