Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v2 08/23] drm/i915/xelpd: Handle proper AUX interrupt bits
Date: Thu, 11 Mar 2021 07:34:00 -0800	[thread overview]
Message-ID: <20210311153415.3024607-9-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210311153415.3024607-1-matthew.d.roper@intel.com>

XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.

While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.

v2:
 - Maintain bit order rather than logical order.  (Lucas)
 - Convert surrounding code to REG_BIT() notation.  (Lucas)

Bspec: 50064
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 12 +++++++++++-
 drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++---------
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 23be88d59055..c9e03973502c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2269,7 +2269,17 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 {
 	u32 mask;
 
-	if (DISPLAY_VER(dev_priv) >= 12)
+	if (DISPLAY_VER(dev_priv) >= 13)
+		return TGL_DE_PORT_AUX_DDIA |
+			TGL_DE_PORT_AUX_DDIB |
+			TGL_DE_PORT_AUX_DDIC |
+			XELPD_DE_PORT_AUX_DDID |
+			XELPD_DE_PORT_AUX_DDIE |
+			TGL_DE_PORT_AUX_USBC1 |
+			TGL_DE_PORT_AUX_USBC2 |
+			TGL_DE_PORT_AUX_USBC3 |
+			TGL_DE_PORT_AUX_USBC4;
+	else if (DISPLAY_VER(dev_priv) >= 12)
 		return TGL_DE_PORT_AUX_DDIA |
 			TGL_DE_PORT_AUX_DDIB |
 			TGL_DE_PORT_AUX_DDIC |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e5dd0203991b..475d14db2844 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7855,15 +7855,17 @@ enum {
 #define  BDW_DE_PORT_HOTPLUG_MASK	GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
 #define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
-#define  TGL_DE_PORT_AUX_USBC6		(1 << 13)
-#define  TGL_DE_PORT_AUX_USBC5		(1 << 12)
-#define  TGL_DE_PORT_AUX_USBC4		(1 << 11)
-#define  TGL_DE_PORT_AUX_USBC3		(1 << 10)
-#define  TGL_DE_PORT_AUX_USBC2		(1 << 9)
-#define  TGL_DE_PORT_AUX_USBC1		(1 << 8)
-#define  TGL_DE_PORT_AUX_DDIC		(1 << 2)
-#define  TGL_DE_PORT_AUX_DDIB		(1 << 1)
-#define  TGL_DE_PORT_AUX_DDIA		(1 << 0)
+#define  TGL_DE_PORT_AUX_USBC6		REG_BIT(13)
+#define  XELPD_DE_PORT_AUX_DDIE		REG_BIT(13)
+#define  TGL_DE_PORT_AUX_USBC5		REG_BIT(12)
+#define  XELPD_DE_PORT_AUX_DDID		REG_BIT(12)
+#define  TGL_DE_PORT_AUX_USBC4		REG_BIT(11)
+#define  TGL_DE_PORT_AUX_USBC3		REG_BIT(10)
+#define  TGL_DE_PORT_AUX_USBC2		REG_BIT(9)
+#define  TGL_DE_PORT_AUX_USBC1		REG_BIT(8)
+#define  TGL_DE_PORT_AUX_DDIC		REG_BIT(2)
+#define  TGL_DE_PORT_AUX_DDIB		REG_BIT(1)
+#define  TGL_DE_PORT_AUX_DDIA		REG_BIT(0)
 
 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-03-11 15:34 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-11 15:33 [Intel-gfx] [PATCH v2 00/23] Separate display version numbering and add XE_LPD (version 13) Matt Roper
2021-03-11 15:33 ` [Intel-gfx] [PATCH v2 01/23] drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE Matt Roper
2021-03-11 15:33 ` [Intel-gfx] [PATCH v2 02/23] drm/i915: Add DISPLAY_VER() Matt Roper
2021-03-17 17:45   ` Jani Nikula
2021-03-19 20:49     ` Matt Roper
2021-03-11 15:33 ` [Intel-gfx] [PATCH v2 03/23] drm/i915/display: Eliminate most usage of INTEL_GEN() Matt Roper
2021-03-15 20:14   ` Lucas De Marchi
2021-03-17 17:57     ` Jani Nikula
2021-03-17 18:37       ` Lucas De Marchi
2021-03-11 15:33 ` [Intel-gfx] [PATCH v2 04/23] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c Matt Roper
2021-03-15 20:17   ` Lucas De Marchi
2021-03-11 15:33 ` [Intel-gfx] [PATCH v2 05/23] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c Matt Roper
2021-03-15 20:19   ` Lucas De Marchi
2021-03-11 15:33 ` [Intel-gfx] [PATCH v2 06/23] drm/i915/display: Simplify GLK display version tests Matt Roper
2021-03-15 20:21   ` Lucas De Marchi
2021-03-11 15:33 ` [Intel-gfx] [PATCH v2 07/23] drm/i915/xelpd: add XE_LPD display characteristics Matt Roper
2021-03-17 17:15   ` Jani Nikula
2021-03-11 15:34 ` Matt Roper [this message]
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 09/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 10/23] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 11/23] drm/i915/xelpd: Support 128k plane stride Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 12/23] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 13/23] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 14/23] drm/i915/xelpd: Handle LPSP for XE_LPD Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 15/23] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 16/23] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 17/23] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 18/23] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 19/23] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 20/23] drm/i915: Get slice height before computing rc params Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 21/23] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 22/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-03-11 15:34 ` [Intel-gfx] [PATCH v2 23/23] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-03-11 16:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Separate display version numbering and add XE_LPD (version 13) Patchwork
2021-03-11 16:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-11 16:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-11 18:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210311153415.3024607-9-matthew.d.roper@intel.com \
    --to=matthew.d.roper@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox