From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 2/4] drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled
Date: Fri, 14 May 2021 16:22:45 -0700 [thread overview]
Message-ID: <20210514232247.144542-2-jose.souza@intel.com> (raw)
In-Reply-To: <20210514232247.144542-1-jose.souza@intel.com>
When PSR is enabled it handles DP_SDP_VSC, changing revision and all
the other fields as necessary.
It can also enabled and disable this SDP as needed without a full
modeset.
So here masking DP_SDP_VSC bit when previous and future state PSR
enabled, it will still be checked when comparing the asked state
to what was programmed to hardware.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out"
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 51f499271cc8..ebac1bd5cfe5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8260,6 +8260,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
+ if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
+ "(expected 0x%08x, found 0x%08x)", \
+ current_config->name & (mask), \
+ pipe_config->name & (mask)); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_I(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
@@ -8606,7 +8616,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(min_voltage_level);
}
- PIPE_CONF_CHECK_X(infoframes.enable);
+ if (fastset && (current_config->has_psr || pipe_config->has_psr))
+ PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
+ ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
+ else
+ PIPE_CONF_CHECK_X(infoframes.enable);
+
PIPE_CONF_CHECK_X(infoframes.gcp);
PIPE_CONF_CHECK_INFOFRAME(avi);
PIPE_CONF_CHECK_INFOFRAME(spd);
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-05-14 23:19 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-14 23:22 [Intel-gfx] [PATCH v2 1/4] drm/i915/display: Fix fastsets involving PSR José Roberto de Souza
2021-05-14 23:22 ` José Roberto de Souza [this message]
2021-06-07 11:44 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled Gwan-gyeong Mun
2021-05-14 23:22 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/display: Nuke has_infoframe José Roberto de Souza
2021-05-21 15:27 ` Mun, Gwan-gyeong
2021-05-21 19:58 ` Souza, Jose
2021-06-07 12:49 ` Gwan-gyeong Mun
2021-06-07 23:16 ` Souza, Jose
2021-05-14 23:22 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/display: Drop FIXME about turn off infoframes José Roberto de Souza
2021-06-01 22:41 ` Sripada, Radhakrishna
2021-06-08 7:26 ` Ville Syrjälä
2021-06-09 19:25 ` Souza, Jose
2021-06-10 12:18 ` Ville Syrjälä
2021-06-10 17:44 ` Souza, Jose
2021-06-11 18:15 ` Ville Syrjälä
2021-05-14 23:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR Patchwork
2021-05-14 23:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-15 0:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-15 0:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2) Patchwork
2021-05-15 0:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-15 1:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-15 13:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-06-07 17:51 ` Souza, Jose
2021-06-07 11:19 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/display: Fix fastsets involving PSR Gwan-gyeong Mun
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210514232247.144542-2-jose.souza@intel.com \
--to=jose.souza@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox