Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/display: Fix fastsets involving PSR

[Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>]

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

On 5/15/21 2:22 AM, José Roberto de Souza wrote:
> Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware
> configuration read out") is not allowing fastsets to happen when PSR
> states changes but PSR is a feature that can be enabled and disabled
> during fastsets.
> 
> So here moving the PSR pipe conf checks to a block that is only
> executed when checking if HW state matches with requested state, not
> during the phase where it checks if fastset is possible or not.
> 
> There still a state mismatch not allowing fastsets between states
> turning off or on PSR because of crtc_state->infoframes.enable
> BIT(DP_SDP_VSC) but at least for now it will allow a fastset between
> PSR1 <-> PSR2, that is a case heavilly used by CI due to pipe CRC not
> work with PSR2, but the remaning issue will be fixed in a future patch.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out")
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0c2b194006f8..51f499271cc8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8548,6 +8548,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   		bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
>   		if (bp_gamma)
>   			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
> +
> +		PIPE_CONF_CHECK_BOOL(has_psr);
> +		PIPE_CONF_CHECK_BOOL(has_psr2);
> +		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> +		PIPE_CONF_CHECK_I(dc3co_exitline);
>   	}
>   
>   	PIPE_CONF_CHECK_BOOL(double_wide);
> @@ -8631,11 +8636,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   	PIPE_CONF_CHECK_I(vrr.flipline);
>   	PIPE_CONF_CHECK_I(vrr.pipeline_full);
>   
> -	PIPE_CONF_CHECK_BOOL(has_psr);
> -	PIPE_CONF_CHECK_BOOL(has_psr2);
> -	PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> -	PIPE_CONF_CHECK_I(dc3co_exitline);
> -
>   #undef PIPE_CONF_CHECK_X
>   #undef PIPE_CONF_CHECK_I
>   #undef PIPE_CONF_CHECK_BOOL
> 
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