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From: Matthew Brost <matthew.brost@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: jason.ekstrand@intel.com, daniel.vetter@intel.com
Subject: Re: [Intel-gfx] [RFC PATCH 19/97] drm/i915/guc: Always copy CT message to new allocation
Date: Tue, 25 May 2021 11:25:06 -0700	[thread overview]
Message-ID: <20210525182505.GA25419@sdutt-i7> (raw)
In-Reply-To: <20210506191451.77768-20-matthew.brost@intel.com>

On Thu, May 06, 2021 at 12:13:33PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> Since most of future CT traffic will be based on G2H requests,
> instead of copying incoming CT message to static buffer and then
> create new allocation for such request, always copy incoming CT
> message to new allocation. Also by doing it while reading CT
> header, we can safely fallback if that atomic allocation fails.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 180 ++++++++++++++--------
>  1 file changed, 120 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index d630ec32decf..a174978c6a27 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -72,8 +72,9 @@ struct ct_request {
>  	u32 *response_buf;
>  };
>  
> -struct ct_incoming_request {
> +struct ct_incoming_msg {
>  	struct list_head link;
> +	u32 size;
>  	u32 msg[];
>  };
>  
> @@ -575,7 +576,26 @@ static inline bool ct_header_is_response(u32 header)
>  	return !!(header & GUC_CT_MSG_IS_RESPONSE);
>  }
>  
> -static int ct_read(struct intel_guc_ct *ct, u32 *data)
> +static struct ct_incoming_msg *ct_alloc_msg(u32 num_dwords)
> +{
> +	struct ct_incoming_msg *msg;
> +
> +	msg = kmalloc(sizeof(*msg) + sizeof(u32) * num_dwords, GFP_ATOMIC);
> +	if (msg)
> +		msg->size = num_dwords;
> +	return msg;
> +}
> +
> +static void ct_free_msg(struct ct_incoming_msg *msg)
> +{
> +	kfree(msg);
> +}
> +
> +/*
> + * Return: number available remaining dwords to read (0 if empty)
> + *         or a negative error code on failure
> + */
> +static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>  {
>  	struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
>  	struct guc_ct_buffer_desc *desc = ctb->desc;
> @@ -586,6 +606,7 @@ static int ct_read(struct intel_guc_ct *ct, u32 *data)
>  	s32 available;
>  	unsigned int len;
>  	unsigned int i;
> +	u32 header;
>  
>  	if (unlikely(desc->is_in_error))
>  		return -EPIPE;
> @@ -601,8 +622,10 @@ static int ct_read(struct intel_guc_ct *ct, u32 *data)
>  
>  	/* tail == head condition indicates empty */
>  	available = tail - head;
> -	if (unlikely(available == 0))
> -		return -ENODATA;
> +	if (unlikely(available == 0)) {
> +		*msg = NULL;
> +		return 0;
> +	}
>  
>  	/* beware of buffer wrap case */
>  	if (unlikely(available < 0))
> @@ -610,14 +633,14 @@ static int ct_read(struct intel_guc_ct *ct, u32 *data)
>  	CT_DEBUG(ct, "available %d (%u:%u)\n", available, head, tail);
>  	GEM_BUG_ON(available < 0);
>  
> -	data[0] = cmds[head];
> +	header = cmds[head];
>  	head = (head + 1) % size;
>  
>  	/* message len with header */
> -	len = ct_header_get_len(data[0]) + 1;
> +	len = ct_header_get_len(header) + 1;
>  	if (unlikely(len > (u32)available)) {
>  		CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
> -			 4, data,
> +			 4, &header,
>  			 4 * (head + available - 1 > size ?
>  			      size - head : available - 1), &cmds[head],
>  			 4 * (head + available - 1 > size ?
> @@ -625,11 +648,24 @@ static int ct_read(struct intel_guc_ct *ct, u32 *data)
>  		goto corrupted;
>  	}
>  
> +	*msg = ct_alloc_msg(len);
> +	if (!*msg) {
> +		CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
> +			 4, &header,
> +			 4 * (head + available - 1 > size ?
> +			      size - head : available - 1), &cmds[head],
> +			 4 * (head + available - 1 > size ?
> +			      available - 1 - size + head : 0), &cmds[0]);
> +		return available;
> +	}
> +
> +	(*msg)->msg[0] = header;
> +
>  	for (i = 1; i < len; i++) {
> -		data[i] = cmds[head];
> +		(*msg)->msg[i] = cmds[head];
>  		head = (head + 1) % size;
>  	}
> -	CT_DEBUG(ct, "received %*ph\n", 4 * len, data);
> +	CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>  
>  	desc->head = head * 4;
>  	return available - len;
> @@ -659,33 +695,33 @@ static int ct_read(struct intel_guc_ct *ct, u32 *data)
>   *                   ^-----------------------len-----------------------^
>   */
>  
> -static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
> +static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *response)
>  {
> -	u32 header = msg[0];
> +	u32 header = response->msg[0];
>  	u32 len = ct_header_get_len(header);
> -	u32 msgsize = (len + 1) * sizeof(u32); /* msg size in bytes w/header */
>  	u32 fence;
>  	u32 status;
>  	u32 datalen;
>  	struct ct_request *req;
>  	unsigned long flags;
>  	bool found = false;
> +	int err = 0;
>  
>  	GEM_BUG_ON(!ct_header_is_response(header));
>  
>  	/* Response payload shall at least include fence and status */
>  	if (unlikely(len < 2)) {
> -		CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
> +		CT_ERROR(ct, "Corrupted response (len %u)\n", len);
>  		return -EPROTO;
>  	}
>  
> -	fence = msg[1];
> -	status = msg[2];
> +	fence = response->msg[1];
> +	status = response->msg[2];
>  	datalen = len - 2;
>  
>  	/* Format of the status follows RESPONSE message */
>  	if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
> -		CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
> +		CT_ERROR(ct, "Corrupted response (status %#x)\n", status);
>  		return -EPROTO;
>  	}
>  
> @@ -699,12 +735,13 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>  			continue;
>  		}
>  		if (unlikely(datalen > req->response_len)) {
> -			CT_ERROR(ct, "Response for %u is too long %*ph\n",
> -				 req->fence, msgsize, msg);
> -			datalen = 0;
> +			CT_ERROR(ct, "Response %u too long (datalen %u > %u)\n",
> +				 req->fence, datalen, req->response_len);
> +			datalen = min(datalen, req->response_len);
> +			err = -EMSGSIZE;
>  		}
>  		if (datalen)
> -			memcpy(req->response_buf, msg + 3, 4 * datalen);
> +			memcpy(req->response_buf, response->msg + 3, 4 * datalen);
>  		req->response_len = datalen;
>  		WRITE_ONCE(req->status, status);
>  		found = true;
> @@ -712,45 +749,61 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>  	}
>  	spin_unlock_irqrestore(&ct->requests.lock, flags);
>  
> -	if (!found)
> -		CT_ERROR(ct, "Unsolicited response %*ph\n", msgsize, msg);
> +	if (!found) {
> +		CT_ERROR(ct, "Unsolicited response (fence %u)\n", fence);
> +		return -ENOKEY;
> +	}
> +
> +	if (unlikely(err))
> +		return err;
> +
> +	ct_free_msg(response);
>  	return 0;
>  }
>  
> -static void ct_process_request(struct intel_guc_ct *ct,
> -			       u32 action, u32 len, const u32 *payload)
> +static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *request)
>  {
>  	struct intel_guc *guc = ct_to_guc(ct);
> +	u32 header, action, len;
> +	const u32 *payload;
>  	int ret;
>  
> +	header = request->msg[0];
> +	payload = &request->msg[1];
> +	action = ct_header_get_action(header);
> +	len = ct_header_get_len(header);
> +
>  	CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload);
>  
>  	switch (action) {
>  	case INTEL_GUC_ACTION_DEFAULT:
>  		ret = intel_guc_to_host_process_recv_msg(guc, payload, len);
> -		if (unlikely(ret))
> -			goto fail_unexpected;
>  		break;
> -
>  	default:
> -fail_unexpected:
> -		CT_ERROR(ct, "Unexpected request %x %*ph\n",
> -			 action, 4 * len, payload);
> +		ret = -EOPNOTSUPP;
>  		break;
>  	}
> +
> +	if (unlikely(ret)) {
> +		CT_ERROR(ct, "Failed to process request %04x (%pe)\n",
> +			 action, ERR_PTR(ret));
> +		return ret;
> +	}
> +
> +	ct_free_msg(request);
> +	return 0;
>  }
>  
>  static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
>  {
>  	unsigned long flags;
> -	struct ct_incoming_request *request;
> -	u32 header;
> -	u32 *payload;
> +	struct ct_incoming_msg *request;
>  	bool done;
> +	int err;
>  
>  	spin_lock_irqsave(&ct->requests.lock, flags);
>  	request = list_first_entry_or_null(&ct->requests.incoming,
> -					   struct ct_incoming_request, link);
> +					   struct ct_incoming_msg, link);
>  	if (request)
>  		list_del(&request->link);
>  	done = !!list_empty(&ct->requests.incoming);
> @@ -759,14 +812,13 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
>  	if (!request)
>  		return true;
>  
> -	header = request->msg[0];
> -	payload = &request->msg[1];
> -	ct_process_request(ct,
> -			   ct_header_get_action(header),
> -			   ct_header_get_len(header),
> -			   payload);
> +	err = ct_process_request(ct, request);
> +	if (unlikely(err)) {
> +		CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
> +			 ERR_PTR(err), 4 * request->size, request->msg);
> +		ct_free_msg(request);
> +	}
>  
> -	kfree(request);
>  	return done;
>  }
>  
> @@ -799,22 +851,11 @@ static void ct_incoming_request_worker_func(struct work_struct *w)
>   *                   ^-----------------------len-----------------------^
>   */
>  
> -static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
> +static int ct_handle_request(struct intel_guc_ct *ct, struct ct_incoming_msg *request)
>  {
> -	u32 header = msg[0];
> -	u32 len = ct_header_get_len(header);
> -	u32 msgsize = (len + 1) * sizeof(u32); /* msg size in bytes w/header */
> -	struct ct_incoming_request *request;
>  	unsigned long flags;
>  
> -	GEM_BUG_ON(ct_header_is_response(header));
> -
> -	request = kmalloc(sizeof(*request) + msgsize, GFP_ATOMIC);
> -	if (unlikely(!request)) {
> -		CT_ERROR(ct, "Dropping request %*ph\n", msgsize, msg);
> -		return 0; /* XXX: -ENOMEM ? */
> -	}
> -	memcpy(request->msg, msg, msgsize);
> +	GEM_BUG_ON(ct_header_is_response(request->msg[0]));
>  
>  	spin_lock_irqsave(&ct->requests.lock, flags);
>  	list_add_tail(&request->link, &ct->requests.incoming);
> @@ -824,22 +865,41 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
>  	return 0;
>  }
>  
> +static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
> +{
> +	u32 header = msg->msg[0];
> +	int err;
> +
> +	if (ct_header_is_response(header))
> +		err = ct_handle_response(ct, msg);
> +	else
> +		err = ct_handle_request(ct, msg);
> +
> +	if (unlikely(err)) {
> +		CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
> +			 ERR_PTR(err), 4 * msg->size, msg->msg);
> +		ct_free_msg(msg);
> +	}
> +}
> +
> +/*
> + * Return: number available remaining dwords to read (0 if empty)
> + *         or a negative error code on failure
> + */
>  static int ct_receive(struct intel_guc_ct *ct)
>  {
> -	u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
> +	struct ct_incoming_msg *msg = NULL;
>  	unsigned long flags;
>  	int ret;
>  
>  	spin_lock_irqsave(&ct->ctbs.recv.lock, flags);
> -	ret = ct_read(ct, msg);
> +	ret = ct_read(ct, &msg);
>  	spin_unlock_irqrestore(&ct->ctbs.recv.lock, flags);
>  	if (ret < 0)
>  		return ret;
>  
> -	if (ct_header_is_response(msg[0]))
> -		ct_handle_response(ct, msg);
> -	else
> -		ct_handle_request(ct, msg);
> +	if (msg)
> +		ct_handle_msg(ct, msg);
>  
>  	return ret;
>  }
> -- 
> 2.28.0
> 
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  reply	other threads:[~2021-05-25 18:32 UTC|newest]

Thread overview: 251+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-06 19:13 [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915 Matthew Brost
2021-05-06 19:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 01/97] drm/i915/gt: Move engine setup out of set_default_submission Matthew Brost
2021-05-19  0:25   ` Matthew Brost
2021-05-25  8:44   ` Tvrtko Ursulin
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 02/97] drm/i915/gt: Move submission_method into intel_gt Matthew Brost
2021-05-19  3:10   ` Matthew Brost
2021-05-25  8:44   ` Tvrtko Ursulin
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 03/97] drm/i915/gt: Move CS interrupt handler to the backend Matthew Brost
2021-05-19  3:31   ` Matthew Brost
2021-05-25  8:45   ` Tvrtko Ursulin
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 04/97] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost
2021-05-20 16:47   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 05/97] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost
2021-05-24 10:30   ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost
2021-05-25  0:31   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 07/97] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost
2021-05-24 10:48   ` Michal Wajdeczko
2021-05-25  0:36   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 08/97] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost
2021-05-24 23:52   ` Michał Winiarski
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 09/97] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost
2021-05-25  2:38   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 10/97] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost
2021-05-25  0:42   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 11/97] drm/i915/guc: Only rely on own CTB size Matthew Brost
2021-05-25  2:47   ` Matthew Brost
2021-05-25 12:48     ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 12/97] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost
2021-05-25  2:53   ` Matthew Brost
2021-05-25 13:07     ` Michal Wajdeczko
2021-05-25 16:56       ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 13/97] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-05-25  3:15   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 14/97] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-05-25  2:56   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 15/97] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-05-25 18:08   ` Matthew Brost
2021-05-25 19:37     ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost
2021-05-25  3:21   ` Matthew Brost
2021-05-25 13:10     ` Michal Wajdeczko
2021-05-25  3:21   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 17/97] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost
2021-05-25 16:14   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 18/97] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost
2021-05-25 18:15   ` Matthew Brost
2021-05-25 19:43     ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 19/97] drm/i915/guc: Always copy CT message to new allocation Matthew Brost
2021-05-25 18:25   ` Matthew Brost [this message]
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 20/97] drm/i915/guc: Introduce unified HXG messages Matthew Brost
2021-05-11 15:16   ` Daniel Vetter
2021-05-11 17:59     ` Matthew Brost
2021-05-11 22:11     ` Michal Wajdeczko
2021-05-12  8:40       ` Daniel Vetter
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 22/97] drm/i915/guc: Update CTB response status Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 23/97] drm/i915/guc: Support per context scheduling policies Matthew Brost
2021-05-25  1:15   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 24/97] drm/i915/guc: Add flag for mark broken CTB Matthew Brost
2021-05-27 19:44   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 25/97] drm/i915/guc: New definition of the CTB descriptor Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 26/97] drm/i915/guc: New definition of the CTB registration action Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 27/97] drm/i915/guc: New CTB based communication Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 28/97] drm/i915/guc: Kill guc_clients.ct_pool Matthew Brost
2021-05-25  1:01   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 29/97] drm/i915/guc: Update firmware to v60.1.2 Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 30/97] drm/i915/uc: turn on GuC/HuC auto mode by default Matthew Brost
2021-05-24 11:00   ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 31/97] drm/i915/guc: Early initialization of GuC send registers Matthew Brost
2021-05-26 20:28   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 32/97] drm/i915: Introduce i915_sched_engine object Matthew Brost
2021-05-11 15:18   ` Daniel Vetter
2021-05-11 17:56     ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 33/97] drm/i915: Engine relative MMIO Matthew Brost
2021-05-25  9:05   ` Tvrtko Ursulin
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 34/97] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost
2021-05-26 20:41   ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 35/97] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-05-24 11:59   ` Michal Wajdeczko
2021-05-25 17:32     ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 36/97] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-05-24 12:21   ` Michal Wajdeczko
2021-05-25 17:30     ` Matthew Brost
2021-05-25  9:21   ` Tvrtko Ursulin
2021-05-25 17:21     ` Matthew Brost
2021-05-26  8:57       ` Tvrtko Ursulin
2021-05-26 18:10         ` Matthew Brost
2021-05-27 10:02           ` Tvrtko Ursulin
2021-05-27 14:35             ` Matthew Brost
2021-05-27 15:11               ` Tvrtko Ursulin
2021-06-07 17:31                 ` Matthew Brost
2021-06-08  8:39                   ` Tvrtko Ursulin
2021-06-08  8:46                     ` Daniel Vetter
2021-06-09 23:10                       ` Matthew Brost
2021-06-10 15:27                         ` Daniel Vetter
2021-06-24 16:38                           ` Matthew Brost
2021-06-24 17:25                             ` Daniel Vetter
2021-06-09 13:58                     ` Michal Wajdeczko
2021-06-09 23:05                       ` Matthew Brost
2021-06-09 14:14                   ` Michal Wajdeczko
2021-06-09 23:13                     ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 37/97] drm/i915/guc: Add stall timer to " Matthew Brost
2021-05-24 12:58   ` Michal Wajdeczko
2021-05-24 18:35     ` Matthew Brost
2021-05-25 14:15       ` Michal Wajdeczko
2021-05-25 16:54         ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 38/97] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-05-24 13:31   ` Michal Wajdeczko
2021-05-25 17:39     ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 39/97] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-05-24 13:43   ` Michal Wajdeczko
2021-05-24 18:40     ` Matthew Brost
2021-05-25  9:24   ` Tvrtko Ursulin
2021-05-25 17:15     ` Matthew Brost
2021-05-26  9:30       ` Tvrtko Ursulin
2021-05-26 18:20         ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 40/97] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-05-24 13:45   ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 41/97] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 42/97] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 43/97] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-05-11 15:26   ` Daniel Vetter
2021-05-11 17:01     ` Matthew Brost
2021-05-11 17:43       ` Daniel Vetter
2021-05-11 19:34         ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 44/97] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-05-25  9:43   ` Tvrtko Ursulin
2021-05-25 17:10     ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 45/97] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 46/97] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-05-29 20:32   ` Michal Wajdeczko
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 47/97] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 48/97] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 49/97] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-05-11 15:37   ` Daniel Vetter
2021-05-11 16:31     ` Matthew Brost
2021-05-26 10:26   ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 50/97] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 51/97] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 52/97] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 53/97] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-05-25  9:52   ` Tvrtko Ursulin
2021-05-25 17:01     ` Matthew Brost
2021-05-26  9:25       ` Tvrtko Ursulin
2021-05-26 18:15         ` Matthew Brost
2021-05-27  8:41           ` Tvrtko Ursulin
2021-05-27 14:38             ` Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 54/97] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 55/97] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-05-25 10:06   ` Tvrtko Ursulin
2021-05-25 17:07     ` Matthew Brost
2021-05-26  9:21       ` Tvrtko Ursulin
2021-05-26 18:18         ` Matthew Brost
2021-05-27  9:02           ` Tvrtko Ursulin
2021-05-27 14:37             ` Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 56/97] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 57/97] drm/i915/guc: Add several request trace points Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 58/97] drm/i915: Add intel_context tracing Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 59/97] drm/i915/guc: GuC virtual engines Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 60/97] drm/i915: Track 'serial' counts for " Matthew Brost
2021-05-25 10:16   ` Tvrtko Ursulin
2021-05-25 17:52     ` Matthew Brost
2021-05-26  8:40       ` Tvrtko Ursulin
2021-05-26 18:45         ` John Harrison
2021-05-27  8:53           ` Tvrtko Ursulin
2021-05-27 17:01             ` John Harrison
2021-06-01  9:31               ` Tvrtko Ursulin
2021-06-02  1:20                 ` John Harrison
2021-06-02 12:04                   ` Tvrtko Ursulin
2021-06-02 12:09   ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 61/97] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-06-02 12:18   ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 62/97] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 63/97] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-06-02 13:31   ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 64/97] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-06-02 14:33   ` Tvrtko Ursulin
2021-06-04  3:17     ` Matthew Brost
2021-06-04  8:16       ` Daniel Vetter
2021-06-04 18:02         ` Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 65/97] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-06-02 14:36   ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 66/97] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-05-11  8:16   ` [Intel-gfx] [drm/i915/guc] 07336fb545: WARNING:at_drivers/gpu/drm/i915/gt/uc/intel_uc.c:#__uc_sanitize[i915] kernel test robot
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 67/97] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 68/97] drm/i915/guc: Handle context reset notification Matthew Brost
2021-05-11 16:25   ` Daniel Vetter
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 69/97] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 70/97] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 71/97] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 72/97] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 73/97] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 74/97] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-05-11 16:28   ` Daniel Vetter
2021-05-11 17:12     ` Matthew Brost
2021-05-11 17:45       ` Daniel Vetter
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 75/97] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 76/97] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 77/97] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 78/97] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 79/97] drm/i915/guc: Don't call ring_is_idle in GuC submission Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 80/97] drm/i915/guc: Implement banned contexts for " Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 81/97] drm/i915/guc: Allow flexible number of context ids Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 82/97] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 83/97] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 85/97] drm/i915/guc: Introduce guc_submit_engine object Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 86/97] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 87/97] drm/i915/guc: Implement GuC priority management Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 88/97] drm/i915/guc: Support request cancellation Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 89/97] drm/i915/guc: Check return of __xa_store when registering a context Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 90/97] drm/i915/guc: Non-static lrc descriptor registration buffer Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 91/97] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 92/97] drm/i915: Add GT PM delayed worker Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 93/97] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 94/97] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 95/97] drm/i915/guc: Selftest for GuC flow control Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 96/97] drm/i915/guc: Update GuC documentation Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 97/97] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-05-09 17:12 ` [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915 Martin Peres
2021-05-09 23:11   ` Jason Ekstrand
2021-05-10 13:55     ` Martin Peres
2021-05-10 16:25       ` Jason Ekstrand
2021-05-11  8:01         ` Martin Peres
2021-05-10 16:33       ` Daniel Vetter
2021-05-10 18:30         ` Francisco Jerez
2021-05-11  8:06         ` Martin Peres
2021-05-11 15:26           ` Bloomfield, Jon
2021-05-11 16:39             ` Matthew Brost
2021-05-12  6:26               ` Martin Peres
2021-05-14 16:31                 ` Jason Ekstrand
2021-05-25 15:37                   ` Alex Deucher
2021-05-11  2:58     ` Dixit, Ashutosh
2021-05-11  7:47       ` Martin Peres
2021-05-14 11:11 ` Tvrtko Ursulin
2021-05-14 16:36   ` Jason Ekstrand
2021-05-14 16:46     ` Matthew Brost
2021-05-14 16:41   ` Matthew Brost
2021-05-25 10:32 ` Tvrtko Ursulin
2021-05-25 16:45   ` Matthew Brost
2021-06-02 15:27     ` Tvrtko Ursulin
2021-06-02 18:57       ` Daniel Vetter
2021-06-03  3:41         ` Matthew Brost
2021-06-03  4:47           ` Daniel Vetter
2021-06-03  9:49             ` Tvrtko Ursulin
2021-06-03 10:52           ` Tvrtko Ursulin
2021-06-03  4:10       ` Matthew Brost
2021-06-03  8:51         ` Tvrtko Ursulin
2021-06-03 16:34           ` Matthew Brost

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