From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Matthew Brost <matthew.brost@intel.com>,
intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: jason.ekstrand@intel.com, daniel.vetter@intel.com
Subject: Re: [Intel-gfx] [RFC PATCH 03/97] drm/i915/gt: Move CS interrupt handler to the backend
Date: Tue, 25 May 2021 09:45:43 +0100 [thread overview]
Message-ID: <dac73410-1850-a005-ca57-dc302482da5f@linux.intel.com> (raw)
In-Reply-To: <20210506191451.77768-4-matthew.brost@intel.com>
On 06/05/2021 20:13, Matthew Brost wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> The different submission backends each have their own preferred
> behaviour and interrupt setup. Let each handle their own interrupts.
>
> This becomes more useful later as we to extract the use of auxiliary
> state in the interrupt handler that is backend specific.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Same, this patch had my r-b already so I'll repeat it:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +---
> .../drm/i915/gt/intel_execlists_submission.c | 41 ++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 82 ++++++-------------
> drivers/gpu/drm/i915/gt/intel_gt_irq.h | 23 ++++++
> .../gpu/drm/i915/gt/intel_ring_submission.c | 8 ++
> drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++-
> drivers/gpu/drm/i915/i915_irq.c | 10 ++-
> 9 files changed, 124 insertions(+), 74 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 0618379b68ca..828e1669f92c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -255,6 +255,11 @@ static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
> intel_engine_set_hwsp_writemask(engine, ~0u);
> }
>
> +static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
> +{
> + GEM_DEBUG_WARN_ON(iir);
> +}
> +
> static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> {
> const struct engine_info *info = &intel_engines[id];
> @@ -292,6 +297,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> engine->hw_id = info->hw_id;
> engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
>
> + engine->irq_handler = nop_irq_handler;
> +
> engine->class = info->class;
> engine->instance = info->instance;
> __sprint_engine_name(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 883bafc44902..9ef349cd5cea 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -402,6 +402,7 @@ struct intel_engine_cs {
> u32 irq_enable_mask; /* bitmask to enable ring interrupt */
> void (*irq_enable)(struct intel_engine_cs *engine);
> void (*irq_disable)(struct intel_engine_cs *engine);
> + void (*irq_handler)(struct intel_engine_cs *engine, u16 iir);
>
> void (*sanitize)(struct intel_engine_cs *engine);
> int (*resume)(struct intel_engine_cs *engine);
> @@ -481,10 +482,9 @@ struct intel_engine_cs {
> #define I915_ENGINE_HAS_PREEMPTION BIT(2)
> #define I915_ENGINE_HAS_SEMAPHORES BIT(3)
> #define I915_ENGINE_HAS_TIMESLICES BIT(4)
> -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
> -#define I915_ENGINE_IS_VIRTUAL BIT(6)
> -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
> -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
> +#define I915_ENGINE_IS_VIRTUAL BIT(5)
> +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
> +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
> unsigned int flags;
>
> /*
> @@ -593,12 +593,6 @@ intel_engine_has_timeslices(const struct intel_engine_cs *engine)
> return engine->flags & I915_ENGINE_HAS_TIMESLICES;
> }
>
> -static inline bool
> -intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
> -{
> - return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> -}
> -
> static inline bool
> intel_engine_is_virtual(const struct intel_engine_cs *engine)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 9d2da5ccaef6..8db200422950 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -118,6 +118,7 @@
> #include "intel_engine_stats.h"
> #include "intel_execlists_submission.h"
> #include "intel_gt.h"
> +#include "intel_gt_irq.h"
> #include "intel_gt_pm.h"
> #include "intel_gt_requests.h"
> #include "intel_lrc.h"
> @@ -2384,6 +2385,45 @@ static void execlists_submission_tasklet(struct tasklet_struct *t)
> rcu_read_unlock();
> }
>
> +static void execlists_irq_handler(struct intel_engine_cs *engine, u16 iir)
> +{
> + bool tasklet = false;
> +
> + if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
> + u32 eir;
> +
> + /* Upper 16b are the enabling mask, rsvd for internal errors */
> + eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
> + ENGINE_TRACE(engine, "CS error: %x\n", eir);
> +
> + /* Disable the error interrupt until after the reset */
> + if (likely(eir)) {
> + ENGINE_WRITE(engine, RING_EMR, ~0u);
> + ENGINE_WRITE(engine, RING_EIR, eir);
> + WRITE_ONCE(engine->execlists.error_interrupt, eir);
> + tasklet = true;
> + }
> + }
> +
> + if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
> + WRITE_ONCE(engine->execlists.yield,
> + ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
> + ENGINE_TRACE(engine, "semaphore yield: %08x\n",
> + engine->execlists.yield);
> + if (del_timer(&engine->execlists.timer))
> + tasklet = true;
> + }
> +
> + if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
> + tasklet = true;
> +
> + if (iir & GT_RENDER_USER_INTERRUPT)
> + intel_engine_signal_breadcrumbs(engine);
> +
> + if (tasklet)
> + tasklet_hi_schedule(&engine->execlists.tasklet);
> +}
> +
> static void __execlists_kick(struct intel_engine_execlists *execlists)
> {
> /* Kick the tasklet for some interrupt coalescing and reset handling */
> @@ -3133,6 +3173,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> * until a more refined solution exists.
> */
> }
> + intel_engine_set_irq_handler(engine, execlists_irq_handler);
>
> engine->flags |= I915_ENGINE_SUPPORTS_STATS;
> if (!intel_vgpu_active(engine->i915)) {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 9fc6c912a4e5..d29126c458ba 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -20,48 +20,6 @@ static void guc_irq_handler(struct intel_guc *guc, u16 iir)
> intel_guc_to_host_event_handler(guc);
> }
>
> -static void
> -cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> -{
> - bool tasklet = false;
> -
> - if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
> - u32 eir;
> -
> - /* Upper 16b are the enabling mask, rsvd for internal errors */
> - eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);
> - ENGINE_TRACE(engine, "CS error: %x\n", eir);
> -
> - /* Disable the error interrupt until after the reset */
> - if (likely(eir)) {
> - ENGINE_WRITE(engine, RING_EMR, ~0u);
> - ENGINE_WRITE(engine, RING_EIR, eir);
> - WRITE_ONCE(engine->execlists.error_interrupt, eir);
> - tasklet = true;
> - }
> - }
> -
> - if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
> - WRITE_ONCE(engine->execlists.yield,
> - ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
> - ENGINE_TRACE(engine, "semaphore yield: %08x\n",
> - engine->execlists.yield);
> - if (del_timer(&engine->execlists.timer))
> - tasklet = true;
> - }
> -
> - if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
> - tasklet = true;
> -
> - if (iir & GT_RENDER_USER_INTERRUPT) {
> - intel_engine_signal_breadcrumbs(engine);
> - tasklet |= intel_engine_needs_breadcrumb_tasklet(engine);
> - }
> -
> - if (tasklet)
> - tasklet_hi_schedule(&engine->execlists.tasklet);
> -}
> -
> static u32
> gen11_gt_engine_identity(struct intel_gt *gt,
> const unsigned int bank, const unsigned int bit)
> @@ -122,7 +80,7 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
> engine = NULL;
>
> if (likely(engine))
> - return cs_irq_handler(engine, iir);
> + return intel_engine_cs_irq(engine, iir);
>
> WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
> class, instance);
> @@ -275,9 +233,12 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
> {
> if (gt_iir & GT_RENDER_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]);
> + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
> + gt_iir);
> +
> if (gt_iir & ILK_BSD_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]);
> + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
> + gt_iir);
> }
>
> static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
> @@ -301,11 +262,16 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
> void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
> {
> if (gt_iir & GT_RENDER_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]);
> + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
> + gt_iir);
> +
> if (gt_iir & GT_BSD_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]);
> + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
> + gt_iir >> 12);
> +
> if (gt_iir & GT_BLT_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]);
> + intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],
> + gt_iir >> 22);
>
> if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
> GT_BSD_CS_ERROR_INTERRUPT |
> @@ -324,10 +290,10 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
> if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> iir = raw_reg_read(regs, GEN8_GT_IIR(0));
> if (likely(iir)) {
> - cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
> - iir >> GEN8_RCS_IRQ_SHIFT);
> - cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
> - iir >> GEN8_BCS_IRQ_SHIFT);
> + intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
> + iir >> GEN8_RCS_IRQ_SHIFT);
> + intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],
> + iir >> GEN8_BCS_IRQ_SHIFT);
> raw_reg_write(regs, GEN8_GT_IIR(0), iir);
> }
> }
> @@ -335,10 +301,10 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
> if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
> iir = raw_reg_read(regs, GEN8_GT_IIR(1));
> if (likely(iir)) {
> - cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
> - iir >> GEN8_VCS0_IRQ_SHIFT);
> - cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
> - iir >> GEN8_VCS1_IRQ_SHIFT);
> + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
> + iir >> GEN8_VCS0_IRQ_SHIFT);
> + intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1],
> + iir >> GEN8_VCS1_IRQ_SHIFT);
> raw_reg_write(regs, GEN8_GT_IIR(1), iir);
> }
> }
> @@ -346,8 +312,8 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
> if (master_ctl & GEN8_GT_VECS_IRQ) {
> iir = raw_reg_read(regs, GEN8_GT_IIR(3));
> if (likely(iir)) {
> - cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
> - iir >> GEN8_VECS_IRQ_SHIFT);
> + intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
> + iir >> GEN8_VECS_IRQ_SHIFT);
> raw_reg_write(regs, GEN8_GT_IIR(3), iir);
> }
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> index f667e976fb2b..41cad38668c5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> @@ -8,6 +8,8 @@
>
> #include <linux/types.h>
>
> +#include "intel_engine_types.h"
> +
> struct intel_gt;
>
> #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
> @@ -39,4 +41,25 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);
> void gen8_gt_irq_reset(struct intel_gt *gt);
> void gen8_gt_irq_postinstall(struct intel_gt *gt);
>
> +static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir)
> +{
> + if (iir)
> + engine->irq_handler(engine, iir);
> +}
> +
> +static inline void
> +intel_engine_set_irq_handler(struct intel_engine_cs *engine,
> + void (*fn)(struct intel_engine_cs *engine,
> + u16 iir))
> +{
> + /*
> + * As the interrupt is live as allocate and setup the engines,
> + * err on the side of caution and apply barriers to updating
> + * the irq handler callback. This assures that when we do use
> + * the engine, we will receive interrupts only to ourselves,
> + * and not lose any.
> + */
> + smp_store_mb(engine->irq_handler, fn);
> +}
> +
> #endif /* INTEL_GT_IRQ_H */
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 5f4f7f1df48f..2b6dffcc2262 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -12,6 +12,7 @@
> #include "intel_breadcrumbs.h"
> #include "intel_context.h"
> #include "intel_gt.h"
> +#include "intel_gt_irq.h"
> #include "intel_reset.h"
> #include "intel_ring.h"
> #include "shmem_utils.h"
> @@ -1017,10 +1018,17 @@ static void ring_release(struct intel_engine_cs *engine)
> intel_timeline_put(engine->legacy.timeline);
> }
>
> +static void irq_handler(struct intel_engine_cs *engine, u16 iir)
> +{
> + intel_engine_signal_breadcrumbs(engine);
> +}
> +
> static void setup_irq(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> + intel_engine_set_irq_handler(engine, irq_handler);
> +
> if (INTEL_GEN(i915) >= 6) {
> engine->irq_enable = gen6_irq_enable;
> engine->irq_disable = gen6_irq_disable;
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 405d814e9040..97cab1b99871 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1774,7 +1774,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
> return;
>
> if (pm_iir & PM_VEBOX_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(gt->engine[VECS0]);
> + intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10);
>
> if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
> DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 17b551a0c89f..335719f17490 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -11,6 +11,7 @@
> #include "gt/intel_context.h"
> #include "gt/intel_engine_pm.h"
> #include "gt/intel_gt.h"
> +#include "gt/intel_gt_irq.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_lrc.h"
> #include "gt/intel_mocs.h"
> @@ -264,6 +265,14 @@ static void guc_submission_tasklet(struct tasklet_struct *t)
> spin_unlock_irqrestore(&engine->active.lock, flags);
> }
>
> +static void cs_irq_handler(struct intel_engine_cs *engine, u16 iir)
> +{
> + if (iir & GT_RENDER_USER_INTERRUPT) {
> + intel_engine_signal_breadcrumbs(engine);
> + tasklet_hi_schedule(&engine->execlists.tasklet);
> + }
> +}
> +
> static void guc_reset_prepare(struct intel_engine_cs *engine)
> {
> struct intel_engine_execlists * const execlists = &engine->execlists;
> @@ -645,7 +654,6 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> }
> engine->set_default_submission = guc_set_default_submission;
>
> - engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> engine->flags |= I915_ENGINE_HAS_PREEMPTION;
>
> /*
> @@ -681,6 +689,7 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
> static inline void guc_default_irqs(struct intel_engine_cs *engine)
> {
> engine->irq_keep_mask = GT_RENDER_USER_INTERRUPT;
> + intel_engine_set_irq_handler(engine, cs_irq_handler);
> }
>
> int intel_guc_submission_setup(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f6967a93ec7a..d58118806299 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4014,7 +4014,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
> intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
>
> if (iir & I915_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
> + intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
> @@ -4122,7 +4122,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
> intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
>
> if (iir & I915_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
> + intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
> @@ -4267,10 +4267,12 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
> intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
>
> if (iir & I915_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
> + intel_engine_cs_irq(dev_priv->gt.engine[RCS0],
> + iir);
>
> if (iir & I915_BSD_USER_INTERRUPT)
> - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
> + intel_engine_cs_irq(dev_priv->gt.engine[VCS0],
> + iir >> 25);
>
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>
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next prev parent reply other threads:[~2021-05-25 8:45 UTC|newest]
Thread overview: 251+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 19:13 [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915 Matthew Brost
2021-05-06 19:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 01/97] drm/i915/gt: Move engine setup out of set_default_submission Matthew Brost
2021-05-19 0:25 ` Matthew Brost
2021-05-25 8:44 ` Tvrtko Ursulin
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 02/97] drm/i915/gt: Move submission_method into intel_gt Matthew Brost
2021-05-19 3:10 ` Matthew Brost
2021-05-25 8:44 ` Tvrtko Ursulin
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 03/97] drm/i915/gt: Move CS interrupt handler to the backend Matthew Brost
2021-05-19 3:31 ` Matthew Brost
2021-05-25 8:45 ` Tvrtko Ursulin [this message]
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 04/97] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost
2021-05-20 16:47 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 05/97] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost
2021-05-24 10:30 ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost
2021-05-25 0:31 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 07/97] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost
2021-05-24 10:48 ` Michal Wajdeczko
2021-05-25 0:36 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 08/97] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost
2021-05-24 23:52 ` Michał Winiarski
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 09/97] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost
2021-05-25 2:38 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 10/97] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost
2021-05-25 0:42 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 11/97] drm/i915/guc: Only rely on own CTB size Matthew Brost
2021-05-25 2:47 ` Matthew Brost
2021-05-25 12:48 ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 12/97] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost
2021-05-25 2:53 ` Matthew Brost
2021-05-25 13:07 ` Michal Wajdeczko
2021-05-25 16:56 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 13/97] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-05-25 3:15 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 14/97] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-05-25 2:56 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 15/97] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-05-25 18:08 ` Matthew Brost
2021-05-25 19:37 ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost
2021-05-25 3:21 ` Matthew Brost
2021-05-25 13:10 ` Michal Wajdeczko
2021-05-25 3:21 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 17/97] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost
2021-05-25 16:14 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 18/97] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost
2021-05-25 18:15 ` Matthew Brost
2021-05-25 19:43 ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 19/97] drm/i915/guc: Always copy CT message to new allocation Matthew Brost
2021-05-25 18:25 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 20/97] drm/i915/guc: Introduce unified HXG messages Matthew Brost
2021-05-11 15:16 ` Daniel Vetter
2021-05-11 17:59 ` Matthew Brost
2021-05-11 22:11 ` Michal Wajdeczko
2021-05-12 8:40 ` Daniel Vetter
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 22/97] drm/i915/guc: Update CTB response status Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 23/97] drm/i915/guc: Support per context scheduling policies Matthew Brost
2021-05-25 1:15 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 24/97] drm/i915/guc: Add flag for mark broken CTB Matthew Brost
2021-05-27 19:44 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 25/97] drm/i915/guc: New definition of the CTB descriptor Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 26/97] drm/i915/guc: New definition of the CTB registration action Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 27/97] drm/i915/guc: New CTB based communication Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 28/97] drm/i915/guc: Kill guc_clients.ct_pool Matthew Brost
2021-05-25 1:01 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 29/97] drm/i915/guc: Update firmware to v60.1.2 Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 30/97] drm/i915/uc: turn on GuC/HuC auto mode by default Matthew Brost
2021-05-24 11:00 ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 31/97] drm/i915/guc: Early initialization of GuC send registers Matthew Brost
2021-05-26 20:28 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 32/97] drm/i915: Introduce i915_sched_engine object Matthew Brost
2021-05-11 15:18 ` Daniel Vetter
2021-05-11 17:56 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 33/97] drm/i915: Engine relative MMIO Matthew Brost
2021-05-25 9:05 ` Tvrtko Ursulin
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 34/97] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost
2021-05-26 20:41 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 35/97] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-05-24 11:59 ` Michal Wajdeczko
2021-05-25 17:32 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 36/97] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-05-24 12:21 ` Michal Wajdeczko
2021-05-25 17:30 ` Matthew Brost
2021-05-25 9:21 ` Tvrtko Ursulin
2021-05-25 17:21 ` Matthew Brost
2021-05-26 8:57 ` Tvrtko Ursulin
2021-05-26 18:10 ` Matthew Brost
2021-05-27 10:02 ` Tvrtko Ursulin
2021-05-27 14:35 ` Matthew Brost
2021-05-27 15:11 ` Tvrtko Ursulin
2021-06-07 17:31 ` Matthew Brost
2021-06-08 8:39 ` Tvrtko Ursulin
2021-06-08 8:46 ` Daniel Vetter
2021-06-09 23:10 ` Matthew Brost
2021-06-10 15:27 ` Daniel Vetter
2021-06-24 16:38 ` Matthew Brost
2021-06-24 17:25 ` Daniel Vetter
2021-06-09 13:58 ` Michal Wajdeczko
2021-06-09 23:05 ` Matthew Brost
2021-06-09 14:14 ` Michal Wajdeczko
2021-06-09 23:13 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 37/97] drm/i915/guc: Add stall timer to " Matthew Brost
2021-05-24 12:58 ` Michal Wajdeczko
2021-05-24 18:35 ` Matthew Brost
2021-05-25 14:15 ` Michal Wajdeczko
2021-05-25 16:54 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 38/97] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-05-24 13:31 ` Michal Wajdeczko
2021-05-25 17:39 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 39/97] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-05-24 13:43 ` Michal Wajdeczko
2021-05-24 18:40 ` Matthew Brost
2021-05-25 9:24 ` Tvrtko Ursulin
2021-05-25 17:15 ` Matthew Brost
2021-05-26 9:30 ` Tvrtko Ursulin
2021-05-26 18:20 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 40/97] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-05-24 13:45 ` Michal Wajdeczko
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 41/97] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 42/97] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 43/97] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-05-11 15:26 ` Daniel Vetter
2021-05-11 17:01 ` Matthew Brost
2021-05-11 17:43 ` Daniel Vetter
2021-05-11 19:34 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 44/97] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-05-25 9:43 ` Tvrtko Ursulin
2021-05-25 17:10 ` Matthew Brost
2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 45/97] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 46/97] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-05-29 20:32 ` Michal Wajdeczko
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 47/97] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 48/97] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 49/97] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-05-11 15:37 ` Daniel Vetter
2021-05-11 16:31 ` Matthew Brost
2021-05-26 10:26 ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 50/97] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 51/97] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 52/97] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 53/97] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-05-25 9:52 ` Tvrtko Ursulin
2021-05-25 17:01 ` Matthew Brost
2021-05-26 9:25 ` Tvrtko Ursulin
2021-05-26 18:15 ` Matthew Brost
2021-05-27 8:41 ` Tvrtko Ursulin
2021-05-27 14:38 ` Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 54/97] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 55/97] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-05-25 10:06 ` Tvrtko Ursulin
2021-05-25 17:07 ` Matthew Brost
2021-05-26 9:21 ` Tvrtko Ursulin
2021-05-26 18:18 ` Matthew Brost
2021-05-27 9:02 ` Tvrtko Ursulin
2021-05-27 14:37 ` Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 56/97] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 57/97] drm/i915/guc: Add several request trace points Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 58/97] drm/i915: Add intel_context tracing Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 59/97] drm/i915/guc: GuC virtual engines Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 60/97] drm/i915: Track 'serial' counts for " Matthew Brost
2021-05-25 10:16 ` Tvrtko Ursulin
2021-05-25 17:52 ` Matthew Brost
2021-05-26 8:40 ` Tvrtko Ursulin
2021-05-26 18:45 ` John Harrison
2021-05-27 8:53 ` Tvrtko Ursulin
2021-05-27 17:01 ` John Harrison
2021-06-01 9:31 ` Tvrtko Ursulin
2021-06-02 1:20 ` John Harrison
2021-06-02 12:04 ` Tvrtko Ursulin
2021-06-02 12:09 ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 61/97] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-06-02 12:18 ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 62/97] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 63/97] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-06-02 13:31 ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 64/97] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-06-02 14:33 ` Tvrtko Ursulin
2021-06-04 3:17 ` Matthew Brost
2021-06-04 8:16 ` Daniel Vetter
2021-06-04 18:02 ` Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 65/97] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-06-02 14:36 ` Tvrtko Ursulin
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 66/97] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-05-11 8:16 ` [Intel-gfx] [drm/i915/guc] 07336fb545: WARNING:at_drivers/gpu/drm/i915/gt/uc/intel_uc.c:#__uc_sanitize[i915] kernel test robot
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 67/97] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 68/97] drm/i915/guc: Handle context reset notification Matthew Brost
2021-05-11 16:25 ` Daniel Vetter
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 69/97] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 70/97] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 71/97] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 72/97] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 73/97] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 74/97] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-05-11 16:28 ` Daniel Vetter
2021-05-11 17:12 ` Matthew Brost
2021-05-11 17:45 ` Daniel Vetter
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 75/97] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 76/97] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 77/97] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 78/97] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 79/97] drm/i915/guc: Don't call ring_is_idle in GuC submission Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 80/97] drm/i915/guc: Implement banned contexts for " Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 81/97] drm/i915/guc: Allow flexible number of context ids Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 82/97] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 83/97] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 85/97] drm/i915/guc: Introduce guc_submit_engine object Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 86/97] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 87/97] drm/i915/guc: Implement GuC priority management Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 88/97] drm/i915/guc: Support request cancellation Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 89/97] drm/i915/guc: Check return of __xa_store when registering a context Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 90/97] drm/i915/guc: Non-static lrc descriptor registration buffer Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 91/97] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 92/97] drm/i915: Add GT PM delayed worker Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 93/97] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 94/97] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 95/97] drm/i915/guc: Selftest for GuC flow control Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 96/97] drm/i915/guc: Update GuC documentation Matthew Brost
2021-05-06 19:14 ` [Intel-gfx] [RFC PATCH 97/97] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-05-09 17:12 ` [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915 Martin Peres
2021-05-09 23:11 ` Jason Ekstrand
2021-05-10 13:55 ` Martin Peres
2021-05-10 16:25 ` Jason Ekstrand
2021-05-11 8:01 ` Martin Peres
2021-05-10 16:33 ` Daniel Vetter
2021-05-10 18:30 ` Francisco Jerez
2021-05-11 8:06 ` Martin Peres
2021-05-11 15:26 ` Bloomfield, Jon
2021-05-11 16:39 ` Matthew Brost
2021-05-12 6:26 ` Martin Peres
2021-05-14 16:31 ` Jason Ekstrand
2021-05-25 15:37 ` Alex Deucher
2021-05-11 2:58 ` Dixit, Ashutosh
2021-05-11 7:47 ` Martin Peres
2021-05-14 11:11 ` Tvrtko Ursulin
2021-05-14 16:36 ` Jason Ekstrand
2021-05-14 16:46 ` Matthew Brost
2021-05-14 16:41 ` Matthew Brost
2021-05-25 10:32 ` Tvrtko Ursulin
2021-05-25 16:45 ` Matthew Brost
2021-06-02 15:27 ` Tvrtko Ursulin
2021-06-02 18:57 ` Daniel Vetter
2021-06-03 3:41 ` Matthew Brost
2021-06-03 4:47 ` Daniel Vetter
2021-06-03 9:49 ` Tvrtko Ursulin
2021-06-03 10:52 ` Tvrtko Ursulin
2021-06-03 4:10 ` Matthew Brost
2021-06-03 8:51 ` Tvrtko Ursulin
2021-06-03 16:34 ` Matthew Brost
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