From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Gwan-gyeong Mun" <gwan-gyeong.mun@intel.com>,
"José Roberto de Souza" <jose.souza@intel.com>
Subject: [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update
Date: Thu, 9 Sep 2021 16:07:23 -0700 [thread overview]
Message-ID: <20210909230725.33735-3-jose.souza@intel.com> (raw)
In-Reply-To: <20210909230725.33735-1-jose.souza@intel.com>
BSpec states that the minimum number of frames before selective update
is 2, so making sure this minimum limit is fulfilled.
BSpec: 50422
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 92c0b2159559f..1a3effa3ce709 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -510,7 +510,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
val |= EDP_Y_COORDINATE_ENABLE;
- val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
+ val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));
val |= intel_psr2_get_tp_time(intel_dp);
/* Wa_22012278275:adl-p */
--
2.33.0
next prev parent reply other threads:[~2021-09-09 23:02 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
2021-09-09 23:07 ` [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds José Roberto de Souza
2021-09-10 13:38 ` Gwan-gyeong Mun
2021-09-10 16:29 ` Souza, Jose
2021-09-13 16:09 ` Gwan-gyeong Mun
2021-09-13 17:00 ` Souza, Jose
2021-09-14 12:39 ` Gwan-gyeong Mun
2021-09-09 23:07 ` José Roberto de Souza [this message]
2021-09-10 13:26 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area José Roberto de Souza
2021-09-13 16:03 ` Gwan-gyeong Mun
2021-09-13 16:45 ` Souza, Jose
2021-09-14 12:42 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled José Roberto de Souza
2021-09-10 13:29 ` Gwan-gyeong Mun
2021-09-10 0:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation Patchwork
2021-09-10 0:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-10 2:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-10 13:39 ` [Intel-gfx] [PATCH 1/5] " Gwan-gyeong Mun
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