From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
Date: Fri, 10 Sep 2021 16:39:41 +0300 [thread overview]
Message-ID: <b5b28181-a1e6-3b64-84e7-18fcffc4f090@intel.com> (raw)
In-Reply-To: <20210909230725.33735-1-jose.souza@intel.com>
Looks good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> As the SU_REGION_START begins at 0, the SU_REGION_END should be number
> of lines - 1.
>
> BSpec: 50424
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3f6fb7d67f84d..36816abb3bcc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1501,7 +1501,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>
> if (IS_ALDERLAKE_P(dev_priv)) {
> val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
> - val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
> + val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
> } else {
> drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
>
>
prev parent reply other threads:[~2021-09-10 13:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
2021-09-09 23:07 ` [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds José Roberto de Souza
2021-09-10 13:38 ` Gwan-gyeong Mun
2021-09-10 16:29 ` Souza, Jose
2021-09-13 16:09 ` Gwan-gyeong Mun
2021-09-13 17:00 ` Souza, Jose
2021-09-14 12:39 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update José Roberto de Souza
2021-09-10 13:26 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area José Roberto de Souza
2021-09-13 16:03 ` Gwan-gyeong Mun
2021-09-13 16:45 ` Souza, Jose
2021-09-14 12:42 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled José Roberto de Souza
2021-09-10 13:29 ` Gwan-gyeong Mun
2021-09-10 0:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation Patchwork
2021-09-10 0:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-10 2:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-10 13:39 ` Gwan-gyeong Mun [this message]
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