From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 9/9] drm/i915: Allow per-lane drive settings with LTTPRs
Date: Wed, 29 Sep 2021 19:55:25 +0300 [thread overview]
Message-ID: <20210929165525.11410-1-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210927182455.27119-10-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
LTTPRs should support per-lane drive settings I think, and even if
they don't they should implement their own fallback logic to determine
suitable common drive settings to use for all the lanes.
v2: Actually check the correct thing
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index f26c44a6b568..eeea6c73e218 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -304,7 +304,7 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
- return false;
+ return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy);
}
static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
--
2.32.0
next prev parent reply other threads:[~2021-09-29 16:55 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala
2021-09-27 18:24 ` [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ Ville Syrjala
2021-09-29 16:59 ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() Ville Syrjala
2021-09-29 19:17 ` Imre Deak
2021-09-30 7:33 ` Ville Syrjälä
2021-09-27 18:24 ` [Intel-gfx] [PATCH 3/9] drm/i915: Nuke usless .set_signal_levels() wrappers Ville Syrjala
2021-09-29 19:43 ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 4/9] drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() Ville Syrjala
2021-09-29 19:48 ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 5/9] drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() Ville Syrjala
2021-09-29 20:09 ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 6/9] drm/i915: Nuke intel_ddi_hdmi_num_entries() Ville Syrjala
2021-09-29 20:11 ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 7/9] drm/i915: Pass the lane to intel_ddi_level() Ville Syrjala
2021-09-29 20:14 ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 8/9] drm/i915: Prepare link training for per-lane drive settings Ville Syrjala
2021-09-28 21:22 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-09-29 16:54 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2021-09-29 20:26 ` Imre Deak
2021-09-30 7:07 ` Ville Syrjälä
2021-09-27 18:24 ` [Intel-gfx] [PATCH 9/9] drm/i915: Allow per-lane drive settings with LTTPRs Ville Syrjala
2021-09-29 16:55 ` Ville Syrjala [this message]
2021-09-29 20:27 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-09-27 20:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work Patchwork
2021-09-27 20:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-27 20:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-28 1:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-28 21:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev2) Patchwork
2021-09-28 21:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-28 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-29 0:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-29 17:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev4) Patchwork
2021-09-29 17:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-29 18:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-29 21:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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