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From: Matthew Brost <matthew.brost@intel.com>
To: John Harrison <john.c.harrison@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	daniele.ceraolospurio@intel.com
Subject: Re: [Intel-gfx] [PATCH 03/26] drm/i915/guc: Take engine PM when a context is pinned with GuC submission
Date: Thu, 7 Oct 2021 08:19:47 -0700	[thread overview]
Message-ID: <20211007151947.GA27846@jons-linux-dev-box> (raw)
In-Reply-To: <a2d5377a-ec8e-40ec-d0cf-c91aa51bba48@intel.com>

On Wed, Oct 06, 2021 at 08:45:42PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Taking a PM reference to prevent intel_gt_wait_for_idle from short
> > circuiting while a scheduling of user context could be enabled.
> I'm not sure what 'while a scheduling of user context could be enabled'
> means.
>

Not really sure how this isn't clear.

It means if a user context has scheduling enabled this function cannot
short circuit returning idle.

Matt
 
> John.
> 
> > Returning GT idle when it is not can cause all sorts of issues
> > throughout the stack.
> > 
> > v2:
> >   (Daniel Vetter)
> >    - Add might_lock annotations to pin / unpin function
> > v3:
> >   (CI)
> >    - Drop intel_engine_pm_might_put from unpin path as an async put is
> >      used
> > v4:
> >   (John Harrison)
> >    - Make intel_engine_pm_might_get/put work with GuC virtual engines
> >    - Update commit message
> > 
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >   drivers/gpu/drm/i915/gt/intel_context.c       |  2 ++
> >   drivers/gpu/drm/i915/gt/intel_engine_pm.h     | 32 +++++++++++++++++
> >   drivers/gpu/drm/i915/gt/intel_gt_pm.h         | 10 ++++++
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 36 +++++++++++++++++--
> >   drivers/gpu/drm/i915/intel_wakeref.h          | 12 +++++++
> >   5 files changed, 89 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> > index 1076066f41e0..f601323b939f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -240,6 +240,8 @@ int __intel_context_do_pin_ww(struct intel_context *ce,
> >   	if (err)
> >   		goto err_post_unpin;
> > +	intel_engine_pm_might_get(ce->engine);
> > +
> >   	if (unlikely(intel_context_is_closed(ce))) {
> >   		err = -ENOENT;
> >   		goto err_unlock;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > index 6fdeae668e6e..d68675925b79 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > @@ -6,9 +6,11 @@
> >   #ifndef INTEL_ENGINE_PM_H
> >   #define INTEL_ENGINE_PM_H
> > +#include "i915_drv.h"
> >   #include "i915_request.h"
> >   #include "intel_engine_types.h"
> >   #include "intel_wakeref.h"
> > +#include "intel_gt_pm.h"
> >   static inline bool
> >   intel_engine_pm_is_awake(const struct intel_engine_cs *engine)
> > @@ -31,6 +33,21 @@ static inline bool intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)
> >   	return intel_wakeref_get_if_active(&engine->wakeref);
> >   }
> > +static inline void intel_engine_pm_might_get(struct intel_engine_cs *engine)
> > +{
> > +	if (!intel_engine_is_virtual(engine)) {
> > +		intel_wakeref_might_get(&engine->wakeref);
> > +	} else {
> > +		struct intel_gt *gt = engine->gt;
> > +		struct intel_engine_cs *tengine;
> > +		intel_engine_mask_t tmp, mask = engine->mask;
> > +
> > +		for_each_engine_masked(tengine, gt, mask, tmp)
> > +			intel_wakeref_might_get(&tengine->wakeref);
> > +	}
> > +	intel_gt_pm_might_get(engine->gt);
> > +}
> > +
> >   static inline void intel_engine_pm_put(struct intel_engine_cs *engine)
> >   {
> >   	intel_wakeref_put(&engine->wakeref);
> > @@ -52,6 +69,21 @@ static inline void intel_engine_pm_flush(struct intel_engine_cs *engine)
> >   	intel_wakeref_unlock_wait(&engine->wakeref);
> >   }
> > +static inline void intel_engine_pm_might_put(struct intel_engine_cs *engine)
> > +{
> > +	if (!intel_engine_is_virtual(engine)) {
> > +		intel_wakeref_might_put(&engine->wakeref);
> > +	} else {
> > +		struct intel_gt *gt = engine->gt;
> > +		struct intel_engine_cs *tengine;
> > +		intel_engine_mask_t tmp, mask = engine->mask;
> > +
> > +		for_each_engine_masked(tengine, gt, mask, tmp)
> > +			intel_wakeref_might_put(&tengine->wakeref);
> > +	}
> > +	intel_gt_pm_might_put(engine->gt);
> > +}
> > +
> >   static inline struct i915_request *
> >   intel_engine_create_kernel_request(struct intel_engine_cs *engine)
> >   {
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > index 05de6c1af25b..bc898df7a48c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > @@ -31,6 +31,11 @@ static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
> >   	return intel_wakeref_get_if_active(&gt->wakeref);
> >   }
> > +static inline void intel_gt_pm_might_get(struct intel_gt *gt)
> > +{
> > +	intel_wakeref_might_get(&gt->wakeref);
> > +}
> > +
> >   static inline void intel_gt_pm_put(struct intel_gt *gt)
> >   {
> >   	intel_wakeref_put(&gt->wakeref);
> > @@ -41,6 +46,11 @@ static inline void intel_gt_pm_put_async(struct intel_gt *gt)
> >   	intel_wakeref_put_async(&gt->wakeref);
> >   }
> > +static inline void intel_gt_pm_might_put(struct intel_gt *gt)
> > +{
> > +	intel_wakeref_might_put(&gt->wakeref);
> > +}
> > +
> >   #define with_intel_gt_pm(gt, tmp) \
> >   	for (tmp = 1, intel_gt_pm_get(gt); tmp; \
> >   	     intel_gt_pm_put(gt), tmp = 0)
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 17da2fea1bff..8b82da50c2bc 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1571,7 +1571,12 @@ static int guc_context_pre_pin(struct intel_context *ce,
> >   static int guc_context_pin(struct intel_context *ce, void *vaddr)
> >   {
> > -	return __guc_context_pin(ce, ce->engine, vaddr);
> > +	int ret = __guc_context_pin(ce, ce->engine, vaddr);
> > +
> > +	if (likely(!ret && !intel_context_is_barrier(ce)))
> > +		intel_engine_pm_get(ce->engine);
> > +
> > +	return ret;
> >   }
> >   static void guc_context_unpin(struct intel_context *ce)
> > @@ -1580,6 +1585,9 @@ static void guc_context_unpin(struct intel_context *ce)
> >   	unpin_guc_id(guc, ce);
> >   	lrc_unpin(ce);
> > +
> > +	if (likely(!intel_context_is_barrier(ce)))
> > +		intel_engine_pm_put_async(ce->engine);
> >   }
> >   static void guc_context_post_unpin(struct intel_context *ce)
> > @@ -2341,8 +2349,30 @@ static int guc_virtual_context_pre_pin(struct intel_context *ce,
> >   static int guc_virtual_context_pin(struct intel_context *ce, void *vaddr)
> >   {
> >   	struct intel_engine_cs *engine = guc_virtual_get_sibling(ce->engine, 0);
> > +	int ret = __guc_context_pin(ce, engine, vaddr);
> > +	intel_engine_mask_t tmp, mask = ce->engine->mask;
> > +
> > +	if (likely(!ret))
> > +		for_each_engine_masked(engine, ce->engine->gt, mask, tmp)
> > +			intel_engine_pm_get(engine);
> > -	return __guc_context_pin(ce, engine, vaddr);
> > +	return ret;
> > +}
> > +
> > +static void guc_virtual_context_unpin(struct intel_context *ce)
> > +{
> > +	intel_engine_mask_t tmp, mask = ce->engine->mask;
> > +	struct intel_engine_cs *engine;
> > +	struct intel_guc *guc = ce_to_guc(ce);
> > +
> > +	GEM_BUG_ON(context_enabled(ce));
> > +	GEM_BUG_ON(intel_context_is_barrier(ce));
> > +
> > +	unpin_guc_id(guc, ce);
> > +	lrc_unpin(ce);
> > +
> > +	for_each_engine_masked(engine, ce->engine->gt, mask, tmp)
> > +		intel_engine_pm_put_async(engine);
> >   }
> >   static void guc_virtual_context_enter(struct intel_context *ce)
> > @@ -2379,7 +2409,7 @@ static const struct intel_context_ops virtual_guc_context_ops = {
> >   	.pre_pin = guc_virtual_context_pre_pin,
> >   	.pin = guc_virtual_context_pin,
> > -	.unpin = guc_context_unpin,
> > +	.unpin = guc_virtual_context_unpin,
> >   	.post_unpin = guc_context_post_unpin,
> >   	.ban = guc_context_ban,
> > diff --git a/drivers/gpu/drm/i915/intel_wakeref.h b/drivers/gpu/drm/i915/intel_wakeref.h
> > index 545c8f277c46..4f4c2e15e736 100644
> > --- a/drivers/gpu/drm/i915/intel_wakeref.h
> > +++ b/drivers/gpu/drm/i915/intel_wakeref.h
> > @@ -123,6 +123,12 @@ enum {
> >   	__INTEL_WAKEREF_PUT_LAST_BIT__
> >   };
> > +static inline void
> > +intel_wakeref_might_get(struct intel_wakeref *wf)
> > +{
> > +	might_lock(&wf->mutex);
> > +}
> > +
> >   /**
> >    * intel_wakeref_put_flags: Release the wakeref
> >    * @wf: the wakeref
> > @@ -170,6 +176,12 @@ intel_wakeref_put_delay(struct intel_wakeref *wf, unsigned long delay)
> >   			    FIELD_PREP(INTEL_WAKEREF_PUT_DELAY, delay));
> >   }
> > +static inline void
> > +intel_wakeref_might_put(struct intel_wakeref *wf)
> > +{
> > +	might_lock(&wf->mutex);
> > +}
> > +
> >   /**
> >    * intel_wakeref_lock: Lock the wakeref (mutex)
> >    * @wf: the wakeref
> 

  reply	other threads:[~2021-10-07 15:24 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-04 22:06 [Intel-gfx] [PATCH 00/26] Parallel submission aka multi-bb execbuf Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 01/26] drm/i915/guc: Move GuC guc_id allocation under submission state sub-struct Matthew Brost
2021-10-07  3:06   ` John Harrison
2021-10-07 15:05     ` Matthew Brost
2021-10-07 18:13       ` John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 02/26] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-10-07  3:37   ` John Harrison
2021-10-08  1:28     ` Matthew Brost
2021-10-08 18:23     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 03/26] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-10-07  3:45   ` John Harrison
2021-10-07 15:19     ` Matthew Brost [this message]
2021-10-07 18:15       ` John Harrison
2021-10-08  1:23         ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 04/26] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-10-07  3:49   ` John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 05/26] drm/i915: Add logical engine mapping Matthew Brost
2021-10-07 19:03   ` John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 06/26] drm/i915: Expose logical engine instance to user Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 07/26] drm/i915/guc: Introduce context parent-child relationship Matthew Brost
2021-10-07 19:35   ` John Harrison
2021-10-08 18:33     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 08/26] drm/i915/guc: Add multi-lrc context registration Matthew Brost
2021-10-07 19:50   ` John Harrison
2021-10-08  1:31     ` Matthew Brost
2021-10-08 17:20     ` John Harrison
2021-10-08 17:29       ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 09/26] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost
2021-10-07 20:23   ` John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 10/26] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost
2021-10-07 22:03   ` John Harrison
2021-10-08  1:21     ` Matthew Brost
2021-10-08 16:40       ` John Harrison
2021-10-13 18:03         ` Matthew Brost
2021-10-13 19:11           ` John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 11/26] drm/i915/guc: Implement parallel context pin / unpin functions Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 12/26] drm/i915/guc: Implement multi-lrc submission Matthew Brost
2021-10-05  7:55   ` kernel test robot
2021-10-05 10:37   ` kernel test robot
2021-10-08 17:20   ` John Harrison
2021-10-13 18:24     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 13/26] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 14/26] drm/i915/guc: Implement multi-lrc reset Matthew Brost
2021-10-08 17:39   ` John Harrison
2021-10-08 17:56     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 15/26] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost
2021-10-08 17:46   ` John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 16/26] drm/i915: Fix bug in user proto-context creation that leaked contexts Matthew Brost
2021-10-08 17:49   ` John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 17/26] drm/i915/guc: Connect UAPI to GuC multi-lrc interface Matthew Brost
2021-10-11 22:09   ` John Harrison
2021-10-11 22:59     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 18/26] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 19/26] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 20/26] drm/i915/guc: Implement no mid batch preemption for multi-lrc Matthew Brost
2021-10-11 23:32   ` John Harrison
2021-10-13  1:52     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 21/26] drm/i915: Multi-BB execbuf Matthew Brost
2021-10-05  8:31   ` kernel test robot
2021-10-05 17:02   ` Matthew Brost
2021-10-06 20:46   ` Matthew Brost
2021-10-12 21:22   ` John Harrison
2021-10-13  0:37     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 22/26] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost
2021-10-12 21:56   ` John Harrison
2021-10-13  0:18     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 23/26] drm/i915: Make request conflict tracking understand parallel submits Matthew Brost
2021-10-12 22:08   ` John Harrison
2021-10-13  0:32     ` Matthew Brost
2021-10-13 19:35       ` John Harrison
2021-10-13 17:51     ` Matthew Brost
2021-10-13 19:25       ` John Harrison
2021-10-04 22:06 ` [Intel-gfx] [PATCH 24/26] drm/i915: Update I915_GEM_BUSY IOCTL to understand composite fences Matthew Brost
2021-10-11 22:15   ` Daniele Ceraolo Spurio
2021-10-12  7:53   ` Tvrtko Ursulin
2021-10-12 18:31     ` Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 25/26] drm/i915: Enable multi-bb execbuf Matthew Brost
2021-10-04 22:06 ` [Intel-gfx] [PATCH 26/26] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
2021-10-04 22:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev4) Patchwork
2021-10-12 22:15   ` John Harrison
2021-10-13  0:15     ` Matthew Brost
2021-10-13 19:24       ` John Harrison
2021-10-04 22:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-04 22:26 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-10-12 22:15   ` John Harrison
2021-10-13  0:12     ` Matthew Brost
2021-10-04 22:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-05  1:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev5) Patchwork
2021-10-05  1:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-05  1:54 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-10-05  2:21 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-12 18:11 ` [Intel-gfx] [PATCH 02/26] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost

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