From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 19/26] drm/i915: Allow platforms to share power well descriptors
Date: Tue, 8 Feb 2022 13:36:49 +0200 [thread overview]
Message-ID: <20220208113656.179823-20-imre.deak@intel.com> (raw)
In-Reply-To: <20220208113656.179823-1-imre.deak@intel.com>
Some power wells - like always-on and skl+/icl+ PW_1 - with the same
name, domain list, flags, ops are used by multiple platforms, so allow
platforms to reuse the descriptors of such power wells.
This change also lets the follow up patches to simplify the DG1/RKL
power well definitions, and remove the ADL-S skip_mask special casing.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../i915/display/intel_display_power_map.c | 281 ++++++++----------
1 file changed, 122 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 08b6fff924946..1d5d60ec00135 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -38,9 +38,17 @@
{ .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
+struct i915_power_well_desc_list {
+ const struct i915_power_well_desc *list;
+ u8 count;
+};
+
+#define I915_PW_DESCRIPTORS(x) __LIST(x)
+
+
I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
-static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
+static const struct i915_power_well_desc i9xx_power_wells_always_on[] = {
{
.instances = &I915_PW_INSTANCES(
I915_PW("always-on", &i9xx_pwdoms_always_on),
@@ -50,6 +58,10 @@ static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
},
};
+static const struct i915_power_well_desc_list i9xx_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+};
+
I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
@@ -59,14 +71,8 @@ I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc i830_power_wells[] = {
+static const struct i915_power_well_desc i830_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("pipes", &i830_pwdoms_pipes),
),
@@ -74,6 +80,11 @@ static const struct i915_power_well_desc i830_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list i830_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(i830_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
@@ -92,14 +103,8 @@ I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc hsw_power_wells[] = {
+static const struct i915_power_well_desc hsw_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &hsw_pwdoms_display,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
@@ -110,6 +115,11 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list hsw_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(hsw_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
@@ -127,14 +137,8 @@ I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc bdw_power_wells[] = {
+static const struct i915_power_well_desc bdw_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &bdw_pwdoms_display,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
@@ -146,6 +150,11 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list bdw_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(bdw_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
POWER_DOMAIN_DISPLAY_CORE,
POWER_DOMAIN_PIPE_A,
@@ -181,14 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc vlv_power_wells[] = {
+static const struct i915_power_well_desc vlv_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &vlv_pwdoms_display,
.vlv.idx = PUNIT_PWGT_IDX_DISP2D,
@@ -217,6 +220,11 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list vlv_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(vlv_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(chv_pwdoms_display,
POWER_DOMAIN_DISPLAY_CORE,
POWER_DOMAIN_PIPE_A,
@@ -253,14 +261,8 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc chv_power_wells[] = {
+static const struct i915_power_well_desc chv_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/*
* Pipe A power well is the new disp2d well. Pipe B and C
* power wells don't actually exist. Pipe A power well is
@@ -283,6 +285,11 @@ static const struct i915_power_well_desc chv_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list chv_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(chv_power_wells_main),
+};
+
#define SKL_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -330,14 +337,8 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
POWER_DOMAIN_PORT_DDI_IO_D,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc skl_power_wells[] = {
+static const struct i915_power_well_desc skl_power_wells_pw_1[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("PW_1", I915_PW_DOMAINS_NONE,
@@ -347,7 +348,11 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- }, {
+ },
+};
+
+static const struct i915_power_well_desc skl_power_wells_main[] = {
+ {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("MISC_IO", I915_PW_DOMAINS_NONE,
@@ -383,6 +388,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list skl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(skl_power_wells_main),
+};
+
#define BXT_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -423,24 +434,8 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc bxt_power_wells[] = {
+static const struct i915_power_well_desc bxt_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &bxt_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -469,6 +464,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list bxt_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(bxt_power_wells_main),
+};
+
#define GLK_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -529,24 +530,8 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc glk_power_wells[] = {
+static const struct i915_power_well_desc glk_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &glk_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -588,6 +573,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list glk_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(glk_power_wells_main),
+};
+
/*
* ICL PW_0/PG_0 domains (HW/DMC control):
* - PCI
@@ -682,14 +673,8 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
-static const struct i915_power_well_desc icl_power_wells[] = {
+static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("PW_1", I915_PW_DOMAINS_NONE,
@@ -699,7 +684,11 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- }, {
+ },
+};
+
+static const struct i915_power_well_desc icl_power_wells_main[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &icl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -763,6 +752,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list icl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(icl_power_wells_main),
+};
+
#define TGL_PW_5_POWER_DOMAINS \
POWER_DOMAIN_PIPE_D, \
POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
@@ -868,24 +863,8 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
POWER_DOMAIN_AUX_TBT6,
POWER_DOMAIN_TC_COLD_OFF);
-static const struct i915_power_well_desc tgl_power_wells[] = {
+static const struct i915_power_well_desc tgl_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &tgl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -971,6 +950,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list tgl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(tgl_power_wells_main),
+};
+
#define RKL_PW_4_POWER_DOMAINS \
POWER_DOMAIN_PIPE_C, \
POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
@@ -1025,24 +1010,8 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc rkl_power_wells[] = {
+static const struct i915_power_well_desc rkl_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &rkl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1085,6 +1054,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list rkl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(rkl_power_wells_main),
+};
+
/*
* DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
*/
@@ -1117,24 +1092,8 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc dg1_power_wells[] = {
+static const struct i915_power_well_desc dg1_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &dg1_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1193,6 +1152,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list dg1_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(dg1_power_wells_main),
+};
+
/*
* XE_LPD Power Domains
*
@@ -1318,24 +1283,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
-static const struct i915_power_well_desc xelpd_power_wells[] = {
+static const struct i915_power_well_desc xelpd_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &xelpd_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1421,6 +1370,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list xelpd_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpd_power_wells_main),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1439,27 +1394,35 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst,
set_bit(inst->domain_list->list[j], power_well->domains.bits);
}
-#define for_each_power_well_instance(_desc_list, _desc_count, _desc, _inst) \
+#define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \
for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \
for ((_inst) = (_desc)->instances->list; \
(_inst) - (_desc)->instances->list < (_desc)->instances->count; \
(_inst)++)
+#define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \
+ for ((_descs) = (_desc_list); \
+ (_descs) - (_desc_list) < (_desc_count); \
+ (_descs)++) \
+ for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \
+ (_desc), (_inst))
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
- const struct i915_power_well_desc *power_well_descs,
+ const struct i915_power_well_desc_list *power_well_descs,
int power_well_descs_sz, u64 skip_mask)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
u64 power_well_ids = 0;
+ const struct i915_power_well_desc_list *desc_list;
const struct i915_power_well_desc *desc;
const struct i915_power_well_instance *inst;
int power_well_count = 0;
int plt_idx = 0;
- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst)
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
if (!(BIT_ULL(inst->id) & skip_mask))
power_well_count++;
@@ -1471,7 +1434,7 @@ __set_power_wells(struct i915_power_domains *power_domains,
if (!power_domains->power_wells)
return -ENOMEM;
- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst) {
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {
struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
enum i915_power_well_id id = inst->id;
@@ -1549,7 +1512,7 @@ int intel_init_power_wells(struct i915_power_domains *power_domains)
else if (IS_I830(i915))
return set_power_wells(power_domains, i830_power_wells);
else
- return set_power_wells(power_domains, i9xx_always_on_power_well);
+ return set_power_wells(power_domains, i9xx_power_wells);
}
void intel_cleanup_power_wells(struct i915_power_domains *power_domains)
--
2.27.0
next prev parent reply other threads:[~2022-02-08 11:37 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-08 11:36 [Intel-gfx] [PATCH v2 00/26] drm/i915: Refactor the display power domain mappings Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 01/26] drm/i915: Fix the VDSC_PW2 power domain enum value Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 02/26] drm/i915: Sanitize open-coded power well enable()/disable() calls Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 03/26] drm/i915: Remove redundant state verification during TypeC AUX power well disabling Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 04/26] drm/i915: Move i915_power_well_regs struct into i915_power_well_ops Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 05/26] drm/i915: Move power well get/put/enable/disable functions to a new file Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 06/26] drm/i915: Add function to call a power well's sync_hw() hook Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 07/26] drm/i915: Add functions to get a power well's state/name/domains/mask/refcount Imre Deak
2022-02-11 14:26 ` Hogander, Jouni
2022-02-11 15:29 ` Imre Deak
2022-02-17 11:52 ` Hogander, Jouni
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 08/26] drm/i915: Move intel_display_power_well_is_enabled() to intel_display_power_well.c Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 09/26] drm/i915: Move per-platform power well hooks " Imre Deak
2022-02-11 15:47 ` Hogander, Jouni
2022-02-11 18:21 ` Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 10/26] drm/i915: Unexport the for_each_power_well() macros Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 11/26] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 12/26] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 13/26] drm/i915: Move the HSW power well flags " Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 14/26] drm/i915: Rename the power domain names to end with pipes/ports Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 15/26] drm/i915: Sanitize the power well names Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 16/26] drm/i915: Convert the power well descriptor domain mask to an array of domains Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 17/26] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 18/26] drm/i915: Simplify power well definitions by adding power well instances Imre Deak
2022-02-08 11:36 ` Imre Deak [this message]
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 20/26] drm/i915: Simplify the DG1 power well descriptors Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 21/26] drm/i915: Sanitize the ADL-S power well definition Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 22/26] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 23/26] drm/i915: Remove the aliasing of power domain enum values Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 24/26] drm/i915: Remove the ICL specific TBT power domains Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 25/26] drm/i915: Remove duplicate DDI/AUX power domain mappings Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 26/26] drm/i915: Remove the XELPD specific AUX and DDI power domains Imre Deak
2022-02-08 12:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev2) Patchwork
2022-02-08 12:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-08 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-02-17 11:59 ` [Intel-gfx] [PATCH v2 00/26] drm/i915: Refactor the display power domain mappings Hogander, Jouni
2022-02-22 15:24 ` Imre Deak
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