From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 03/26] drm/i915: Remove redundant state verification during TypeC AUX power well disabling
Date: Tue, 8 Feb 2022 13:36:33 +0200 [thread overview]
Message-ID: <20220208113656.179823-4-imre.deak@intel.com> (raw)
In-Reply-To: <20220208113656.179823-1-imre.deak@intel.com>
Commit d5ce34da31456a
("drm/i915: Add state verification for the TypeC port mode")
added a verification to the TypeC AUX power well enable()/disable()
hooks to check if the TypeC port related to this power well is properly
locked. If the disabling happens asynchronously the verification is
skipped, since in this case the port is unlocked. The detection of
asnychronous disabling doesn't work as intended though, since the power
well's reference count is always 0 when its disable() hook is called
(and since there won't be any domain reference held for this power well
either, the verification is always skipped); remove the verification
from the disable() hook for now. In the power well's enable() hook the
power well's reference will be always >0 and there won't be any
asynchronous disabling pending for it, so we can drop the async refcount
check from there.
No functional change.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.c | 32 +------------------
1 file changed, 1 insertion(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index a90866b8bf7c4..621aa890ff6f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -635,28 +635,10 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
-
-static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- int refs = hweight64(power_well->desc->domains &
- async_put_domains_mask(&dev_priv->power_domains));
-
- drm_WARN_ON(&dev_priv->drm, refs > power_well->count);
-
- return refs;
-}
-
static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well,
struct intel_digital_port *dig_port)
{
- /* Bypass the check if all references are released asynchronously */
- if (power_well_async_ref_count(dev_priv, power_well) ==
- power_well->count)
- return;
-
if (drm_WARN_ON(&dev_priv->drm, !dig_port))
return;
@@ -747,18 +729,6 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
}
}
-static void
-icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
- struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
-
- icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
-
- hsw_power_well_disable(dev_priv, power_well);
-}
-
static void
icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
@@ -781,7 +751,7 @@ icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
if (intel_phy_is_tc(dev_priv, phy))
- return icl_tc_phy_aux_power_well_disable(dev_priv, power_well);
+ return hsw_power_well_disable(dev_priv, power_well);
else if (IS_ICELAKE(dev_priv))
return icl_combo_phy_aux_power_well_disable(dev_priv,
power_well);
--
2.27.0
next prev parent reply other threads:[~2022-02-08 11:37 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-08 11:36 [Intel-gfx] [PATCH v2 00/26] drm/i915: Refactor the display power domain mappings Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 01/26] drm/i915: Fix the VDSC_PW2 power domain enum value Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 02/26] drm/i915: Sanitize open-coded power well enable()/disable() calls Imre Deak
2022-02-08 11:36 ` Imre Deak [this message]
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 04/26] drm/i915: Move i915_power_well_regs struct into i915_power_well_ops Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 05/26] drm/i915: Move power well get/put/enable/disable functions to a new file Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 06/26] drm/i915: Add function to call a power well's sync_hw() hook Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 07/26] drm/i915: Add functions to get a power well's state/name/domains/mask/refcount Imre Deak
2022-02-11 14:26 ` Hogander, Jouni
2022-02-11 15:29 ` Imre Deak
2022-02-17 11:52 ` Hogander, Jouni
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 08/26] drm/i915: Move intel_display_power_well_is_enabled() to intel_display_power_well.c Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 09/26] drm/i915: Move per-platform power well hooks " Imre Deak
2022-02-11 15:47 ` Hogander, Jouni
2022-02-11 18:21 ` Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 10/26] drm/i915: Unexport the for_each_power_well() macros Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 11/26] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 12/26] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 13/26] drm/i915: Move the HSW power well flags " Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 14/26] drm/i915: Rename the power domain names to end with pipes/ports Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 15/26] drm/i915: Sanitize the power well names Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 16/26] drm/i915: Convert the power well descriptor domain mask to an array of domains Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 17/26] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 18/26] drm/i915: Simplify power well definitions by adding power well instances Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 19/26] drm/i915: Allow platforms to share power well descriptors Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 20/26] drm/i915: Simplify the DG1 " Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 21/26] drm/i915: Sanitize the ADL-S power well definition Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 22/26] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 23/26] drm/i915: Remove the aliasing of power domain enum values Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 24/26] drm/i915: Remove the ICL specific TBT power domains Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 25/26] drm/i915: Remove duplicate DDI/AUX power domain mappings Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 26/26] drm/i915: Remove the XELPD specific AUX and DDI power domains Imre Deak
2022-02-08 12:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev2) Patchwork
2022-02-08 12:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-08 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-02-17 11:59 ` [Intel-gfx] [PATCH v2 00/26] drm/i915: Refactor the display power domain mappings Hogander, Jouni
2022-02-22 15:24 ` Imre Deak
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