From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Deak, Imre" <imre.deak@intel.com>
Cc: "Nikula, Jani" <jani.nikula@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 07/26] drm/i915: Add functions to get a power well's state/name/domains/mask/refcount
Date: Fri, 11 Feb 2022 14:26:27 +0000 [thread overview]
Message-ID: <6bed0b81eb3c6cdaf8268ca339c1c586f1718ec9.camel@intel.com> (raw)
In-Reply-To: <20220208113656.179823-8-imre.deak@intel.com>
On Tue, 2022-02-08 at 13:36 +0200, Imre Deak wrote:
> Add functions to get a power well's actual- and cached-enabled state,
> name, domain mask and refcount, as a step towards making the low-
> level
> power well internals (i915_power_well_ops/desc structs) hidden.
It's not really in scope of this patch, but still: Why this cached-
enabled state is needed on the first hand? Are we expecting seeing
hw_state as enabled while count == 0 or vice versa?
>
> No functional change.
>
> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 69 +++++++++------
> ----
> .../i915/display/intel_display_power_well.c | 31 +++++++++
> .../i915/display/intel_display_power_well.h | 7 ++
> 3 files changed, 72 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 056965248a3b2..321b271c4b674 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -191,10 +191,10 @@ bool __intel_display_power_is_enabled(struct
> drm_i915_private *dev_priv,
> is_enabled = true;
>
> for_each_power_domain_well_reverse(dev_priv, power_well,
> BIT_ULL(domain)) {
> - if (power_well->desc->always_on)
> + if (intel_power_well_is_always_on(power_well))
> continue;
>
> - if (!power_well->hw_enabled) {
> + if (!intel_power_well_is_enabled_cached(power_well)) {
> is_enabled = false;
> break;
> }
> @@ -330,7 +330,7 @@ static void hsw_wait_for_power_well_enable(struct
> drm_i915_private *dev_priv,
> if (intel_de_wait_for_set(dev_priv, regs->driver,
> HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
> drm_dbg_kms(&dev_priv->drm, "%s power well enable
> timeout\n",
> - power_well->desc->name);
> + intel_power_well_name(power_well));
>
> drm_WARN_ON(&dev_priv->drm, !timeout_expected);
>
> @@ -378,7 +378,7 @@ static void
> hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
>
> drm_dbg_kms(&dev_priv->drm,
> "%s forced on (bios:%d driver:%d kvmr:%d
> debug:%d)\n",
> - power_well->desc->name,
> + intel_power_well_name(power_well),
> !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs &
> 8));
> }
>
> @@ -967,8 +967,7 @@ void
> intel_display_power_set_target_dc_state(struct drm_i915_private
> *dev_priv,
> if (state == dev_priv->dmc.target_dc_state)
> goto unlock;
>
> - dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
> - power_well);
> + dc_off_enabled = intel_power_well_is_enabled(dev_priv,
> power_well);
> /*
> * If DC off power well is disabled, need to enable and disable
> the
> * DC off power well to effect target DC state.
> @@ -1090,17 +1089,17 @@ static void
> bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
> struct i915_power_well *power_well;
>
> power_well = lookup_power_well(dev_priv,
> BXT_DISP_PW_DPIO_CMN_A);
> - if (power_well->count > 0)
> + if (intel_power_well_refcount(power_well) > 0)
> bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
>
> power_well = lookup_power_well(dev_priv,
> VLV_DISP_PW_DPIO_CMN_BC);
> - if (power_well->count > 0)
> + if (intel_power_well_refcount(power_well) > 0)
> bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
>
> if (IS_GEMINILAKE(dev_priv)) {
> power_well = lookup_power_well(dev_priv,
> GLK_DISP_PW_DPIO_CMN_C);
> - if (power_well->count > 0)
> + if (intel_power_well_refcount(power_well) > 0)
> bxt_ddi_phy_verify_state(dev_priv,
> power_well->desc-
> >bxt.phy);
> }
> @@ -1226,7 +1225,7 @@ static bool
> i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
> static void i830_pipes_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - if (power_well->count > 0)
> + if (intel_power_well_refcount(power_well) > 0)
> i830_pipes_power_well_enable(dev_priv, power_well);
> else
> i830_pipes_power_well_disable(dev_priv, power_well);
> @@ -1499,7 +1498,7 @@ static void assert_chv_phy_status(struct
> drm_i915_private *dev_priv)
> PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 0) |
> PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 1));
>
> - if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
> + if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
> phy_status |= PHY_POWERGOOD(DPIO_PHY0);
>
> /* this assumes override is only used to enable lanes
> */
> @@ -1540,7 +1539,7 @@ static void assert_chv_phy_status(struct
> drm_i915_private *dev_priv)
> phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 1);
> }
>
> - if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
> + if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
> phy_status |= PHY_POWERGOOD(DPIO_PHY1);
>
> /* this assumes override is only used to enable lanes
> */
> @@ -3334,12 +3333,10 @@ bool
> intel_display_power_well_is_enabled(struct drm_i915_private
> *dev_priv,
> enum i915_power_well_id
> power_well_id)
> {
> struct i915_power_well *power_well;
> - bool ret;
>
> power_well = lookup_power_well(dev_priv, power_well_id);
> - ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
>
> - return ret;
> + return intel_power_well_is_enabled(dev_priv, power_well);
> }
>
> static const struct i915_power_well_desc skl_power_wells[] = {
> @@ -3909,7 +3906,7 @@ static void
> tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
> struct i915_power_well *power_well)
> {
> - if (power_well->count > 0)
> + if (intel_power_well_refcount(power_well) > 0)
> tgl_tc_cold_off_power_well_enable(i915, power_well);
> else
> tgl_tc_cold_off_power_well_disable(i915, power_well);
> @@ -3923,7 +3920,7 @@ tgl_tc_cold_off_power_well_is_enabled(struct
> drm_i915_private *dev_priv,
> * Not the correctly implementation but there is no way to just
> read it
> * from PCODE, so returning count to avoid state mismatch
> errors
> */
> - return power_well->count;
> + return intel_power_well_refcount(power_well);
> }
>
> static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
> @@ -5729,7 +5726,7 @@ static void chv_phy_control_init(struct
> drm_i915_private *dev_priv)
> * override and set the lane powerdown bits accding to the
> * current lane status.
> */
> - if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
> + if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
> u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
> unsigned int mask;
>
> @@ -5760,7 +5757,7 @@ static void chv_phy_control_init(struct
> drm_i915_private *dev_priv)
> dev_priv->chv_phy_assert[DPIO_PHY0] = true;
> }
>
> - if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
> + if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
> u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
> unsigned int mask;
>
> @@ -5796,8 +5793,8 @@ static void vlv_cmnlane_wa(struct
> drm_i915_private *dev_priv)
> lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
>
> /* If the display might be already active skip this */
> - if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
> - disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
> + if (intel_power_well_is_enabled(dev_priv, cmn) &&
> + intel_power_well_is_enabled(dev_priv, disp2d) &&
> intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
> return;
>
> @@ -5964,12 +5961,12 @@ void
> intel_power_domains_sanitize_state(struct drm_i915_private *i915)
>
> for_each_power_well_reverse(i915, power_well) {
> if (power_well->desc->always_on || power_well->count ||
> - !power_well->desc->ops->is_enabled(i915,
> power_well))
> + !intel_power_well_is_enabled(i915, power_well))
> continue;
>
> drm_dbg_kms(&i915->drm,
> "BIOS left unused %s power well enabled,
> disabling it\n",
> - power_well->desc->name);
> + intel_power_well_name(power_well));
> intel_power_well_disable(i915, power_well);
> }
>
> @@ -6108,9 +6105,9 @@ static void
> intel_power_domains_dump_info(struct drm_i915_private *i915)
> enum intel_display_power_domain domain;
>
> drm_dbg(&i915->drm, "%-25s %d\n",
> - power_well->desc->name, power_well->count);
> + intel_power_well_name(power_well),
> intel_power_well_refcount(power_well));
>
> - for_each_power_domain(domain, power_well->desc-
> >domains)
> + for_each_power_domain(domain,
> intel_power_well_domains(power_well))
> drm_dbg(&i915->drm, " %-23s %d\n",
> intel_display_power_domain_str(domain),
> power_domains-
> >domain_use_count[domain]);
> @@ -6143,23 +6140,25 @@ static void
> intel_power_domains_verify_state(struct drm_i915_private *i915)
> int domains_count;
> bool enabled;
>
> - enabled = power_well->desc->ops->is_enabled(i915,
> power_well);
> - if ((power_well->count || power_well->desc->always_on)
> !=
> + enabled = intel_power_well_is_enabled(i915,
> power_well);
> + if ((intel_power_well_refcount(power_well) ||
> + intel_power_well_is_always_on(power_well)) !=
> enabled)
> drm_err(&i915->drm,
> "power well %s state mismatch (refcount
> %d/enabled %d)",
> - power_well->desc->name,
> - power_well->count, enabled);
> + intel_power_well_name(power_well),
> + intel_power_well_refcount(power_well),
> enabled);
>
> domains_count = 0;
> - for_each_power_domain(domain, power_well->desc-
> >domains)
> + for_each_power_domain(domain,
> intel_power_well_domains(power_well))
> domains_count += power_domains-
> >domain_use_count[domain];
>
> - if (power_well->count != domains_count) {
> + if (intel_power_well_refcount(power_well) !=
> domains_count) {
> drm_err(&i915->drm,
> "power well %s refcount/domain refcount
> mismatch "
> "(refcount %d/domains refcount %d)\n",
> - power_well->desc->name, power_well-
> >count,
> + intel_power_well_name(power_well),
> + intel_power_well_refcount(power_well),
> domains_count);
> dump_domain_info = true;
> }
> @@ -6264,10 +6263,10 @@ void intel_display_power_debug(struct
> drm_i915_private *i915, struct seq_file *m
> enum intel_display_power_domain power_domain;
>
> power_well = &power_domains->power_wells[i];
> - seq_printf(m, "%-25s %d\n", power_well->desc->name,
> - power_well->count);
> + seq_printf(m, "%-25s %d\n",
> intel_power_well_name(power_well),
> + intel_power_well_refcount(power_well));
>
> - for_each_power_domain(power_domain, power_well->desc-
> >domains)
> + for_each_power_domain(power_domain,
> intel_power_well_domains(power_well))
> seq_printf(m, " %-23s %d\n",
> intel_display_power_domain_str(power
> _domain),
> power_domains-
> >domain_use_count[power_domain]);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 63b97bcc64bc3..415ad193a8e83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -47,3 +47,34 @@ void intel_power_well_put(struct drm_i915_private
> *i915,
> if (!--power_well->count)
> intel_power_well_disable(i915, power_well);
> }
> +
> +bool intel_power_well_is_enabled(struct drm_i915_private *i915,
> + struct i915_power_well *power_well)
> +{
> + return power_well->desc->ops->is_enabled(i915, power_well);
> +}
> +
> +bool intel_power_well_is_enabled_cached(struct i915_power_well
> *power_well)
> +{
> + return power_well->hw_enabled;
> +}
> +
> +bool intel_power_well_is_always_on(struct i915_power_well
> *power_well)
> +{
> + return power_well->desc->always_on;
> +}
> +
> +const char *intel_power_well_name(struct i915_power_well
> *power_well)
> +{
> + return power_well->desc->name;
> +}
> +
> +u64 intel_power_well_domains(struct i915_power_well *power_well)
> +{
> + return power_well->desc->domains;
> +}
> +
> +int intel_power_well_refcount(struct i915_power_well *power_well)
> +{
> + return power_well->count;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index ba5bbd36f7fc0..43affbdbc48c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -113,5 +113,12 @@ void intel_power_well_get(struct
> drm_i915_private *i915,
> struct i915_power_well *power_well);
> void intel_power_well_put(struct drm_i915_private *i915,
> struct i915_power_well *power_well);
> +bool intel_power_well_is_enabled(struct drm_i915_private *i915,
> + struct i915_power_well *power_well);
> +bool intel_power_well_is_enabled_cached(struct i915_power_well
> *power_well);
> +bool intel_power_well_is_always_on(struct i915_power_well
> *power_well);
> +const char *intel_power_well_name(struct i915_power_well
> *power_well);
> +u64 intel_power_well_domains(struct i915_power_well *power_well);
> +int intel_power_well_refcount(struct i915_power_well *power_well);
>
> #endif
BR,
Jouni Högander
next prev parent reply other threads:[~2022-02-11 14:26 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-08 11:36 [Intel-gfx] [PATCH v2 00/26] drm/i915: Refactor the display power domain mappings Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 01/26] drm/i915: Fix the VDSC_PW2 power domain enum value Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 02/26] drm/i915: Sanitize open-coded power well enable()/disable() calls Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 03/26] drm/i915: Remove redundant state verification during TypeC AUX power well disabling Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 04/26] drm/i915: Move i915_power_well_regs struct into i915_power_well_ops Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 05/26] drm/i915: Move power well get/put/enable/disable functions to a new file Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 06/26] drm/i915: Add function to call a power well's sync_hw() hook Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 07/26] drm/i915: Add functions to get a power well's state/name/domains/mask/refcount Imre Deak
2022-02-11 14:26 ` Hogander, Jouni [this message]
2022-02-11 15:29 ` Imre Deak
2022-02-17 11:52 ` Hogander, Jouni
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 08/26] drm/i915: Move intel_display_power_well_is_enabled() to intel_display_power_well.c Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 09/26] drm/i915: Move per-platform power well hooks " Imre Deak
2022-02-11 15:47 ` Hogander, Jouni
2022-02-11 18:21 ` Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 10/26] drm/i915: Unexport the for_each_power_well() macros Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 11/26] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 12/26] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 13/26] drm/i915: Move the HSW power well flags " Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 14/26] drm/i915: Rename the power domain names to end with pipes/ports Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 15/26] drm/i915: Sanitize the power well names Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 16/26] drm/i915: Convert the power well descriptor domain mask to an array of domains Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 17/26] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 18/26] drm/i915: Simplify power well definitions by adding power well instances Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 19/26] drm/i915: Allow platforms to share power well descriptors Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 20/26] drm/i915: Simplify the DG1 " Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 21/26] drm/i915: Sanitize the ADL-S power well definition Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 22/26] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 23/26] drm/i915: Remove the aliasing of power domain enum values Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 24/26] drm/i915: Remove the ICL specific TBT power domains Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 25/26] drm/i915: Remove duplicate DDI/AUX power domain mappings Imre Deak
2022-02-08 11:36 ` [Intel-gfx] [PATCH v2 26/26] drm/i915: Remove the XELPD specific AUX and DDI power domains Imre Deak
2022-02-08 12:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev2) Patchwork
2022-02-08 12:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-08 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-02-17 11:59 ` [Intel-gfx] [PATCH v2 00/26] drm/i915: Refactor the display power domain mappings Hogander, Jouni
2022-02-22 15:24 ` Imre Deak
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