[Intel-gfx] [RFC 00/15] Add support for HDMI2.1 FRL

[Ankit Nautiyal <ankit.k.nautiyal@intel.com>]

This set is RFC for adding support for HDMI2.1 FRL Link training.
FRL or Fixed Rate Link is defined by HDMI2.1 spec for supporting higher
bit-rate. As per HDMI2.1 specification, a new data-channel or lane is
added in FRL mode, by repurposing the TMDS clock Channel. This enables
HDMI to support 48 Gbps bandwidth (i.e. bit rate of 12 Gbps/lane for 4
lanes).

This series is a step for Native HDMI2.1 support for MTL and to begin
discussion on the Fixed Rate Link Training part. It adds new structures,
registers and functions for facilitating FRL training for HDMI2.1.
Basically it provides the support for starting the Link training for a
given bit rate and lane count.

The appropriate bit rate and lanes need to be computed in the compute
config phase for HDMI, for a given video-mode, which is not part of this
series, but can be built on the basic structures and new members added
in this series. The FRL Training will take place only when we take a
decision to go for FRL mode and set the crtc_state parameters
appropriately during compute config phase.

The first 2 patches are prep work to have helper for getting MAX
FRL rate for existing DP-to HDMI2.1 PCON and Native HDMI2.1 from an
older series: https://patchwork.freedesktop.org/series/99311/

As HDMI2.1 needs C20 PHY, there is dependency on patch series from
Mika: https://patchwork.freedesktop.org/series/109714/
Therefore Patch 3 which adds the C10/C20 registers, is taken from the
above series for completeness, and FRL bits are added on top of that.

Ankit Nautiyal (13):
  drm/edid: Add helper to get max FRL rate for an HDMI sink
  drm/i915/dp: Use the drm helpers for getting max FRL rate
  drm/i915/hdmi21/mtl: Add new data members for FRL configuration
  drm/drm_scdc_helper: Add SCDC helper funcs for HDMI2.1
  drm/i915/mtl: Add registers for FRL Link Training
  drm/i915/mtl: Add HDMI2.1 bits in PORT_BUF_CTL_1
  drm/i915/mtl: Add port_data/data width for TRANS_DDI_FUNC and
    DDI_BUF_CTL
  drm/i915/display/mtl: Add new members in crtc_state for FRL
    configuration
  drm/i915/display/mtl: Update Transcoder/DDI registers with the frl
    bits
  drm/i915/display/mtl: Reset FRL Transcoder config while disabling HDMI
  drm/i915/hdmi21/mtl: Enable Scrambling only for FRL mode
  drm/i915/hdmi21/mtl: Add support for sending uevent to user for FRL
    training failure
  drm/i915/display/mtl: Add functions for FRL trainining state machine

Mika Kahola (1):
  drm/i915/mtl: Create separate reg file for PICA registers

Vandita Kulkarni (1):
  drm/i915/hdmi21/mtl: Parse frl max link rate from vbt

 drivers/gpu/drm/display/drm_scdc_helper.c     | 196 ++++++++
 drivers/gpu/drm/drm_edid.c                    |  38 ++
 drivers/gpu/drm/i915/display/intel_bios.c     |  51 ++
 drivers/gpu/drm/i915/display/intel_bios.h     |   1 +
 .../gpu/drm/i915/display/intel_cx0_reg_defs.h | 144 ++++++
 drivers/gpu/drm/i915/display/intel_ddi.c      |  63 ++-
 .../drm/i915/display/intel_display_types.h    |  32 ++
 drivers/gpu/drm/i915/display/intel_dp.c       |  17 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 443 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.h     |   2 +
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   7 +
 drivers/gpu/drm/i915/i915_reg.h               |  33 +-
 include/drm/display/drm_scdc.h                |  23 +
 include/drm/display/drm_scdc_helper.h         |  21 +
 include/drm/drm_edid.h                        |   2 +
 15 files changed, 1052 insertions(+), 21 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h

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2.25.1