From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 01/15] drm/edid: Add helper to get max FRL rate for an HDMI sink
Date: Mon, 7 Nov 2022 12:50:31 +0530 [thread overview]
Message-ID: <20221107072045.628895-2-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20221107072045.628895-1-ankit.k.nautiyal@intel.com>
Add the helpers for getting the max FRL rate with and without DSC
for an HDMI sink.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/drm_edid.c | 38 ++++++++++++++++++++++++++++++++++++++
include/drm/drm_edid.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index b2d61c05f559..5961399c31ba 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -7182,3 +7182,41 @@ static void _drm_update_tile_info(struct drm_connector *connector,
connector->tile_group = NULL;
}
}
+
+/**
+ * drm_hdmi_sink_max_frl_rate - get the max frl rate, if supported
+ * @connector - connector with HDMI sink
+ *
+ * RETURNS:
+ * max frl rate supported by the HDMI sink, 0 if FRL not supported
+ */
+int drm_hdmi_sink_max_frl_rate(struct drm_connector *connector)
+{
+ int max_lanes = connector->display_info.hdmi.max_lanes;
+ int rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
+
+ return max_lanes * rate_per_lane;
+}
+EXPORT_SYMBOL(drm_hdmi_sink_max_frl_rate);
+
+/**
+ * drm_hdmi_sink_dsc_max_frl_rate - get the max frl rate from HDMI sink with
+ * DSC1.2 compression.
+ * @connector - connector with HDMI sink
+ *
+ * RETURNS:
+ * max frl rate supported by the HDMI sink with DSC1.2, 0 if FRL not supported
+ */
+int drm_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector)
+{
+ int max_dsc_lanes, dsc_rate_per_lane;
+
+ if (!connector->display_info.hdmi.dsc_cap.v_1p2)
+ return 0;
+
+ max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
+ dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
+
+ return max_dsc_lanes * dsc_rate_per_lane;
+}
+EXPORT_SYMBOL(drm_hdmi_sink_dsc_max_frl_rate);
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 372963600f1d..c567826eee58 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -611,5 +611,7 @@ int drm_edid_connector_update(struct drm_connector *connector,
const struct drm_edid *edid);
const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
int ext_id, int *ext_index);
+int drm_hdmi_sink_max_frl_rate(struct drm_connector *connector);
+int drm_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector);
#endif /* __DRM_EDID_H__ */
--
2.25.1
next prev parent reply other threads:[~2022-11-07 7:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-07 7:20 [Intel-gfx] [RFC 00/15] Add support for HDMI2.1 FRL Ankit Nautiyal
2022-11-07 7:20 ` Ankit Nautiyal [this message]
2022-11-07 7:20 ` [Intel-gfx] [RFC 02/15] drm/i915/dp: Use the drm helpers for getting max FRL rate Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 03/15] drm/i915/mtl: Create separate reg file for PICA registers Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 04/15] drm/i915/hdmi21/mtl: Parse frl max link rate from vbt Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 05/15] drm/i915/hdmi21/mtl: Add new data members for FRL configuration Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 06/15] drm/drm_scdc_helper: Add SCDC helper funcs for HDMI2.1 Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 07/15] drm/i915/mtl: Add registers for FRL Link Training Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 08/15] drm/i915/mtl: Add HDMI2.1 bits in PORT_BUF_CTL_1 Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 09/15] drm/i915/mtl: Add port_data/data width for TRANS_DDI_FUNC and DDI_BUF_CTL Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 10/15] drm/i915/display/mtl: Add new members in crtc_state for FRL configuration Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 11/15] drm/i915/display/mtl: Update Transcoder/DDI registers with the frl bits Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 12/15] drm/i915/display/mtl: Reset FRL Transcoder config while disabling HDMI Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 13/15] drm/i915/hdmi21/mtl: Enable Scrambling only for FRL mode Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 14/15] drm/i915/hdmi21/mtl: Add support for sending uevent to user for FRL training failure Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 15/15] drm/i915/display/mtl: Add functions for FRL trainining state machine Ankit Nautiyal
2022-11-07 8:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for HDMI2.1 FRL Patchwork
2022-11-07 8:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-11-07 8:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-07 9:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2026-02-04 23:06 ` [Intel-gfx] [RFC 00/15] " Tomasz Pakuła
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221107072045.628895-2-ankit.k.nautiyal@intel.com \
--to=ankit.k.nautiyal@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox