From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 08/15] drm/i915/mtl: Add HDMI2.1 bits in PORT_BUF_CTL_1
Date: Mon, 7 Nov 2022 12:50:38 +0530 [thread overview]
Message-ID: <20221107072045.628895-9-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20221107072045.628895-1-ankit.k.nautiyal@intel.com>
This patch adds bits related to HDMI2.1 in PORT_BUF_CTL_1 that
is needed to be programmed for D2D Interface for Ports in
IO expansion Die.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index dfe156141d73..efba0ce90229 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -66,14 +66,22 @@
[PORT_TC4] = _XELPDP_PORT_BUF_CTL1_LN0_USBC4))
#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port))
+#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
+#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
#define XELPDP_PORT_REVERSAL REG_BIT(16)
+#define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18)
+#define XELPDP_PORT_BUF_PORT_DATA_10BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)
+#define XELPDP_PORT_BUF_PORT_DATA_20BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
+#define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
+#define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7)
#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
+#define XELPDP_PORT_HDMI_FRL_SHFTR_EN REG_BIT(0)
#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 4)
#define XELPDP_LANE0_PIPE_RESET REG_BIT(31)
--
2.25.1
next prev parent reply other threads:[~2022-11-07 7:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-07 7:20 [Intel-gfx] [RFC 00/15] Add support for HDMI2.1 FRL Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 01/15] drm/edid: Add helper to get max FRL rate for an HDMI sink Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 02/15] drm/i915/dp: Use the drm helpers for getting max FRL rate Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 03/15] drm/i915/mtl: Create separate reg file for PICA registers Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 04/15] drm/i915/hdmi21/mtl: Parse frl max link rate from vbt Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 05/15] drm/i915/hdmi21/mtl: Add new data members for FRL configuration Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 06/15] drm/drm_scdc_helper: Add SCDC helper funcs for HDMI2.1 Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 07/15] drm/i915/mtl: Add registers for FRL Link Training Ankit Nautiyal
2022-11-07 7:20 ` Ankit Nautiyal [this message]
2022-11-07 7:20 ` [Intel-gfx] [RFC 09/15] drm/i915/mtl: Add port_data/data width for TRANS_DDI_FUNC and DDI_BUF_CTL Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 10/15] drm/i915/display/mtl: Add new members in crtc_state for FRL configuration Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 11/15] drm/i915/display/mtl: Update Transcoder/DDI registers with the frl bits Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 12/15] drm/i915/display/mtl: Reset FRL Transcoder config while disabling HDMI Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 13/15] drm/i915/hdmi21/mtl: Enable Scrambling only for FRL mode Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 14/15] drm/i915/hdmi21/mtl: Add support for sending uevent to user for FRL training failure Ankit Nautiyal
2022-11-07 7:20 ` [Intel-gfx] [RFC 15/15] drm/i915/display/mtl: Add functions for FRL trainining state machine Ankit Nautiyal
2022-11-07 8:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for HDMI2.1 FRL Patchwork
2022-11-07 8:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-11-07 8:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-07 9:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2026-02-04 23:06 ` [Intel-gfx] [RFC 00/15] " Tomasz Pakuła
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