[Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/

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* [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/
@ 2023-05-18  3:17 Matt Roper
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header " Matt Roper
                   ` (8 more replies)
  0 siblings, 9 replies; 21+ messages in thread
From: Matt Roper @ 2023-05-18  3:17 UTC (permalink / raw)
  To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi, Matt Roper, intel-xe

Since i915's display code will soon be shared by two DRM drivers (i915
and Xe), it makes sense for the display code itself to be responsible
for recognizing the platform it's running on rather than relying on the
making the top-level DRM driver handle this.  This also becomes more
important for all platforms MTL and beyond where we're not really
supposed to identify platform behavior by PCI device ID anymore, but
rather by the hardware IP version reported by the device through the
GMD_ID register.

This series creates a more well-defined split between display and
non-display deviceinfo/runtimeinfo and then moves the definition of the
display-specific feature flags under the display/ code.  Finally, it
switches MTL (and all future platforms), to select the display feature
flags based on the hardware's GMD_ID identification.


Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>

Matt Roper (5):
  drm/i915/display: Move display device info to header under display/
  drm/i915: Convert INTEL_INFO()->display to a pointer
  drm/i915/display: Move display runtime info to display structure
  drm/i915/display: Make display responsible for probing its own IP
  drm/i915/display: Handle GMD_ID identification in display code

 drivers/gpu/drm/i915/Makefile                 |   2 +
 drivers/gpu/drm/i915/display/intel_color.c    |  30 +-
 drivers/gpu/drm/i915/display/intel_crtc.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_cursor.c   |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_display.h  |  10 +-
 .../drm/i915/display/intel_display_device.c   | 746 ++++++++++++++++++
 .../drm/i915/display/intel_display_device.h   |  89 +++
 .../drm/i915/display/intel_display_power.c    |   6 +-
 .../drm/i915/display/intel_display_reg_defs.h |  14 +-
 drivers/gpu/drm/i915/display/intel_fb_pin.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_fbc.c      |   6 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_hti.c      |   2 +-
 .../drm/i915/display/skl_universal_plane.c    |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |   8 +-
 drivers/gpu/drm/i915/i915_driver.c            |  10 +-
 drivers/gpu/drm/i915/i915_drv.h               |  45 +-
 drivers/gpu/drm/i915/i915_pci.c               | 382 +--------
 drivers/gpu/drm/i915/i915_reg.h               |  33 -
 drivers/gpu/drm/i915/intel_device_info.c      | 121 +--
 drivers/gpu/drm/i915/intel_device_info.h      |  67 +-
 drivers/gpu/drm/i915/intel_step.c             |   8 +-
 23 files changed, 995 insertions(+), 598 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h

-- 
2.40.0


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header under display/
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
@ 2023-05-18  3:18 ` Matt Roper
  2023-05-18  5:19   ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
  2023-05-18  6:18   ` [Intel-gfx] " Andrzej Hajda
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
                   ` (7 subsequent siblings)
  8 siblings, 2 replies; 21+ messages in thread
From: Matt Roper @ 2023-05-18  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Matt Roper, intel-xe

Moving display-specific substruture definitions will help keep display
more self-contained and make it easier to re-use in other drivers (i.e.,
Xe) in the future.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/intel_display_device.h   | 60 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h      | 49 +--------------
 2 files changed, 62 insertions(+), 47 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
new file mode 100644
index 000000000000..c689d582dbf1
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_DEVICE_H__
+#define __INTEL_DISPLAY_DEVICE_H__
+
+#include <linux/types.h>
+
+#include "display/intel_display_limits.h"
+
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+	/* Keep in alphabetical order */ \
+	func(cursor_needs_physical); \
+	func(has_cdclk_crawl); \
+	func(has_cdclk_squash); \
+	func(has_ddi); \
+	func(has_dp_mst); \
+	func(has_dsb); \
+	func(has_fpga_dbg); \
+	func(has_gmch); \
+	func(has_hotplug); \
+	func(has_hti); \
+	func(has_ipc); \
+	func(has_overlay); \
+	func(has_psr); \
+	func(has_psr_hw_tracking); \
+	func(overlay_needs_physical); \
+	func(supports_tv);
+
+struct intel_display_device_info {
+	u8 abox_mask;
+
+	struct {
+		u16 size; /* in blocks */
+		u8 slice_mask;
+	} dbuf;
+
+#define DEFINE_FLAG(name) u8 name:1
+	DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
+#undef DEFINE_FLAG
+
+	/* Global register offset for the display engine */
+	u32 mmio_offset;
+
+	/* Register offsets for the various display pipes and transcoders */
+	u32 pipe_offsets[I915_MAX_TRANSCODERS];
+	u32 trans_offsets[I915_MAX_TRANSCODERS];
+	u32 cursor_offsets[I915_MAX_PIPES];
+
+	struct {
+		u32 degamma_lut_size;
+		u32 gamma_lut_size;
+		u32 degamma_lut_tests;
+		u32 gamma_lut_tests;
+	} color;
+};
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 959a4080840c..96f6bdb04b1b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -29,7 +29,7 @@
 
 #include "intel_step.h"
 
-#include "display/intel_display_limits.h"
+#include "display/intel_display_device.h"
 
 #include "gt/intel_engine_types.h"
 #include "gt/intel_context_types.h"
@@ -182,25 +182,6 @@ enum intel_ppgtt_type {
 	func(unfenced_needs_alignment); \
 	func(hws_needs_physical);
 
-#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
-	/* Keep in alphabetical order */ \
-	func(cursor_needs_physical); \
-	func(has_cdclk_crawl); \
-	func(has_cdclk_squash); \
-	func(has_ddi); \
-	func(has_dp_mst); \
-	func(has_dsb); \
-	func(has_fpga_dbg); \
-	func(has_gmch); \
-	func(has_hotplug); \
-	func(has_hti); \
-	func(has_ipc); \
-	func(has_overlay); \
-	func(has_psr); \
-	func(has_psr_hw_tracking); \
-	func(overlay_needs_physical); \
-	func(supports_tv);
-
 struct intel_ip_version {
 	u8 ver;
 	u8 rel;
@@ -278,33 +259,7 @@ struct intel_device_info {
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
 
-	struct {
-		u8 abox_mask;
-
-		struct {
-			u16 size; /* in blocks */
-			u8 slice_mask;
-		} dbuf;
-
-#define DEFINE_FLAG(name) u8 name:1
-		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
-#undef DEFINE_FLAG
-
-		/* Global register offset for the display engine */
-		u32 mmio_offset;
-
-		/* Register offsets for the various display pipes and transcoders */
-		u32 pipe_offsets[I915_MAX_TRANSCODERS];
-		u32 trans_offsets[I915_MAX_TRANSCODERS];
-		u32 cursor_offsets[I915_MAX_PIPES];
-
-		struct {
-			u32 degamma_lut_size;
-			u32 gamma_lut_size;
-			u32 degamma_lut_tests;
-			u32 gamma_lut_tests;
-		} color;
-	} display;
+	struct intel_display_device_info display;
 
 	/*
 	 * Initial runtime info. Do not access outside of i915_driver_create().
-- 
2.40.0


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [Intel-xe] [PATCH 1/5] drm/i915/display: Move display device info to header under display/
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header " Matt Roper
@ 2023-05-18  5:19   ` Lucas De Marchi
  2023-05-18  6:18   ` [Intel-gfx] " Andrzej Hajda
  1 sibling, 0 replies; 21+ messages in thread
From: Lucas De Marchi @ 2023-05-18  5:19 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, intel-xe

On Wed, May 17, 2023 at 08:18:00PM -0700, Matt Roper wrote:
>Moving display-specific substruture definitions will help keep display
>more self-contained and make it easier to re-use in other drivers (i.e.,
>Xe) in the future.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> .../drm/i915/display/intel_display_device.h   | 60 +++++++++++++++++++
> drivers/gpu/drm/i915/intel_device_info.h      | 49 +--------------
> 2 files changed, 62 insertions(+), 47 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
>new file mode 100644
>index 000000000000..c689d582dbf1
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>@@ -0,0 +1,60 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2023 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_DISPLAY_DEVICE_H__
>+#define __INTEL_DISPLAY_DEVICE_H__
>+
>+#include <linux/types.h>
>+
>+#include "display/intel_display_limits.h"
>+
>+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
>+	/* Keep in alphabetical order */ \
>+	func(cursor_needs_physical); \
>+	func(has_cdclk_crawl); \
>+	func(has_cdclk_squash); \
>+	func(has_ddi); \
>+	func(has_dp_mst); \
>+	func(has_dsb); \
>+	func(has_fpga_dbg); \
>+	func(has_gmch); \
>+	func(has_hotplug); \
>+	func(has_hti); \
>+	func(has_ipc); \
>+	func(has_overlay); \
>+	func(has_psr); \
>+	func(has_psr_hw_tracking); \
>+	func(overlay_needs_physical); \
>+	func(supports_tv);
>+
>+struct intel_display_device_info {
>+	u8 abox_mask;
>+
>+	struct {
>+		u16 size; /* in blocks */
>+		u8 slice_mask;
>+	} dbuf;
>+
>+#define DEFINE_FLAG(name) u8 name:1
>+	DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
>+#undef DEFINE_FLAG
>+
>+	/* Global register offset for the display engine */
>+	u32 mmio_offset;
>+
>+	/* Register offsets for the various display pipes and transcoders */
>+	u32 pipe_offsets[I915_MAX_TRANSCODERS];
>+	u32 trans_offsets[I915_MAX_TRANSCODERS];
>+	u32 cursor_offsets[I915_MAX_PIPES];
>+
>+	struct {
>+		u32 degamma_lut_size;
>+		u32 gamma_lut_size;
>+		u32 degamma_lut_tests;
>+		u32 gamma_lut_tests;
>+	} color;
>+};
>+
>+#endif
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index 959a4080840c..96f6bdb04b1b 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -29,7 +29,7 @@
>
> #include "intel_step.h"
>
>-#include "display/intel_display_limits.h"
>+#include "display/intel_display_device.h"
>
> #include "gt/intel_engine_types.h"
> #include "gt/intel_context_types.h"
>@@ -182,25 +182,6 @@ enum intel_ppgtt_type {
> 	func(unfenced_needs_alignment); \
> 	func(hws_needs_physical);
>
>-#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
>-	/* Keep in alphabetical order */ \
>-	func(cursor_needs_physical); \
>-	func(has_cdclk_crawl); \
>-	func(has_cdclk_squash); \
>-	func(has_ddi); \
>-	func(has_dp_mst); \
>-	func(has_dsb); \
>-	func(has_fpga_dbg); \
>-	func(has_gmch); \
>-	func(has_hotplug); \
>-	func(has_hti); \
>-	func(has_ipc); \
>-	func(has_overlay); \
>-	func(has_psr); \
>-	func(has_psr_hw_tracking); \
>-	func(overlay_needs_physical); \
>-	func(supports_tv);
>-
> struct intel_ip_version {
> 	u8 ver;
> 	u8 rel;
>@@ -278,33 +259,7 @@ struct intel_device_info {
> 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
>
>-	struct {
>-		u8 abox_mask;
>-
>-		struct {
>-			u16 size; /* in blocks */
>-			u8 slice_mask;
>-		} dbuf;
>-
>-#define DEFINE_FLAG(name) u8 name:1
>-		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
>-#undef DEFINE_FLAG
>-
>-		/* Global register offset for the display engine */
>-		u32 mmio_offset;
>-
>-		/* Register offsets for the various display pipes and transcoders */
>-		u32 pipe_offsets[I915_MAX_TRANSCODERS];
>-		u32 trans_offsets[I915_MAX_TRANSCODERS];
>-		u32 cursor_offsets[I915_MAX_PIPES];
>-
>-		struct {
>-			u32 degamma_lut_size;
>-			u32 gamma_lut_size;
>-			u32 degamma_lut_tests;
>-			u32 gamma_lut_tests;
>-		} color;
>-	} display;
>+	struct intel_display_device_info display;

nice!! this greatly reduces the header needs for xe so we can eventually
stop including the whole display world just to have the types needed
available. If we go one step further and make it an opaque pointer, then
it'd  be even better, but we'd need a mass conversion everywhere using
display. It seems to be going the right directions


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>



Lucas De Marchi

>
> 	/*
> 	 * Initial runtime info. Do not access outside of i915_driver_create().
>-- 
>2.40.0
>

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header under display/
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header " Matt Roper
  2023-05-18  5:19   ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
@ 2023-05-18  6:18   ` Andrzej Hajda
  1 sibling, 0 replies; 21+ messages in thread
From: Andrzej Hajda @ 2023-05-18  6:18 UTC (permalink / raw)
  To: Matt Roper, intel-gfx; +Cc: intel-xe

On 18.05.2023 05:18, Matt Roper wrote:
> Moving display-specific substruture definitions will help keep display
> more self-contained and make it easier to re-use in other drivers (i.e.,
> Xe) in the future.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

s/substruture/substructure/

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

> ---
>   .../drm/i915/display/intel_display_device.h   | 60 +++++++++++++++++++
>   drivers/gpu/drm/i915/intel_device_info.h      | 49 +--------------
>   2 files changed, 62 insertions(+), 47 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> new file mode 100644
> index 000000000000..c689d582dbf1
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -0,0 +1,60 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DISPLAY_DEVICE_H__
> +#define __INTEL_DISPLAY_DEVICE_H__
> +
> +#include <linux/types.h>
> +
> +#include "display/intel_display_limits.h"
> +
> +#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> +	/* Keep in alphabetical order */ \
> +	func(cursor_needs_physical); \
> +	func(has_cdclk_crawl); \
> +	func(has_cdclk_squash); \
> +	func(has_ddi); \
> +	func(has_dp_mst); \
> +	func(has_dsb); \
> +	func(has_fpga_dbg); \
> +	func(has_gmch); \
> +	func(has_hotplug); \
> +	func(has_hti); \
> +	func(has_ipc); \
> +	func(has_overlay); \
> +	func(has_psr); \
> +	func(has_psr_hw_tracking); \
> +	func(overlay_needs_physical); \
> +	func(supports_tv);
> +
> +struct intel_display_device_info {
> +	u8 abox_mask;
> +
> +	struct {
> +		u16 size; /* in blocks */
> +		u8 slice_mask;
> +	} dbuf;
> +
> +#define DEFINE_FLAG(name) u8 name:1
> +	DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
> +#undef DEFINE_FLAG
> +
> +	/* Global register offset for the display engine */
> +	u32 mmio_offset;
> +
> +	/* Register offsets for the various display pipes and transcoders */
> +	u32 pipe_offsets[I915_MAX_TRANSCODERS];
> +	u32 trans_offsets[I915_MAX_TRANSCODERS];
> +	u32 cursor_offsets[I915_MAX_PIPES];
> +
> +	struct {
> +		u32 degamma_lut_size;
> +		u32 gamma_lut_size;
> +		u32 degamma_lut_tests;
> +		u32 gamma_lut_tests;
> +	} color;
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 959a4080840c..96f6bdb04b1b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -29,7 +29,7 @@
>   
>   #include "intel_step.h"
>   
> -#include "display/intel_display_limits.h"
> +#include "display/intel_display_device.h"
>   
>   #include "gt/intel_engine_types.h"
>   #include "gt/intel_context_types.h"
> @@ -182,25 +182,6 @@ enum intel_ppgtt_type {
>   	func(unfenced_needs_alignment); \
>   	func(hws_needs_physical);
>   
> -#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> -	/* Keep in alphabetical order */ \
> -	func(cursor_needs_physical); \
> -	func(has_cdclk_crawl); \
> -	func(has_cdclk_squash); \
> -	func(has_ddi); \
> -	func(has_dp_mst); \
> -	func(has_dsb); \
> -	func(has_fpga_dbg); \
> -	func(has_gmch); \
> -	func(has_hotplug); \
> -	func(has_hti); \
> -	func(has_ipc); \
> -	func(has_overlay); \
> -	func(has_psr); \
> -	func(has_psr_hw_tracking); \
> -	func(overlay_needs_physical); \
> -	func(supports_tv);
> -
>   struct intel_ip_version {
>   	u8 ver;
>   	u8 rel;
> @@ -278,33 +259,7 @@ struct intel_device_info {
>   	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
>   #undef DEFINE_FLAG
>   
> -	struct {
> -		u8 abox_mask;
> -
> -		struct {
> -			u16 size; /* in blocks */
> -			u8 slice_mask;
> -		} dbuf;
> -
> -#define DEFINE_FLAG(name) u8 name:1
> -		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
> -#undef DEFINE_FLAG
> -
> -		/* Global register offset for the display engine */
> -		u32 mmio_offset;
> -
> -		/* Register offsets for the various display pipes and transcoders */
> -		u32 pipe_offsets[I915_MAX_TRANSCODERS];
> -		u32 trans_offsets[I915_MAX_TRANSCODERS];
> -		u32 cursor_offsets[I915_MAX_PIPES];
> -
> -		struct {
> -			u32 degamma_lut_size;
> -			u32 gamma_lut_size;
> -			u32 degamma_lut_tests;
> -			u32 gamma_lut_tests;
> -		} color;
> -	} display;
> +	struct intel_display_device_info display;
>   
>   	/*
>   	 * Initial runtime info. Do not access outside of i915_driver_create().


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header " Matt Roper
@ 2023-05-18  3:18 ` Matt Roper
  2023-05-18  5:24   ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
  2023-05-18  6:44   ` [Intel-gfx] " Andrzej Hajda
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Move display runtime info to display structure Matt Roper
                   ` (6 subsequent siblings)
  8 siblings, 2 replies; 21+ messages in thread
From: Matt Roper @ 2023-05-18  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Matt Roper, intel-xe

Rather than embeddeding the display's device info within the main device
info structure, just provide a pointer to the display-specific
structure.  This is in preparation for moving the display device info
definitions into the display code itself and for eventually allowing the
pointer to be assigned at runtime on platforms that use GMD_ID for
device identification.

In the future, this will also eventually allow the same display device
info structures to be used outside the current i915 code (e.g., from the
Xe driver).

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c    |  30 +-
 drivers/gpu/drm/i915/display/intel_cursor.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   2 +-
 .../drm/i915/display/intel_display_power.c    |   6 +-
 .../drm/i915/display/intel_display_reg_defs.h |  14 +-
 drivers/gpu/drm/i915/display/intel_fb_pin.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_hti.c      |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |   8 +-
 drivers/gpu/drm/i915/i915_drv.h               |  28 +-
 drivers/gpu/drm/i915/i915_pci.c               | 579 ++++++++++++------
 drivers/gpu/drm/i915/intel_device_info.c      |   6 +-
 drivers/gpu/drm/i915/intel_device_info.h      |   2 +-
 12 files changed, 450 insertions(+), 231 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 07f1afe1d406..ba32808f434b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)
 	if (lut_is_legacy(gamma_lut))
 		return 0;
 
-	return INTEL_INFO(i915)->display.color.gamma_lut_tests;
+	return INTEL_INFO(i915)->display->color.gamma_lut_tests;
 }
 
 static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	return INTEL_INFO(i915)->display.color.degamma_lut_tests;
+	return INTEL_INFO(i915)->display->color.degamma_lut_tests;
 }
 
 static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
@@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
 	if (lut_is_legacy(gamma_lut))
 		return LEGACY_LUT_LENGTH;
 
-	return INTEL_INFO(i915)->display.color.gamma_lut_size;
+	return INTEL_INFO(i915)->display->color.gamma_lut_size;
 }
 
 static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
-	return INTEL_INFO(i915)->display.color.degamma_lut_size;
+	return INTEL_INFO(i915)->display->color.degamma_lut_size;
 }
 
 static int check_lut_size(const struct drm_property_blob *lut, int expected)
@@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state *crtc_state)
 		struct drm_property_blob *gamma_lut;
 
 		gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
-					       INTEL_INFO(i915)->display.color.degamma_lut_size,
+					       INTEL_INFO(i915)->display->color.degamma_lut_size,
 					       false);
 		if (IS_ERR(gamma_lut))
 			return PTR_ERR(gamma_lut);
@@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
 static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+	u32 lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display->color.degamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -2980,7 +2980,7 @@ static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -3044,7 +3044,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -3228,7 +3228,7 @@ static void bdw_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->display->color.degamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -3293,7 +3293,7 @@ static struct drm_property_blob *
 icl_read_lut_multi_segment(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
@@ -3471,8 +3471,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
 
 	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 
-	gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
-	degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
+	gamma_lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
+	degamma_lut_size = INTEL_INFO(i915)->display->color.degamma_lut_size;
 	has_ctm = degamma_lut_size != 0;
 
 	/*
@@ -3497,7 +3497,7 @@ int intel_color_init(struct drm_i915_private *i915)
 	if (DISPLAY_VER(i915) != 10)
 		return 0;
 
-	blob = create_linear_lut(i915, INTEL_INFO(i915)->display.color.degamma_lut_size);
+	blob = create_linear_lut(i915, INTEL_INFO(i915)->display->color.degamma_lut_size);
 	if (IS_ERR(blob))
 		return PTR_ERR(blob);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 31bef0427377..dd2def27add9 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -36,7 +36,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
 	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	u32 base;
 
-	if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
+	if (INTEL_INFO(dev_priv)->display->cursor_needs_physical)
 		base = sg_dma_address(obj->mm.pages->sgl);
 	else
 		base = intel_plane_ggtt_offset(plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 205b3929b861..aa3a21ccd7fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -113,7 +113,7 @@ enum i9xx_plane_id {
 
 #define for_each_dbuf_slice(__dev_priv, __slice) \
 	for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
-		for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
+		for_each_if(INTEL_INFO(__dev_priv)->display->dbuf.slice_mask & BIT(__slice))
 
 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
 	for_each_dbuf_slice((__dev_priv), (__slice)) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6ed2ece89c3f..68a7ab20ff16 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1053,7 +1053,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
 			     u8 req_slices)
 {
 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
-	u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
+	u8 slice_mask = INTEL_INFO(dev_priv)->display->dbuf.slice_mask;
 	enum dbuf_slice slice;
 
 	drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
@@ -1113,7 +1113,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
 
 static void icl_mbus_init(struct drm_i915_private *dev_priv)
 {
-	unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
+	unsigned long abox_regs = INTEL_INFO(dev_priv)->display->abox_mask;
 	u32 mask, val, i;
 
 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
@@ -1568,7 +1568,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	enum intel_dram_type type = dev_priv->dram_info.type;
 	u8 num_channels = dev_priv->dram_info.num_channels;
 	const struct buddy_page_mask *table;
-	unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
+	unsigned long abox_mask = INTEL_INFO(dev_priv)->display->abox_mask;
 	int config, i;
 
 	/* BW_BUDDY registers are not used on dgpu's beyond DG1 */
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index 755c1ea8225c..e0f82f28d8b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -8,7 +8,7 @@
 
 #include "i915_reg_defs.h"
 
-#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display.mmio_offset)
+#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display->mmio_offset)
 
 #define VLV_DISPLAY_BASE		0x180000
 
@@ -36,14 +36,14 @@
  * Device info offset array based helpers for groups of registers with unevenly
  * spaced base offsets.
  */
-#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
-					      INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
+#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display->pipe_offsets[(pipe)] - \
+					      INTEL_INFO(dev_priv)->display->pipe_offsets[PIPE_A] + \
 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
-					      INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
+#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display->trans_offsets[(tran)] - \
+					      INTEL_INFO(dev_priv)->display->trans_offsets[TRANSCODER_A] + \
 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
-					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
+#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display->cursor_offsets[(pipe)] - \
+					      INTEL_INFO(dev_priv)->display->cursor_offsets[PIPE_A] + \
 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
 
 #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 1aca7552a85d..9ed11936d967 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -243,7 +243,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 	struct i915_vma *vma;
 	bool phys_cursor =
 		plane->id == PLANE_CURSOR &&
-		INTEL_INFO(dev_priv)->display.cursor_needs_physical;
+		INTEL_INFO(dev_priv)->display->cursor_needs_physical;
 
 	if (!intel_fb_uses_dpt(fb)) {
 		vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
diff --git a/drivers/gpu/drm/i915/display/intel_hti.c b/drivers/gpu/drm/i915/display/intel_hti.c
index c518efebdf77..92a48aeef860 100644
--- a/drivers/gpu/drm/i915/display/intel_hti.c
+++ b/drivers/gpu/drm/i915/display/intel_hti.c
@@ -15,7 +15,7 @@ void intel_hti_init(struct drm_i915_private *i915)
 	 * If the platform has HTI, we need to find out whether it has reserved
 	 * any display resources before we create our display outputs.
 	 */
-	if (INTEL_INFO(i915)->display.has_hti)
+	if (INTEL_INFO(i915)->display->has_hti)
 		i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
 }
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1c7e6468f3e3..4189eb3b8ff8 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -507,8 +507,8 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
 
 static int intel_dbuf_slice_size(struct drm_i915_private *i915)
 {
-	return INTEL_INFO(i915)->display.dbuf.size /
-		hweight8(INTEL_INFO(i915)->display.dbuf.slice_mask);
+	return INTEL_INFO(i915)->display->dbuf.size /
+		hweight8(INTEL_INFO(i915)->display->dbuf.slice_mask);
 }
 
 static void
@@ -527,7 +527,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask,
 	ddb->end = fls(slice_mask) * slice_size;
 
 	WARN_ON(ddb->start >= ddb->end);
-	WARN_ON(ddb->end > INTEL_INFO(i915)->display.dbuf.size);
+	WARN_ON(ddb->end > INTEL_INFO(i915)->display->dbuf.size);
 }
 
 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
@@ -2625,7 +2625,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
 			    "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
 			    old_dbuf_state->enabled_slices,
 			    new_dbuf_state->enabled_slices,
-			    INTEL_INFO(i915)->display.dbuf.slice_mask,
+			    INTEL_INFO(i915)->display->dbuf.slice_mask,
 			    str_yes_no(old_dbuf_state->joined_mbus),
 			    str_yes_no(new_dbuf_state->joined_mbus));
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14c5338c96a6..116fc4441f8b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -782,9 +782,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
 })
 
-#define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display.has_overlay)
+#define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(i915) \
-		(INTEL_INFO(i915)->display.overlay_needs_physical)
+		(INTEL_INFO(i915)->display->overlay_needs_physical)
 
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(i915)	(IS_I830(i915) || IS_I845G(i915))
@@ -806,8 +806,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  */
 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
 					 !(IS_I915G(i915) || IS_I915GM(i915)))
-#define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display.supports_tv)
-#define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display.has_hotplug)
+#define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display->supports_tv)
+#define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display->has_hotplug)
 
 #define HAS_FW_BLC(i915)	(DISPLAY_VER(i915) > 2)
 #define HAS_FBC(i915)	(RUNTIME_INFO(i915)->fbc_mask != 0)
@@ -817,18 +817,18 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_IPS(i915)	(IS_HSW_ULT(i915) || IS_BROADWELL(i915))
 
-#define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display.has_dp_mst)
+#define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display->has_dp_mst)
 #define HAS_DP20(i915)	(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
 
 #define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
 
-#define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display.has_cdclk_crawl)
-#define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display.has_cdclk_squash)
-#define HAS_DDI(i915)		 (INTEL_INFO(i915)->display.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
-#define HAS_PSR(i915)		 (INTEL_INFO(i915)->display.has_psr)
+#define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display->has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display->has_cdclk_squash)
+#define HAS_DDI(i915)		 (INTEL_INFO(i915)->display->has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display->has_fpga_dbg)
+#define HAS_PSR(i915)		 (INTEL_INFO(i915)->display->has_psr)
 #define HAS_PSR_HW_TRACKING(i915) \
-	(INTEL_INFO(i915)->display.has_psr_hw_tracking)
+	(INTEL_INFO(i915)->display->has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(i915)	 (DISPLAY_VER(i915) >= 12)
 #define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
 
@@ -839,7 +839,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_RPS(i915)	(INTEL_INFO(i915)->has_rps)
 
 #define HAS_DMC(i915)	(RUNTIME_INFO(i915)->has_dmc)
-#define HAS_DSB(i915)	(INTEL_INFO(i915)->display.has_dsb)
+#define HAS_DSB(i915)	(INTEL_INFO(i915)->display->has_dsb)
 #define HAS_DSC(__i915)		(RUNTIME_INFO(__i915)->has_dsc)
 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 
@@ -869,7 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  */
 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
 
-#define HAS_IPC(i915)		(INTEL_INFO(i915)->display.has_ipc)
+#define HAS_IPC(i915)		(INTEL_INFO(i915)->display->has_ipc)
 #define HAS_SAGV(i915)		(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
 
 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
@@ -889,7 +889,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GLOBAL_MOCS_REGISTERS(i915)	(INTEL_INFO(i915)->has_global_mocs)
 
-#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
+#define HAS_GMCH(i915) (INTEL_INFO(i915)->display->has_gmch)
 
 #define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e4a19161afce..dd874a4db604 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -47,43 +47,43 @@
 #define NO_DISPLAY .__runtime.pipe_mask = 0
 
 #define I845_PIPE_OFFSETS \
-	.display.pipe_offsets = { \
+	.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
 	}, \
-	.display.trans_offsets = { \
+	.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 	}
 
 #define I9XX_PIPE_OFFSETS \
-	.display.pipe_offsets = { \
+	.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 	}, \
-	.display.trans_offsets = { \
+	.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 	}
 
 #define IVB_PIPE_OFFSETS \
-	.display.pipe_offsets = { \
+	.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = PIPE_C_OFFSET, \
 	}, \
-	.display.trans_offsets = { \
+	.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 	}
 
 #define HSW_PIPE_OFFSETS \
-	.display.pipe_offsets = { \
+	.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = PIPE_C_OFFSET, \
 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 	}, \
-	.display.trans_offsets = { \
+	.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -91,44 +91,44 @@
 	}
 
 #define CHV_PIPE_OFFSETS \
-	.display.pipe_offsets = { \
+	.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET, \
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
 	}, \
-	.display.trans_offsets = { \
+	.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
 	}
 
 #define I845_CURSOR_OFFSETS \
-	.display.cursor_offsets = { \
+	.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 	}
 
 #define I9XX_CURSOR_OFFSETS \
-	.display.cursor_offsets = { \
+	.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = CURSOR_B_OFFSET, \
 	}
 
 #define CHV_CURSOR_OFFSETS \
-	.display.cursor_offsets = { \
+	.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = CURSOR_B_OFFSET, \
 		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
 	}
 
 #define IVB_CURSOR_OFFSETS \
-	.display.cursor_offsets = { \
+	.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
 	}
 
 #define TGL_CURSOR_OFFSETS \
-	.display.cursor_offsets = { \
+	.cursor_offsets = { \
 		[PIPE_A] = CURSOR_A_OFFSET, \
 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -136,29 +136,29 @@
 	}
 
 #define I845_COLORS \
-	.display.color = { .gamma_lut_size = 256 }
+	.color = { .gamma_lut_size = 256 }
 #define I9XX_COLORS \
-	.display.color = { .gamma_lut_size = 129, \
+	.color = { .gamma_lut_size = 129, \
 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 	}
 #define ILK_COLORS \
-	.display.color = { .gamma_lut_size = 1024 }
+	.color = { .gamma_lut_size = 1024 }
 #define IVB_COLORS \
-	.display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
+	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 #define CHV_COLORS \
-	.display.color = { \
+	.color = { \
 		.degamma_lut_size = 65, .gamma_lut_size = 257, \
 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 	}
 #define GLK_COLORS \
-	.display.color = { \
+	.color = { \
 		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
 	}
 #define ICL_COLORS \
-	.display.color = { \
+	.color = { \
 		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
@@ -205,15 +205,24 @@
 #define GEN_DEFAULT_REGIONS \
 	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
 
+#define I830_DISPLAY \
+	.has_overlay = 1, \
+	.cursor_needs_physical = 1, \
+	.overlay_needs_physical = 1, \
+	.has_gmch = 1, \
+	I9XX_PIPE_OFFSETS, \
+	I9XX_CURSOR_OFFSETS, \
+	I9XX_COLORS
+
+static const struct intel_display_device_info i830_display = {
+	I830_DISPLAY,
+};
+
 #define I830_FEATURES \
 	GEN(2), \
 	.is_mobile = 1, \
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
-	.display.has_overlay = 1, \
-	.display.cursor_needs_physical = 1, \
-	.display.overlay_needs_physical = 1, \
-	.display.has_gmch = 1, \
 	.gpu_reset_clobbers_display = true, \
 	.has_3d_pipeline = 1, \
 	.hws_needs_physical = 1, \
@@ -223,20 +232,26 @@
 	.has_coherent_ggtt = false, \
 	.dma_mask_size = 32, \
 	.max_pat_index = 3, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
 
+#define I845_DISPLAY \
+	.has_overlay = 1, \
+	.overlay_needs_physical = 1, \
+	.has_gmch = 1, \
+	I845_PIPE_OFFSETS, \
+	I845_CURSOR_OFFSETS, \
+	I845_COLORS
+
+static const struct intel_display_device_info i845_display = {
+	I845_DISPLAY,
+};
+
 #define I845_FEATURES \
 	GEN(2), \
 	.__runtime.pipe_mask = BIT(PIPE_A), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
-	.display.has_overlay = 1, \
-	.display.overlay_needs_physical = 1, \
-	.display.has_gmch = 1, \
 	.has_3d_pipeline = 1, \
 	.gpu_reset_clobbers_display = true, \
 	.hws_needs_physical = 1, \
@@ -246,9 +261,6 @@
 	.has_coherent_ggtt = false, \
 	.dma_mask_size = 32, \
 	.max_pat_index = 3, \
-	I845_PIPE_OFFSETS, \
-	I845_CURSOR_OFFSETS, \
-	I845_COLORS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
@@ -256,30 +268,81 @@
 static const struct intel_device_info i830_info = {
 	I830_FEATURES,
 	PLATFORM(INTEL_I830),
+	.display = &i830_display,
 };
 
 static const struct intel_device_info i845g_info = {
 	I845_FEATURES,
 	PLATFORM(INTEL_I845G),
+	.display = &i845_display,
+};
+
+static const struct intel_display_device_info i85x_display = {
+	I830_DISPLAY,
 };
 
 static const struct intel_device_info i85x_info = {
 	I830_FEATURES,
 	PLATFORM(INTEL_I85X),
+	.display = &i85x_display,
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
+static const struct intel_display_device_info i865g_display = {
+	I845_DISPLAY,
+};
+
 static const struct intel_device_info i865g_info = {
 	I845_FEATURES,
 	PLATFORM(INTEL_I865G),
+	.display = &i865g_display,
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
+#define GEN3_DISPLAY \
+	.has_gmch = 1, \
+	.has_overlay = 1, \
+	I9XX_PIPE_OFFSETS, \
+	I9XX_CURSOR_OFFSETS, \
+	I9XX_COLORS
+
+static const struct intel_display_device_info i915g_display = {
+	GEN3_DISPLAY,
+	.cursor_needs_physical = 1,
+	.overlay_needs_physical = 1,
+};
+
+static const struct intel_display_device_info i915gm_display = {
+	GEN3_DISPLAY,
+	.cursor_needs_physical = 1,
+	.overlay_needs_physical = 1,
+	.supports_tv = 1,
+};
+
+static const struct intel_display_device_info i945g_display = {
+	GEN3_DISPLAY,
+	.has_hotplug = 1,
+	.cursor_needs_physical = 1,
+	.overlay_needs_physical = 1,
+};
+
+static const struct intel_display_device_info i945gm_display = {
+	GEN3_DISPLAY,
+	.has_hotplug = 1,
+	.cursor_needs_physical = 1,
+	.overlay_needs_physical = 1,
+	.supports_tv = 1,
+};
+
+static const struct intel_display_device_info g33_display = {
+	GEN3_DISPLAY,
+	.has_hotplug = 1,
+};
+
 #define GEN3_FEATURES \
 	GEN(3), \
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
-	.display.has_gmch = 1, \
 	.gpu_reset_clobbers_display = true, \
 	.__runtime.platform_engine_mask = BIT(RCS0), \
 	.has_3d_pipeline = 1, \
@@ -287,9 +350,6 @@ static const struct intel_device_info i865g_info = {
 	.has_coherent_ggtt = true, \
 	.dma_mask_size = 32, \
 	.max_pat_index = 3, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
@@ -297,10 +357,8 @@ static const struct intel_device_info i865g_info = {
 static const struct intel_device_info i915g_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I915G),
+	.display = &i915g_display,
 	.has_coherent_ggtt = false,
-	.display.cursor_needs_physical = 1,
-	.display.has_overlay = 1,
-	.display.overlay_needs_physical = 1,
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
@@ -308,11 +366,8 @@ static const struct intel_device_info i915g_info = {
 static const struct intel_device_info i915gm_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I915GM),
+	.display = &i915gm_display,
 	.is_mobile = 1,
-	.display.cursor_needs_physical = 1,
-	.display.has_overlay = 1,
-	.display.overlay_needs_physical = 1,
-	.display.supports_tv = 1,
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
@@ -321,10 +376,7 @@ static const struct intel_device_info i915gm_info = {
 static const struct intel_device_info i945g_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I945G),
-	.display.has_hotplug = 1,
-	.display.cursor_needs_physical = 1,
-	.display.has_overlay = 1,
-	.display.overlay_needs_physical = 1,
+	.display = &i945g_display,
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
@@ -332,12 +384,8 @@ static const struct intel_device_info i945g_info = {
 static const struct intel_device_info i945gm_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I945GM),
+	.display = &i945gm_display,
 	.is_mobile = 1,
-	.display.has_hotplug = 1,
-	.display.cursor_needs_physical = 1,
-	.display.has_overlay = 1,
-	.display.overlay_needs_physical = 1,
-	.display.supports_tv = 1,
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
@@ -346,16 +394,14 @@ static const struct intel_device_info i945gm_info = {
 static const struct intel_device_info g33_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_G33),
-	.display.has_hotplug = 1,
-	.display.has_overlay = 1,
+	.display = &g33_display,
 	.dma_mask_size = 36,
 };
 
 static const struct intel_device_info pnv_g_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_PINEVIEW),
-	.display.has_hotplug = 1,
-	.display.has_overlay = 1,
+	.display = &g33_display,
 	.dma_mask_size = 36,
 };
 
@@ -363,17 +409,41 @@ static const struct intel_device_info pnv_m_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_PINEVIEW),
 	.is_mobile = 1,
-	.display.has_hotplug = 1,
-	.display.has_overlay = 1,
+	.display = &g33_display,
 	.dma_mask_size = 36,
 };
 
+#define GEN4_DISPLAY \
+	.has_hotplug = 1, \
+	.has_gmch = 1, \
+	I9XX_PIPE_OFFSETS, \
+	I9XX_CURSOR_OFFSETS, \
+	I9XX_COLORS
+
+static const struct intel_display_device_info i965g_display = {
+	GEN4_DISPLAY,
+	.has_overlay = 1,
+};
+
+static const struct intel_display_device_info i965gm_display = {
+	GEN4_DISPLAY,
+	.has_overlay = 1,
+	.supports_tv = 1,
+};
+
+static const struct intel_display_device_info g45_display = {
+	GEN4_DISPLAY,
+};
+
+static const struct intel_display_device_info gm45_display = {
+	GEN4_DISPLAY,
+	.supports_tv = 1,
+};
+
 #define GEN4_FEATURES \
 	GEN(4), \
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
-	.display.has_hotplug = 1, \
-	.display.has_gmch = 1, \
 	.gpu_reset_clobbers_display = true, \
 	.__runtime.platform_engine_mask = BIT(RCS0), \
 	.has_3d_pipeline = 1, \
@@ -381,9 +451,6 @@ static const struct intel_device_info pnv_m_info = {
 	.has_coherent_ggtt = true, \
 	.dma_mask_size = 36, \
 	.max_pat_index = 3, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
@@ -391,7 +458,7 @@ static const struct intel_device_info pnv_m_info = {
 static const struct intel_device_info i965g_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_I965G),
-	.display.has_overlay = 1,
+	.display = &i965g_display,
 	.hws_needs_physical = 1,
 	.has_snoop = false,
 };
@@ -399,10 +466,9 @@ static const struct intel_device_info i965g_info = {
 static const struct intel_device_info i965gm_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_I965GM),
+	.display = &i965gm_display,
 	.is_mobile = 1,
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-	.display.has_overlay = 1,
-	.display.supports_tv = 1,
 	.hws_needs_physical = 1,
 	.has_snoop = false,
 };
@@ -411,6 +477,7 @@ static const struct intel_device_info g45_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_G45),
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
+	.display = &g45_display,
 	.gpu_reset_clobbers_display = false,
 };
 
@@ -419,8 +486,8 @@ static const struct intel_device_info gm45_info = {
 	PLATFORM(INTEL_GM45),
 	.is_mobile = 1,
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-	.display.supports_tv = 1,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
+	.display = &gm45_display,
 	.gpu_reset_clobbers_display = false,
 };
 
@@ -428,7 +495,6 @@ static const struct intel_device_info gm45_info = {
 	GEN(5), \
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
-	.display.has_hotplug = 1, \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 	.has_3d_pipeline = 1, \
 	.has_snoop = true, \
@@ -437,21 +503,34 @@ static const struct intel_device_info gm45_info = {
 	.has_rc6 = 0, \
 	.dma_mask_size = 36, \
 	.max_pat_index = 3, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	ILK_COLORS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
 
+#define ILK_DISPLAY \
+	.has_hotplug = 1, \
+	I9XX_PIPE_OFFSETS, \
+	I9XX_CURSOR_OFFSETS, \
+	ILK_COLORS
+
+static const struct intel_display_device_info ilk_d_display = {
+	ILK_DISPLAY,
+};
+
 static const struct intel_device_info ilk_d_info = {
 	GEN5_FEATURES,
 	PLATFORM(INTEL_IRONLAKE),
+	.display = &ilk_d_display,
+};
+
+static const struct intel_display_device_info ilk_m_display = {
+	ILK_DISPLAY,
 };
 
 static const struct intel_device_info ilk_m_info = {
 	GEN5_FEATURES,
 	PLATFORM(INTEL_IRONLAKE),
+	.display = &ilk_m_display,
 	.is_mobile = 1,
 	.has_rps = true,
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
@@ -461,7 +540,6 @@ static const struct intel_device_info ilk_m_info = {
 	GEN(6), \
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
-	.display.has_hotplug = 1, \
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 	.has_3d_pipeline = 1, \
@@ -475,24 +553,30 @@ static const struct intel_device_info ilk_m_info = {
 	.max_pat_index = 3, \
 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 	.__runtime.ppgtt_size = 31, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	ILK_COLORS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
 
+static const struct intel_display_device_info snb_display = {
+	.has_hotplug = 1,
+	I9XX_PIPE_OFFSETS,
+	I9XX_CURSOR_OFFSETS,
+	ILK_COLORS,
+};
+
 #define SNB_D_PLATFORM \
 	GEN6_FEATURES, \
 	PLATFORM(INTEL_SANDYBRIDGE)
 
 static const struct intel_device_info snb_d_gt1_info = {
 	SNB_D_PLATFORM,
+	.display = &snb_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info snb_d_gt2_info = {
 	SNB_D_PLATFORM,
+	.display = &snb_display,
 	.gt = 2,
 };
 
@@ -504,11 +588,13 @@ static const struct intel_device_info snb_d_gt2_info = {
 
 static const struct intel_device_info snb_m_gt1_info = {
 	SNB_M_PLATFORM,
+	.display = &snb_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info snb_m_gt2_info = {
 	SNB_M_PLATFORM,
+	.display = &snb_display,
 	.gt = 2,
 };
 
@@ -516,7 +602,6 @@ static const struct intel_device_info snb_m_gt2_info = {
 	GEN(7), \
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
-	.display.has_hotplug = 1, \
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 	.has_3d_pipeline = 1, \
@@ -530,9 +615,6 @@ static const struct intel_device_info snb_m_gt2_info = {
 	.max_pat_index = 3, \
 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 	.__runtime.ppgtt_size = 31, \
-	IVB_PIPE_OFFSETS, \
-	IVB_CURSOR_OFFSETS, \
-	IVB_COLORS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
@@ -542,13 +624,22 @@ static const struct intel_device_info snb_m_gt2_info = {
 	PLATFORM(INTEL_IVYBRIDGE), \
 	.has_l3_dpf = 1
 
+static const struct intel_display_device_info ivb_display = {
+	.has_hotplug = 1,
+	IVB_PIPE_OFFSETS,
+	IVB_CURSOR_OFFSETS,
+	IVB_COLORS,
+};
+
 static const struct intel_device_info ivb_d_gt1_info = {
 	IVB_D_PLATFORM,
+	.display = &ivb_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info ivb_d_gt2_info = {
 	IVB_D_PLATFORM,
+	.display = &ivb_display,
 	.gt = 2,
 };
 
@@ -560,11 +651,13 @@ static const struct intel_device_info ivb_d_gt2_info = {
 
 static const struct intel_device_info ivb_m_gt1_info = {
 	IVB_M_PLATFORM,
+	.display = &ivb_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info ivb_m_gt2_info = {
 	IVB_M_PLATFORM,
+	.display = &ivb_display,
 	.gt = 2,
 };
 
@@ -576,18 +669,26 @@ static const struct intel_device_info ivb_q_info = {
 	.has_l3_dpf = 1,
 };
 
+static const struct intel_display_device_info vlv_display = {
+	.has_gmch = 1,
+	.has_hotplug = 1,
+	.mmio_offset = VLV_DISPLAY_BASE,
+	I9XX_PIPE_OFFSETS,
+	I9XX_CURSOR_OFFSETS,
+	I9XX_COLORS,
+};
+
 static const struct intel_device_info vlv_info = {
 	PLATFORM(INTEL_VALLEYVIEW),
 	GEN(7),
 	.is_lp = 1,
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+	.display = &vlv_display,
 	.has_runtime_pm = 1,
 	.has_rc6 = 1,
 	.has_reset_engine = true,
 	.has_rps = true,
-	.display.has_gmch = 1,
-	.display.has_hotplug = 1,
 	.dma_mask_size = 40,
 	.max_pat_index = 3,
 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
@@ -595,10 +696,6 @@ static const struct intel_device_info vlv_info = {
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
-	.display.mmio_offset = VLV_DISPLAY_BASE,
-	I9XX_PIPE_OFFSETS,
-	I9XX_CURSOR_OFFSETS,
-	I9XX_COLORS,
 	GEN_DEFAULT_PAGE_SIZES,
 	GEN_DEFAULT_REGIONS,
 	LEGACY_CACHELEVEL,
@@ -609,11 +706,7 @@ static const struct intel_device_info vlv_info = {
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
-	.display.has_ddi = 1, \
-	.display.has_fpga_dbg = 1, \
-	.display.has_dp_mst = 1, \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
-	HSW_PIPE_OFFSETS, \
 	.has_runtime_pm = 1
 
 #define HSW_PLATFORM \
@@ -621,18 +714,31 @@ static const struct intel_device_info vlv_info = {
 	PLATFORM(INTEL_HASWELL), \
 	.has_l3_dpf = 1
 
+static const struct intel_display_device_info hsw_display = {
+	.has_ddi = 1,
+	.has_dp_mst = 1,
+	.has_fpga_dbg = 1,
+	.has_hotplug = 1,
+	HSW_PIPE_OFFSETS,
+	IVB_CURSOR_OFFSETS,
+	IVB_COLORS,
+};
+
 static const struct intel_device_info hsw_gt1_info = {
 	HSW_PLATFORM,
+	.display = &hsw_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info hsw_gt2_info = {
 	HSW_PLATFORM,
+	.display = &hsw_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info hsw_gt3_info = {
 	HSW_PLATFORM,
+	.display = &hsw_display,
 	.gt = 3,
 };
 
@@ -645,22 +751,35 @@ static const struct intel_device_info hsw_gt3_info = {
 	.__runtime.ppgtt_size = 48, \
 	.has_64bit_reloc = 1
 
+static const struct intel_display_device_info bdw_display = {
+	.has_ddi = 1,
+	.has_dp_mst = 1,
+	.has_fpga_dbg = 1,
+	.has_hotplug = 1,
+	HSW_PIPE_OFFSETS,
+	IVB_CURSOR_OFFSETS,
+	IVB_COLORS,
+};
+
 #define BDW_PLATFORM \
 	GEN8_FEATURES, \
 	PLATFORM(INTEL_BROADWELL)
 
 static const struct intel_device_info bdw_gt1_info = {
 	BDW_PLATFORM,
+	.display = &bdw_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info bdw_gt2_info = {
 	BDW_PLATFORM,
+	.display = &bdw_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info bdw_rsvd_info = {
 	BDW_PLATFORM,
+	.display = &bdw_display,
 	.gt = 3,
 	/* According to the device ID those devices are GT3, they were
 	 * previously treated as not GT3, keep it like that.
@@ -669,17 +788,27 @@ static const struct intel_device_info bdw_rsvd_info = {
 
 static const struct intel_device_info bdw_gt3_info = {
 	BDW_PLATFORM,
+	.display = &bdw_display,
 	.gt = 3,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 };
 
+static const struct intel_display_device_info chv_display = {
+	.has_hotplug = 1,
+	.has_gmch = 1,
+	.mmio_offset = VLV_DISPLAY_BASE,
+	CHV_PIPE_OFFSETS,
+	CHV_CURSOR_OFFSETS,
+	CHV_COLORS,
+};
+
 static const struct intel_device_info chv_info = {
 	PLATFORM(INTEL_CHERRYVIEW),
 	GEN(8),
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
-	.display.has_hotplug = 1,
+	.display = &chv_display,
 	.is_lp = 1,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 	.has_64bit_reloc = 1,
@@ -687,7 +816,6 @@ static const struct intel_device_info chv_info = {
 	.has_rc6 = 1,
 	.has_rps = true,
 	.has_logical_ring_contexts = 1,
-	.display.has_gmch = 1,
 	.dma_mask_size = 39,
 	.max_pat_index = 3,
 	.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
@@ -695,10 +823,6 @@ static const struct intel_device_info chv_info = {
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
-	.display.mmio_offset = VLV_DISPLAY_BASE,
-	CHV_PIPE_OFFSETS,
-	CHV_CURSOR_OFFSETS,
-	CHV_COLORS,
 	GEN_DEFAULT_PAGE_SIZES,
 	GEN_DEFAULT_REGIONS,
 	LEGACY_CACHELEVEL,
@@ -714,12 +838,22 @@ static const struct intel_device_info chv_info = {
 	GEN9_DEFAULT_PAGE_SIZES, \
 	.__runtime.has_dmc = 1, \
 	.has_gt_uc = 1, \
-	.__runtime.has_hdcp = 1, \
-	.display.has_ipc = 1, \
-	.display.has_psr = 1, \
-	.display.has_psr_hw_tracking = 1, \
-	.display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
-	.display.dbuf.slice_mask = BIT(DBUF_S1)
+	.__runtime.has_hdcp = 1
+
+static const struct intel_display_device_info skl_display = {
+	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
+	.dbuf.slice_mask = BIT(DBUF_S1),
+	.has_ddi = 1,
+	.has_dp_mst = 1,
+	.has_fpga_dbg = 1,
+	.has_hotplug = 1,
+	.has_ipc = 1,
+	.has_psr = 1,
+	.has_psr_hw_tracking = 1,
+	HSW_PIPE_OFFSETS,
+	IVB_CURSOR_OFFSETS,
+	IVB_COLORS,
+};
 
 #define SKL_PLATFORM \
 	GEN9_FEATURES, \
@@ -727,11 +861,13 @@ static const struct intel_device_info chv_info = {
 
 static const struct intel_device_info skl_gt1_info = {
 	SKL_PLATFORM,
+	.display = &skl_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info skl_gt2_info = {
 	SKL_PLATFORM,
+	.display = &skl_display,
 	.gt = 2,
 };
 
@@ -743,19 +879,19 @@ static const struct intel_device_info skl_gt2_info = {
 
 static const struct intel_device_info skl_gt3_info = {
 	SKL_GT3_PLUS_PLATFORM,
+	.display = &skl_display,
 	.gt = 3,
 };
 
 static const struct intel_device_info skl_gt4_info = {
 	SKL_GT3_PLUS_PLATFORM,
+	.display = &skl_display,
 	.gt = 4,
 };
 
 #define GEN9_LP_FEATURES \
 	GEN(9), \
 	.is_lp = 1, \
-	.display.dbuf.slice_mask = BIT(DBUF_S1), \
-	.display.has_hotplug = 1, \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
@@ -763,17 +899,12 @@ static const struct intel_device_info skl_gt4_info = {
 		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 	.has_3d_pipeline = 1, \
 	.has_64bit_reloc = 1, \
-	.display.has_ddi = 1, \
-	.display.has_fpga_dbg = 1, \
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 	.__runtime.has_hdcp = 1, \
-	.display.has_psr = 1, \
-	.display.has_psr_hw_tracking = 1, \
 	.has_runtime_pm = 1, \
 	.__runtime.has_dmc = 1, \
 	.has_rc6 = 1, \
 	.has_rps = true, \
-	.display.has_dp_mst = 1, \
 	.has_logical_ring_contexts = 1, \
 	.has_gt_uc = 1, \
 	.dma_mask_size = 39, \
@@ -782,27 +913,46 @@ static const struct intel_device_info skl_gt4_info = {
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
-	.display.has_ipc = 1, \
 	.max_pat_index = 3, \
-	HSW_PIPE_OFFSETS, \
-	IVB_CURSOR_OFFSETS, \
-	IVB_COLORS, \
 	GEN9_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
 
+#define GEN9_LP_DISPLAY \
+	.dbuf.slice_mask = BIT(DBUF_S1), \
+	.has_dp_mst = 1, \
+	.has_ddi = 1, \
+	.has_fpga_dbg = 1, \
+	.has_hotplug = 1, \
+	.has_ipc = 1, \
+	.has_psr = 1, \
+	.has_psr_hw_tracking = 1, \
+	HSW_PIPE_OFFSETS, \
+	IVB_CURSOR_OFFSETS, \
+	IVB_COLORS
+
+static const struct intel_display_device_info bxt_display = {
+	GEN9_LP_DISPLAY,
+	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+};
+
 static const struct intel_device_info bxt_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
-	.display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+	.display = &bxt_display,
+};
+
+static const struct intel_display_device_info glk_display = {
+	GEN9_LP_DISPLAY,
+	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
+	GLK_COLORS,
 };
 
 static const struct intel_device_info glk_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
 	.__runtime.display.ip.ver = 10,
-	.display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
-	GLK_COLORS,
+	.display = &glk_display,
 };
 
 #define KBL_PLATFORM \
@@ -811,16 +961,19 @@ static const struct intel_device_info glk_info = {
 
 static const struct intel_device_info kbl_gt1_info = {
 	KBL_PLATFORM,
+	.display = &skl_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info kbl_gt2_info = {
 	KBL_PLATFORM,
+	.display = &skl_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info kbl_gt3_info = {
 	KBL_PLATFORM,
+	.display = &skl_display,
 	.gt = 3,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
@@ -832,16 +985,19 @@ static const struct intel_device_info kbl_gt3_info = {
 
 static const struct intel_device_info cfl_gt1_info = {
 	CFL_PLATFORM,
+	.display = &skl_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info cfl_gt2_info = {
 	CFL_PLATFORM,
+	.display = &skl_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info cfl_gt3_info = {
 	CFL_PLATFORM,
+	.display = &skl_display,
 	.gt = 3,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
@@ -853,11 +1009,13 @@ static const struct intel_device_info cfl_gt3_info = {
 
 static const struct intel_device_info cml_gt1_info = {
 	CML_PLATFORM,
+	.display = &skl_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info cml_gt2_info = {
 	CML_PLATFORM,
+	.display = &skl_display,
 	.gt = 2,
 };
 
@@ -869,39 +1027,51 @@ static const struct intel_device_info cml_gt2_info = {
 #define GEN11_FEATURES \
 	GEN9_FEATURES, \
 	GEN11_DEFAULT_PAGE_SIZES, \
-	.display.abox_mask = BIT(0), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
-	.display.pipe_offsets = { \
-		[TRANSCODER_A] = PIPE_A_OFFSET, \
-		[TRANSCODER_B] = PIPE_B_OFFSET, \
-		[TRANSCODER_C] = PIPE_C_OFFSET, \
-		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
-		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
-		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
-	}, \
-	.display.trans_offsets = { \
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
-		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
-		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
-		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
-		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
-		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
-	}, \
 	GEN(11), \
-	ICL_COLORS, \
-	.display.dbuf.size = 2048, \
-	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 	.__runtime.has_dsc = 1, \
 	.has_coherent_ggtt = false, \
 	.has_logical_ring_elsq = 1
 
+static const struct intel_display_device_info gen11_display = {
+	.abox_mask = BIT(0),
+	.dbuf.size = 2048,
+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
+	.has_ddi = 1,
+	.has_dp_mst = 1,
+	.has_fpga_dbg = 1,
+	.has_hotplug = 1,
+	.has_ipc = 1,
+	.has_psr = 1,
+	.has_psr_hw_tracking = 1,
+	.pipe_offsets = {
+		[TRANSCODER_A] = PIPE_A_OFFSET,
+		[TRANSCODER_B] = PIPE_B_OFFSET,
+		[TRANSCODER_C] = PIPE_C_OFFSET,
+		[TRANSCODER_EDP] = PIPE_EDP_OFFSET,
+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
+	},
+	.trans_offsets = {
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
+		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
+	},
+	IVB_CURSOR_OFFSETS,
+	ICL_COLORS,
+};
+
 static const struct intel_device_info icl_info = {
 	GEN11_FEATURES,
 	PLATFORM(INTEL_ICELAKE),
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+	.display = &gen11_display,
 };
 
 static const struct intel_device_info ehl_info = {
@@ -909,6 +1079,7 @@ static const struct intel_device_info ehl_info = {
 	PLATFORM(INTEL_ELKHARTLAKE),
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 	.__runtime.ppgtt_size = 36,
+	.display = &gen11_display,
 };
 
 static const struct intel_device_info jsl_info = {
@@ -916,17 +1087,34 @@ static const struct intel_device_info jsl_info = {
 	PLATFORM(INTEL_JASPERLAKE),
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 	.__runtime.ppgtt_size = 36,
+	.display = &gen11_display,
 };
 
 #define GEN12_FEATURES \
 	GEN11_FEATURES, \
 	GEN(12), \
-	.display.abox_mask = GENMASK(2, 1), \
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
-	.display.pipe_offsets = { \
+	TGL_CACHELEVEL, \
+	.has_global_mocs = 1, \
+	.has_pxp = 1, \
+	.max_pat_index = 3
+
+#define XE_D_DISPLAY \
+	.abox_mask = GENMASK(2, 1), \
+	.dbuf.size = 2048, \
+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
+	.has_ddi = 1, \
+	.has_dp_mst = 1, \
+	.has_dsb = 1, \
+	.has_fpga_dbg = 1, \
+	.has_hotplug = 1, \
+	.has_ipc = 1, \
+	.has_psr = 1, \
+	.has_psr_hw_tracking = 1, \
+	.pipe_offsets = { \
 		[TRANSCODER_A] = PIPE_A_OFFSET, \
 		[TRANSCODER_B] = PIPE_B_OFFSET, \
 		[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -934,7 +1122,7 @@ static const struct intel_device_info jsl_info = {
 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 	}, \
-	.display.trans_offsets = { \
+	.trans_offsets = { \
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -943,30 +1131,36 @@ static const struct intel_device_info jsl_info = {
 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 	}, \
 	TGL_CURSOR_OFFSETS, \
-	TGL_CACHELEVEL, \
-	.has_global_mocs = 1, \
-	.has_pxp = 1, \
-	.display.has_dsb = 1, \
-	.max_pat_index = 3
+	ICL_COLORS
+
+static const struct intel_display_device_info tgl_display = {
+	XE_D_DISPLAY,
+};
 
 static const struct intel_device_info tgl_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_TIGERLAKE),
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+	.display = &tgl_display,
+};
+
+static const struct intel_display_device_info rkl_display = {
+	XE_D_DISPLAY,
+	.abox_mask = BIT(0),
+	.has_hti = 1,
+	.has_psr_hw_tracking = 0,
 };
 
 static const struct intel_device_info rkl_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_ROCKETLAKE),
-	.display.abox_mask = BIT(0),
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 		BIT(TRANSCODER_C),
-	.display.has_hti = 1,
-	.display.has_psr_hw_tracking = 0,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
+	.display = &rkl_display,
 };
 
 #define DGFX_FEATURES \
@@ -989,43 +1183,43 @@ static const struct intel_device_info dg1_info = {
 		BIT(VCS0) | BIT(VCS2),
 	/* Wa_16011227922 */
 	.__runtime.ppgtt_size = 47,
+	.display = &tgl_display,
+};
+
+static const struct intel_display_device_info adl_s_display = {
+	XE_D_DISPLAY,
+	.has_hti = 1,
+	.has_psr_hw_tracking = 0,
 };
 
 static const struct intel_device_info adl_s_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_ALDERLAKE_S),
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
-	.display.has_hti = 1,
-	.display.has_psr_hw_tracking = 0,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.dma_mask_size = 39,
+	.display = &adl_s_display,
 };
 
 #define XE_LPD_FEATURES \
-	.display.abox_mask = GENMASK(1, 0),					\
-	.display.color = {							\
+	.abox_mask = GENMASK(1, 0),						\
+	.color = {								\
 		.degamma_lut_size = 129, .gamma_lut_size = 1024,		\
 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
-				     DRM_COLOR_LUT_EQUAL_CHANNELS,		\
+		DRM_COLOR_LUT_EQUAL_CHANNELS,					\
 	},									\
-	.display.dbuf.size = 4096,						\
-	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |	\
+	.dbuf.size = 4096,							\
+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
 		BIT(DBUF_S4),							\
-	.display.has_ddi = 1,							\
-	.__runtime.has_dmc = 1,							\
-	.display.has_dp_mst = 1,						\
-	.display.has_dsb = 1,							\
-	.__runtime.has_dsc = 1,							\
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
-	.display.has_fpga_dbg = 1,						\
-	.__runtime.has_hdcp = 1,						\
-	.display.has_hotplug = 1,						\
-	.display.has_ipc = 1,							\
-	.display.has_psr = 1,							\
-	.__runtime.display.ip.ver = 13,							\
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\
-	.display.pipe_offsets = {						\
+	.has_ddi = 1,								\
+	.has_dp_mst = 1,							\
+	.has_dsb = 1,								\
+	.has_fpga_dbg = 1,							\
+	.has_hotplug = 1,							\
+	.has_ipc = 1,								\
+	.has_psr = 1,								\
+	.pipe_offsets = {							\
 		[TRANSCODER_A] = PIPE_A_OFFSET,					\
 		[TRANSCODER_B] = PIPE_B_OFFSET,					\
 		[TRANSCODER_C] = PIPE_C_OFFSET,					\
@@ -1033,7 +1227,7 @@ static const struct intel_device_info adl_s_info = {
 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
 	},									\
-	.display.trans_offsets = {						\
+	.trans_offsets = {						\
 		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
 		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
 		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
@@ -1043,18 +1237,31 @@ static const struct intel_device_info adl_s_info = {
 	},									\
 	TGL_CURSOR_OFFSETS
 
+#define XE_LPD_RUNTIME \
+	.__runtime.has_dmc = 1,							\
+	.__runtime.has_dsc = 1,							\
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
+	.__runtime.has_hdcp = 1,						\
+	.__runtime.display.ip.ver = 13,							\
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
+
+static const struct intel_display_device_info xe_lpd_display = {
+	XE_LPD_FEATURES,
+	.has_cdclk_crawl = 1,
+	.has_psr_hw_tracking = 0,
+};
+
 static const struct intel_device_info adl_p_info = {
 	GEN12_FEATURES,
-	XE_LPD_FEATURES,
+	XE_LPD_RUNTIME,
 	PLATFORM(INTEL_ALDERLAKE_P),
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
 			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
-	.display.has_cdclk_crawl = 1,
-	.display.has_psr_hw_tracking = 0,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.__runtime.ppgtt_size = 48,
+	.display = &xe_lpd_display,
 	.dma_mask_size = 39,
 };
 
@@ -1125,18 +1332,23 @@ static const struct intel_device_info xehpsdv_info = {
 	.has_guc_deprivilege = 1, \
 	.has_heci_pxp = 1, \
 	.has_media_ratio_mode = 1, \
-	.display.has_cdclk_squash = 1, \
 	.__runtime.platform_engine_mask = \
 		BIT(RCS0) | BIT(BCS0) | \
 		BIT(VECS0) | BIT(VECS1) | \
 		BIT(VCS0) | BIT(VCS2) | \
 		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
 
+static const struct intel_display_device_info xe_hpd_display = {
+	XE_LPD_FEATURES,
+	.has_cdclk_squash = 1,
+};
+
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
-	XE_LPD_FEATURES,
+	XE_LPD_RUNTIME,
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+	.display = &xe_hpd_display,
 };
 
 static const struct intel_device_info ats_m_info = {
@@ -1174,11 +1386,9 @@ static const struct intel_device_info pvc_info = {
 	PVC_CACHELEVEL,
 };
 
-#define XE_LPDP_FEATURES	\
-	XE_LPD_FEATURES,	\
+#define XE_LPDP_RUNTIME	\
+	XE_LPD_RUNTIME,	\
 	.__runtime.display.ip.ver = 14,	\
-	.display.has_cdclk_crawl = 1, \
-	.display.has_cdclk_squash = 1, \
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
 
 static const struct intel_gt_definition xelpmp_extra_gt[] = {
@@ -1191,9 +1401,15 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
 	{}
 };
 
+static const struct intel_display_device_info xe_lpdp_display = {
+	XE_LPD_FEATURES,
+	.has_cdclk_crawl = 1,
+	.has_cdclk_squash = 1,
+};
+
 static const struct intel_device_info mtl_info = {
 	XE_HP_FEATURES,
-	XE_LPDP_FEATURES,
+	XE_LPDP_RUNTIME,
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 	/*
@@ -1204,6 +1420,7 @@ static const struct intel_device_info mtl_info = {
 	.__runtime.graphics.ip.rel = 70,
 	.__runtime.media.ip.ver = 13,
 	PLATFORM(INTEL_METEORLAKE),
+	.display = &xe_lpdp_display,
 	.extra_gt_list = xelpmp_extra_gt,
 	.has_flat_ccs = 0,
 	.has_gmd_id = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 4e23be2995bf..d0bf626d0360 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -138,7 +138,7 @@ void intel_device_info_print(const struct intel_device_info *info,
 
 	drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
 
-#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
 	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
 #undef PRINT_FLAG
 
@@ -388,6 +388,8 @@ mkwrite_device_info(struct drm_i915_private *i915)
 	return (struct intel_device_info *)INTEL_INFO(i915);
 }
 
+static const struct intel_display_device_info no_display = { 0 };
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @dev_priv: the i915 device
@@ -538,7 +540,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv)) {
 		dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
 						   DRIVER_ATOMIC);
-		memset(&info->display, 0, sizeof(info->display));
+		info->display = &no_display;
 
 		runtime->cpu_transcoder_mask = 0;
 		memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 96f6bdb04b1b..f212e02e6582 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -259,7 +259,7 @@ struct intel_device_info {
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
 
-	struct intel_display_device_info display;
+	const struct intel_display_device_info *display;
 
 	/*
 	 * Initial runtime info. Do not access outside of i915_driver_create().
-- 
2.40.0


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [Intel-xe] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
@ 2023-05-18  5:24   ` Lucas De Marchi
  2023-05-18  6:44   ` [Intel-gfx] " Andrzej Hajda
  1 sibling, 0 replies; 21+ messages in thread
From: Lucas De Marchi @ 2023-05-18  5:24 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, intel-xe

On Wed, May 17, 2023 at 08:18:01PM -0700, Matt Roper wrote:
>Rather than embeddeding the display's device info within the main device
>info structure, just provide a pointer to the display-specific
>structure.  This is in preparation for moving the display device info
>definitions into the display code itself and for eventually allowing the
>pointer to be assigned at runtime on platforms that use GMD_ID for
>device identification.
>
>In the future, this will also eventually allow the same display device
>info structures to be used outside the current i915 code (e.g., from the
>Xe driver).
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

and here you did what I was thinking after reading patch 1.


Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> 

... since I couldn't go the entire patch right now to review, but I like
where this is leading

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_color.c    |  30 +-
> drivers/gpu/drm/i915/display/intel_cursor.c   |   2 +-
> drivers/gpu/drm/i915/display/intel_display.h  |   2 +-
> .../drm/i915/display/intel_display_power.c    |   6 +-
> .../drm/i915/display/intel_display_reg_defs.h |  14 +-
> drivers/gpu/drm/i915/display/intel_fb_pin.c   |   2 +-
> drivers/gpu/drm/i915/display/intel_hti.c      |   2 +-
> drivers/gpu/drm/i915/display/skl_watermark.c  |   8 +-
> drivers/gpu/drm/i915/i915_drv.h               |  28 +-
> drivers/gpu/drm/i915/i915_pci.c               | 579 ++++++++++++------
> drivers/gpu/drm/i915/intel_device_info.c      |   6 +-
> drivers/gpu/drm/i915/intel_device_info.h      |   2 +-
> 12 files changed, 450 insertions(+), 231 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>index 07f1afe1d406..ba32808f434b 100644
>--- a/drivers/gpu/drm/i915/display/intel_color.c
>+++ b/drivers/gpu/drm/i915/display/intel_color.c
>@@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)
> 	if (lut_is_legacy(gamma_lut))
> 		return 0;
>
>-	return INTEL_INFO(i915)->display.color.gamma_lut_tests;
>+	return INTEL_INFO(i915)->display->color.gamma_lut_tests;
> }
>
> static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
> {
> 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
>-	return INTEL_INFO(i915)->display.color.degamma_lut_tests;
>+	return INTEL_INFO(i915)->display->color.degamma_lut_tests;
> }
>
> static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
>@@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
> 	if (lut_is_legacy(gamma_lut))
> 		return LEGACY_LUT_LENGTH;
>
>-	return INTEL_INFO(i915)->display.color.gamma_lut_size;
>+	return INTEL_INFO(i915)->display->color.gamma_lut_size;
> }
>
> static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
> {
> 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
>-	return INTEL_INFO(i915)->display.color.degamma_lut_size;
>+	return INTEL_INFO(i915)->display->color.degamma_lut_size;
> }
>
> static int check_lut_size(const struct drm_property_blob *lut, int expected)
>@@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state *crtc_state)
> 		struct drm_property_blob *gamma_lut;
>
> 		gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
>-					       INTEL_INFO(i915)->display.color.degamma_lut_size,
>+					       INTEL_INFO(i915)->display->color.degamma_lut_size,
> 					       false);
> 		if (IS_ERR(gamma_lut))
> 			return PTR_ERR(gamma_lut);
>@@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
> static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>-	u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
>+	u32 lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
> 	enum pipe pipe = crtc->pipe;
> 	struct drm_property_blob *blob;
> 	struct drm_color_lut *lut;
>@@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
> static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
>+	int i, lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
> 	enum pipe pipe = crtc->pipe;
> 	struct drm_property_blob *blob;
> 	struct drm_color_lut *lut;
>@@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
> static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
>+	int i, lut_size = INTEL_INFO(dev_priv)->display->color.degamma_lut_size;
> 	enum pipe pipe = crtc->pipe;
> 	struct drm_property_blob *blob;
> 	struct drm_color_lut *lut;
>@@ -2980,7 +2980,7 @@ static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
> static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
> {
> 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>-	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>+	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
> 	enum pipe pipe = crtc->pipe;
> 	struct drm_property_blob *blob;
> 	struct drm_color_lut *lut;
>@@ -3044,7 +3044,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
> static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
> {
> 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>-	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>+	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
> 	enum pipe pipe = crtc->pipe;
> 	struct drm_property_blob *blob;
> 	struct drm_color_lut *lut;
>@@ -3228,7 +3228,7 @@ static void bdw_read_luts(struct intel_crtc_state *crtc_state)
> static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>-	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
>+	int i, lut_size = INTEL_INFO(dev_priv)->display->color.degamma_lut_size;
> 	enum pipe pipe = crtc->pipe;
> 	struct drm_property_blob *blob;
> 	struct drm_color_lut *lut;
>@@ -3293,7 +3293,7 @@ static struct drm_property_blob *
> icl_read_lut_multi_segment(struct intel_crtc *crtc)
> {
> 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>-	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>+	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
> 	enum pipe pipe = crtc->pipe;
> 	struct drm_property_blob *blob;
> 	struct drm_color_lut *lut;
>@@ -3471,8 +3471,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
>
> 	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
>
>-	gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
>-	degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
>+	gamma_lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
>+	degamma_lut_size = INTEL_INFO(i915)->display->color.degamma_lut_size;
> 	has_ctm = degamma_lut_size != 0;
>
> 	/*
>@@ -3497,7 +3497,7 @@ int intel_color_init(struct drm_i915_private *i915)
> 	if (DISPLAY_VER(i915) != 10)
> 		return 0;
>
>-	blob = create_linear_lut(i915, INTEL_INFO(i915)->display.color.degamma_lut_size);
>+	blob = create_linear_lut(i915, INTEL_INFO(i915)->display->color.degamma_lut_size);
> 	if (IS_ERR(blob))
> 		return PTR_ERR(blob);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
>index 31bef0427377..dd2def27add9 100644
>--- a/drivers/gpu/drm/i915/display/intel_cursor.c
>+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
>@@ -36,7 +36,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> 	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> 	u32 base;
>
>-	if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
>+	if (INTEL_INFO(dev_priv)->display->cursor_needs_physical)
> 		base = sg_dma_address(obj->mm.pages->sgl);
> 	else
> 		base = intel_plane_ggtt_offset(plane_state);
>diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>index 205b3929b861..aa3a21ccd7fe 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.h
>+++ b/drivers/gpu/drm/i915/display/intel_display.h
>@@ -113,7 +113,7 @@ enum i9xx_plane_id {
>
> #define for_each_dbuf_slice(__dev_priv, __slice) \
> 	for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
>-		for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
>+		for_each_if(INTEL_INFO(__dev_priv)->display->dbuf.slice_mask & BIT(__slice))
>
> #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
> 	for_each_dbuf_slice((__dev_priv), (__slice)) \
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 6ed2ece89c3f..68a7ab20ff16 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -1053,7 +1053,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
> 			     u8 req_slices)
> {
> 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
>-	u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
>+	u8 slice_mask = INTEL_INFO(dev_priv)->display->dbuf.slice_mask;
> 	enum dbuf_slice slice;
>
> 	drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
>@@ -1113,7 +1113,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
>
> static void icl_mbus_init(struct drm_i915_private *dev_priv)
> {
>-	unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
>+	unsigned long abox_regs = INTEL_INFO(dev_priv)->display->abox_mask;
> 	u32 mask, val, i;
>
> 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
>@@ -1568,7 +1568,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> 	enum intel_dram_type type = dev_priv->dram_info.type;
> 	u8 num_channels = dev_priv->dram_info.num_channels;
> 	const struct buddy_page_mask *table;
>-	unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
>+	unsigned long abox_mask = INTEL_INFO(dev_priv)->display->abox_mask;
> 	int config, i;
>
> 	/* BW_BUDDY registers are not used on dgpu's beyond DG1 */
>diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
>index 755c1ea8225c..e0f82f28d8b3 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
>@@ -8,7 +8,7 @@
>
> #include "i915_reg_defs.h"
>
>-#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display.mmio_offset)
>+#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display->mmio_offset)
>
> #define VLV_DISPLAY_BASE		0x180000
>
>@@ -36,14 +36,14 @@
>  * Device info offset array based helpers for groups of registers with unevenly
>  * spaced base offsets.
>  */
>-#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
>-					      INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
>+#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display->pipe_offsets[(pipe)] - \
>+					      INTEL_INFO(dev_priv)->display->pipe_offsets[PIPE_A] + \
> 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
>-#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
>-					      INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
>+#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display->trans_offsets[(tran)] - \
>+					      INTEL_INFO(dev_priv)->display->trans_offsets[TRANSCODER_A] + \
> 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
>-#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
>-					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
>+#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display->cursor_offsets[(pipe)] - \
>+					      INTEL_INFO(dev_priv)->display->cursor_offsets[PIPE_A] + \
> 					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
>
> #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */
>diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
>index 1aca7552a85d..9ed11936d967 100644
>--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
>+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
>@@ -243,7 +243,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> 	struct i915_vma *vma;
> 	bool phys_cursor =
> 		plane->id == PLANE_CURSOR &&
>-		INTEL_INFO(dev_priv)->display.cursor_needs_physical;
>+		INTEL_INFO(dev_priv)->display->cursor_needs_physical;
>
> 	if (!intel_fb_uses_dpt(fb)) {
> 		vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
>diff --git a/drivers/gpu/drm/i915/display/intel_hti.c b/drivers/gpu/drm/i915/display/intel_hti.c
>index c518efebdf77..92a48aeef860 100644
>--- a/drivers/gpu/drm/i915/display/intel_hti.c
>+++ b/drivers/gpu/drm/i915/display/intel_hti.c
>@@ -15,7 +15,7 @@ void intel_hti_init(struct drm_i915_private *i915)
> 	 * If the platform has HTI, we need to find out whether it has reserved
> 	 * any display resources before we create our display outputs.
> 	 */
>-	if (INTEL_INFO(i915)->display.has_hti)
>+	if (INTEL_INFO(i915)->display->has_hti)
> 		i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
> }
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>index 1c7e6468f3e3..4189eb3b8ff8 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -507,8 +507,8 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
>
> static int intel_dbuf_slice_size(struct drm_i915_private *i915)
> {
>-	return INTEL_INFO(i915)->display.dbuf.size /
>-		hweight8(INTEL_INFO(i915)->display.dbuf.slice_mask);
>+	return INTEL_INFO(i915)->display->dbuf.size /
>+		hweight8(INTEL_INFO(i915)->display->dbuf.slice_mask);
> }
>
> static void
>@@ -527,7 +527,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask,
> 	ddb->end = fls(slice_mask) * slice_size;
>
> 	WARN_ON(ddb->start >= ddb->end);
>-	WARN_ON(ddb->end > INTEL_INFO(i915)->display.dbuf.size);
>+	WARN_ON(ddb->end > INTEL_INFO(i915)->display->dbuf.size);
> }
>
> static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
>@@ -2625,7 +2625,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
> 			    "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
> 			    old_dbuf_state->enabled_slices,
> 			    new_dbuf_state->enabled_slices,
>-			    INTEL_INFO(i915)->display.dbuf.slice_mask,
>+			    INTEL_INFO(i915)->display->dbuf.slice_mask,
> 			    str_yes_no(old_dbuf_state->joined_mbus),
> 			    str_yes_no(new_dbuf_state->joined_mbus));
> 	}
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 14c5338c96a6..116fc4441f8b 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -782,9 +782,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> 	((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
> })
>
>-#define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display.has_overlay)
>+#define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display->has_overlay)
> #define OVERLAY_NEEDS_PHYSICAL(i915) \
>-		(INTEL_INFO(i915)->display.overlay_needs_physical)
>+		(INTEL_INFO(i915)->display->overlay_needs_physical)
>
> /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> #define HAS_BROKEN_CS_TLB(i915)	(IS_I830(i915) || IS_I845G(i915))
>@@ -806,8 +806,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  */
> #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
> 					 !(IS_I915G(i915) || IS_I915GM(i915)))
>-#define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display.supports_tv)
>-#define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display.has_hotplug)
>+#define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display->supports_tv)
>+#define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display->has_hotplug)
>
> #define HAS_FW_BLC(i915)	(DISPLAY_VER(i915) > 2)
> #define HAS_FBC(i915)	(RUNTIME_INFO(i915)->fbc_mask != 0)
>@@ -817,18 +817,18 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_IPS(i915)	(IS_HSW_ULT(i915) || IS_BROADWELL(i915))
>
>-#define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display.has_dp_mst)
>+#define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display->has_dp_mst)
> #define HAS_DP20(i915)	(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
>
> #define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
>
>-#define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display.has_cdclk_crawl)
>-#define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display.has_cdclk_squash)
>-#define HAS_DDI(i915)		 (INTEL_INFO(i915)->display.has_ddi)
>-#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
>-#define HAS_PSR(i915)		 (INTEL_INFO(i915)->display.has_psr)
>+#define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display->has_cdclk_crawl)
>+#define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display->has_cdclk_squash)
>+#define HAS_DDI(i915)		 (INTEL_INFO(i915)->display->has_ddi)
>+#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display->has_fpga_dbg)
>+#define HAS_PSR(i915)		 (INTEL_INFO(i915)->display->has_psr)
> #define HAS_PSR_HW_TRACKING(i915) \
>-	(INTEL_INFO(i915)->display.has_psr_hw_tracking)
>+	(INTEL_INFO(i915)->display->has_psr_hw_tracking)
> #define HAS_PSR2_SEL_FETCH(i915)	 (DISPLAY_VER(i915) >= 12)
> #define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
>
>@@ -839,7 +839,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_RPS(i915)	(INTEL_INFO(i915)->has_rps)
>
> #define HAS_DMC(i915)	(RUNTIME_INFO(i915)->has_dmc)
>-#define HAS_DSB(i915)	(INTEL_INFO(i915)->display.has_dsb)
>+#define HAS_DSB(i915)	(INTEL_INFO(i915)->display->has_dsb)
> #define HAS_DSC(__i915)		(RUNTIME_INFO(__i915)->has_dsc)
> #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
>
>@@ -869,7 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  */
> #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
>
>-#define HAS_IPC(i915)		(INTEL_INFO(i915)->display.has_ipc)
>+#define HAS_IPC(i915)		(INTEL_INFO(i915)->display->has_ipc)
> #define HAS_SAGV(i915)		(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
>
> #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
>@@ -889,7 +889,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GLOBAL_MOCS_REGISTERS(i915)	(INTEL_INFO(i915)->has_global_mocs)
>
>-#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
>+#define HAS_GMCH(i915) (INTEL_INFO(i915)->display->has_gmch)
>
> #define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
>
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index e4a19161afce..dd874a4db604 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -47,43 +47,43 @@
> #define NO_DISPLAY .__runtime.pipe_mask = 0
>
> #define I845_PIPE_OFFSETS \
>-	.display.pipe_offsets = { \
>+	.pipe_offsets = { \
> 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> 	}, \
>-	.display.trans_offsets = { \
>+	.trans_offsets = { \
> 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> 	}
>
> #define I9XX_PIPE_OFFSETS \
>-	.display.pipe_offsets = { \
>+	.pipe_offsets = { \
> 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> 		[TRANSCODER_B] = PIPE_B_OFFSET, \
> 	}, \
>-	.display.trans_offsets = { \
>+	.trans_offsets = { \
> 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> 	}
>
> #define IVB_PIPE_OFFSETS \
>-	.display.pipe_offsets = { \
>+	.pipe_offsets = { \
> 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> 		[TRANSCODER_B] = PIPE_B_OFFSET, \
> 		[TRANSCODER_C] = PIPE_C_OFFSET, \
> 	}, \
>-	.display.trans_offsets = { \
>+	.trans_offsets = { \
> 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> 	}
>
> #define HSW_PIPE_OFFSETS \
>-	.display.pipe_offsets = { \
>+	.pipe_offsets = { \
> 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> 		[TRANSCODER_B] = PIPE_B_OFFSET, \
> 		[TRANSCODER_C] = PIPE_C_OFFSET, \
> 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> 	}, \
>-	.display.trans_offsets = { \
>+	.trans_offsets = { \
> 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
>@@ -91,44 +91,44 @@
> 	}
>
> #define CHV_PIPE_OFFSETS \
>-	.display.pipe_offsets = { \
>+	.pipe_offsets = { \
> 		[TRANSCODER_A] = PIPE_A_OFFSET, \
> 		[TRANSCODER_B] = PIPE_B_OFFSET, \
> 		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> 	}, \
>-	.display.trans_offsets = { \
>+	.trans_offsets = { \
> 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> 		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> 	}
>
> #define I845_CURSOR_OFFSETS \
>-	.display.cursor_offsets = { \
>+	.cursor_offsets = { \
> 		[PIPE_A] = CURSOR_A_OFFSET, \
> 	}
>
> #define I9XX_CURSOR_OFFSETS \
>-	.display.cursor_offsets = { \
>+	.cursor_offsets = { \
> 		[PIPE_A] = CURSOR_A_OFFSET, \
> 		[PIPE_B] = CURSOR_B_OFFSET, \
> 	}
>
> #define CHV_CURSOR_OFFSETS \
>-	.display.cursor_offsets = { \
>+	.cursor_offsets = { \
> 		[PIPE_A] = CURSOR_A_OFFSET, \
> 		[PIPE_B] = CURSOR_B_OFFSET, \
> 		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
> 	}
>
> #define IVB_CURSOR_OFFSETS \
>-	.display.cursor_offsets = { \
>+	.cursor_offsets = { \
> 		[PIPE_A] = CURSOR_A_OFFSET, \
> 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
> 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
> 	}
>
> #define TGL_CURSOR_OFFSETS \
>-	.display.cursor_offsets = { \
>+	.cursor_offsets = { \
> 		[PIPE_A] = CURSOR_A_OFFSET, \
> 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
> 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
>@@ -136,29 +136,29 @@
> 	}
>
> #define I845_COLORS \
>-	.display.color = { .gamma_lut_size = 256 }
>+	.color = { .gamma_lut_size = 256 }
> #define I9XX_COLORS \
>-	.display.color = { .gamma_lut_size = 129, \
>+	.color = { .gamma_lut_size = 129, \
> 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> 	}
> #define ILK_COLORS \
>-	.display.color = { .gamma_lut_size = 1024 }
>+	.color = { .gamma_lut_size = 1024 }
> #define IVB_COLORS \
>-	.display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
>+	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> #define CHV_COLORS \
>-	.display.color = { \
>+	.color = { \
> 		.degamma_lut_size = 65, .gamma_lut_size = 257, \
> 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> 		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> 	}
> #define GLK_COLORS \
>-	.display.color = { \
>+	.color = { \
> 		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
> 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
> 	}
> #define ICL_COLORS \
>-	.display.color = { \
>+	.color = { \
> 		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
> 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
>@@ -205,15 +205,24 @@
> #define GEN_DEFAULT_REGIONS \
> 	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
>
>+#define I830_DISPLAY \
>+	.has_overlay = 1, \
>+	.cursor_needs_physical = 1, \
>+	.overlay_needs_physical = 1, \
>+	.has_gmch = 1, \
>+	I9XX_PIPE_OFFSETS, \
>+	I9XX_CURSOR_OFFSETS, \
>+	I9XX_COLORS
>+
>+static const struct intel_display_device_info i830_display = {
>+	I830_DISPLAY,
>+};
>+
> #define I830_FEATURES \
> 	GEN(2), \
> 	.is_mobile = 1, \
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>-	.display.has_overlay = 1, \
>-	.display.cursor_needs_physical = 1, \
>-	.display.overlay_needs_physical = 1, \
>-	.display.has_gmch = 1, \
> 	.gpu_reset_clobbers_display = true, \
> 	.has_3d_pipeline = 1, \
> 	.hws_needs_physical = 1, \
>@@ -223,20 +232,26 @@
> 	.has_coherent_ggtt = false, \
> 	.dma_mask_size = 32, \
> 	.max_pat_index = 3, \
>-	I9XX_PIPE_OFFSETS, \
>-	I9XX_CURSOR_OFFSETS, \
>-	I9XX_COLORS, \
> 	GEN_DEFAULT_PAGE_SIZES, \
> 	GEN_DEFAULT_REGIONS, \
> 	LEGACY_CACHELEVEL
>
>+#define I845_DISPLAY \
>+	.has_overlay = 1, \
>+	.overlay_needs_physical = 1, \
>+	.has_gmch = 1, \
>+	I845_PIPE_OFFSETS, \
>+	I845_CURSOR_OFFSETS, \
>+	I845_COLORS
>+
>+static const struct intel_display_device_info i845_display = {
>+	I845_DISPLAY,
>+};
>+
> #define I845_FEATURES \
> 	GEN(2), \
> 	.__runtime.pipe_mask = BIT(PIPE_A), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
>-	.display.has_overlay = 1, \
>-	.display.overlay_needs_physical = 1, \
>-	.display.has_gmch = 1, \
> 	.has_3d_pipeline = 1, \
> 	.gpu_reset_clobbers_display = true, \
> 	.hws_needs_physical = 1, \
>@@ -246,9 +261,6 @@
> 	.has_coherent_ggtt = false, \
> 	.dma_mask_size = 32, \
> 	.max_pat_index = 3, \
>-	I845_PIPE_OFFSETS, \
>-	I845_CURSOR_OFFSETS, \
>-	I845_COLORS, \
> 	GEN_DEFAULT_PAGE_SIZES, \
> 	GEN_DEFAULT_REGIONS, \
> 	LEGACY_CACHELEVEL
>@@ -256,30 +268,81 @@
> static const struct intel_device_info i830_info = {
> 	I830_FEATURES,
> 	PLATFORM(INTEL_I830),
>+	.display = &i830_display,
> };
>
> static const struct intel_device_info i845g_info = {
> 	I845_FEATURES,
> 	PLATFORM(INTEL_I845G),
>+	.display = &i845_display,
>+};
>+
>+static const struct intel_display_device_info i85x_display = {
>+	I830_DISPLAY,
> };
>
> static const struct intel_device_info i85x_info = {
> 	I830_FEATURES,
> 	PLATFORM(INTEL_I85X),
>+	.display = &i85x_display,
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> };
>
>+static const struct intel_display_device_info i865g_display = {
>+	I845_DISPLAY,
>+};
>+
> static const struct intel_device_info i865g_info = {
> 	I845_FEATURES,
> 	PLATFORM(INTEL_I865G),
>+	.display = &i865g_display,
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> };
>
>+#define GEN3_DISPLAY \
>+	.has_gmch = 1, \
>+	.has_overlay = 1, \
>+	I9XX_PIPE_OFFSETS, \
>+	I9XX_CURSOR_OFFSETS, \
>+	I9XX_COLORS
>+
>+static const struct intel_display_device_info i915g_display = {
>+	GEN3_DISPLAY,
>+	.cursor_needs_physical = 1,
>+	.overlay_needs_physical = 1,
>+};
>+
>+static const struct intel_display_device_info i915gm_display = {
>+	GEN3_DISPLAY,
>+	.cursor_needs_physical = 1,
>+	.overlay_needs_physical = 1,
>+	.supports_tv = 1,
>+};
>+
>+static const struct intel_display_device_info i945g_display = {
>+	GEN3_DISPLAY,
>+	.has_hotplug = 1,
>+	.cursor_needs_physical = 1,
>+	.overlay_needs_physical = 1,
>+};
>+
>+static const struct intel_display_device_info i945gm_display = {
>+	GEN3_DISPLAY,
>+	.has_hotplug = 1,
>+	.cursor_needs_physical = 1,
>+	.overlay_needs_physical = 1,
>+	.supports_tv = 1,
>+};
>+
>+static const struct intel_display_device_info g33_display = {
>+	GEN3_DISPLAY,
>+	.has_hotplug = 1,
>+};
>+
> #define GEN3_FEATURES \
> 	GEN(3), \
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>-	.display.has_gmch = 1, \
> 	.gpu_reset_clobbers_display = true, \
> 	.__runtime.platform_engine_mask = BIT(RCS0), \
> 	.has_3d_pipeline = 1, \
>@@ -287,9 +350,6 @@ static const struct intel_device_info i865g_info = {
> 	.has_coherent_ggtt = true, \
> 	.dma_mask_size = 32, \
> 	.max_pat_index = 3, \
>-	I9XX_PIPE_OFFSETS, \
>-	I9XX_CURSOR_OFFSETS, \
>-	I9XX_COLORS, \
> 	GEN_DEFAULT_PAGE_SIZES, \
> 	GEN_DEFAULT_REGIONS, \
> 	LEGACY_CACHELEVEL
>@@ -297,10 +357,8 @@ static const struct intel_device_info i865g_info = {
> static const struct intel_device_info i915g_info = {
> 	GEN3_FEATURES,
> 	PLATFORM(INTEL_I915G),
>+	.display = &i915g_display,
> 	.has_coherent_ggtt = false,
>-	.display.cursor_needs_physical = 1,
>-	.display.has_overlay = 1,
>-	.display.overlay_needs_physical = 1,
> 	.hws_needs_physical = 1,
> 	.unfenced_needs_alignment = 1,
> };
>@@ -308,11 +366,8 @@ static const struct intel_device_info i915g_info = {
> static const struct intel_device_info i915gm_info = {
> 	GEN3_FEATURES,
> 	PLATFORM(INTEL_I915GM),
>+	.display = &i915gm_display,
> 	.is_mobile = 1,
>-	.display.cursor_needs_physical = 1,
>-	.display.has_overlay = 1,
>-	.display.overlay_needs_physical = 1,
>-	.display.supports_tv = 1,
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> 	.hws_needs_physical = 1,
> 	.unfenced_needs_alignment = 1,
>@@ -321,10 +376,7 @@ static const struct intel_device_info i915gm_info = {
> static const struct intel_device_info i945g_info = {
> 	GEN3_FEATURES,
> 	PLATFORM(INTEL_I945G),
>-	.display.has_hotplug = 1,
>-	.display.cursor_needs_physical = 1,
>-	.display.has_overlay = 1,
>-	.display.overlay_needs_physical = 1,
>+	.display = &i945g_display,
> 	.hws_needs_physical = 1,
> 	.unfenced_needs_alignment = 1,
> };
>@@ -332,12 +384,8 @@ static const struct intel_device_info i945g_info = {
> static const struct intel_device_info i945gm_info = {
> 	GEN3_FEATURES,
> 	PLATFORM(INTEL_I945GM),
>+	.display = &i945gm_display,
> 	.is_mobile = 1,
>-	.display.has_hotplug = 1,
>-	.display.cursor_needs_physical = 1,
>-	.display.has_overlay = 1,
>-	.display.overlay_needs_physical = 1,
>-	.display.supports_tv = 1,
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> 	.hws_needs_physical = 1,
> 	.unfenced_needs_alignment = 1,
>@@ -346,16 +394,14 @@ static const struct intel_device_info i945gm_info = {
> static const struct intel_device_info g33_info = {
> 	GEN3_FEATURES,
> 	PLATFORM(INTEL_G33),
>-	.display.has_hotplug = 1,
>-	.display.has_overlay = 1,
>+	.display = &g33_display,
> 	.dma_mask_size = 36,
> };
>
> static const struct intel_device_info pnv_g_info = {
> 	GEN3_FEATURES,
> 	PLATFORM(INTEL_PINEVIEW),
>-	.display.has_hotplug = 1,
>-	.display.has_overlay = 1,
>+	.display = &g33_display,
> 	.dma_mask_size = 36,
> };
>
>@@ -363,17 +409,41 @@ static const struct intel_device_info pnv_m_info = {
> 	GEN3_FEATURES,
> 	PLATFORM(INTEL_PINEVIEW),
> 	.is_mobile = 1,
>-	.display.has_hotplug = 1,
>-	.display.has_overlay = 1,
>+	.display = &g33_display,
> 	.dma_mask_size = 36,
> };
>
>+#define GEN4_DISPLAY \
>+	.has_hotplug = 1, \
>+	.has_gmch = 1, \
>+	I9XX_PIPE_OFFSETS, \
>+	I9XX_CURSOR_OFFSETS, \
>+	I9XX_COLORS
>+
>+static const struct intel_display_device_info i965g_display = {
>+	GEN4_DISPLAY,
>+	.has_overlay = 1,
>+};
>+
>+static const struct intel_display_device_info i965gm_display = {
>+	GEN4_DISPLAY,
>+	.has_overlay = 1,
>+	.supports_tv = 1,
>+};
>+
>+static const struct intel_display_device_info g45_display = {
>+	GEN4_DISPLAY,
>+};
>+
>+static const struct intel_display_device_info gm45_display = {
>+	GEN4_DISPLAY,
>+	.supports_tv = 1,
>+};
>+
> #define GEN4_FEATURES \
> 	GEN(4), \
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>-	.display.has_hotplug = 1, \
>-	.display.has_gmch = 1, \
> 	.gpu_reset_clobbers_display = true, \
> 	.__runtime.platform_engine_mask = BIT(RCS0), \
> 	.has_3d_pipeline = 1, \
>@@ -381,9 +451,6 @@ static const struct intel_device_info pnv_m_info = {
> 	.has_coherent_ggtt = true, \
> 	.dma_mask_size = 36, \
> 	.max_pat_index = 3, \
>-	I9XX_PIPE_OFFSETS, \
>-	I9XX_CURSOR_OFFSETS, \
>-	I9XX_COLORS, \
> 	GEN_DEFAULT_PAGE_SIZES, \
> 	GEN_DEFAULT_REGIONS, \
> 	LEGACY_CACHELEVEL
>@@ -391,7 +458,7 @@ static const struct intel_device_info pnv_m_info = {
> static const struct intel_device_info i965g_info = {
> 	GEN4_FEATURES,
> 	PLATFORM(INTEL_I965G),
>-	.display.has_overlay = 1,
>+	.display = &i965g_display,
> 	.hws_needs_physical = 1,
> 	.has_snoop = false,
> };
>@@ -399,10 +466,9 @@ static const struct intel_device_info i965g_info = {
> static const struct intel_device_info i965gm_info = {
> 	GEN4_FEATURES,
> 	PLATFORM(INTEL_I965GM),
>+	.display = &i965gm_display,
> 	.is_mobile = 1,
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>-	.display.has_overlay = 1,
>-	.display.supports_tv = 1,
> 	.hws_needs_physical = 1,
> 	.has_snoop = false,
> };
>@@ -411,6 +477,7 @@ static const struct intel_device_info g45_info = {
> 	GEN4_FEATURES,
> 	PLATFORM(INTEL_G45),
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
>+	.display = &g45_display,
> 	.gpu_reset_clobbers_display = false,
> };
>
>@@ -419,8 +486,8 @@ static const struct intel_device_info gm45_info = {
> 	PLATFORM(INTEL_GM45),
> 	.is_mobile = 1,
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>-	.display.supports_tv = 1,
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
>+	.display = &gm45_display,
> 	.gpu_reset_clobbers_display = false,
> };
>
>@@ -428,7 +495,6 @@ static const struct intel_device_info gm45_info = {
> 	GEN(5), \
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>-	.display.has_hotplug = 1, \
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
> 	.has_3d_pipeline = 1, \
> 	.has_snoop = true, \
>@@ -437,21 +503,34 @@ static const struct intel_device_info gm45_info = {
> 	.has_rc6 = 0, \
> 	.dma_mask_size = 36, \
> 	.max_pat_index = 3, \
>-	I9XX_PIPE_OFFSETS, \
>-	I9XX_CURSOR_OFFSETS, \
>-	ILK_COLORS, \
> 	GEN_DEFAULT_PAGE_SIZES, \
> 	GEN_DEFAULT_REGIONS, \
> 	LEGACY_CACHELEVEL
>
>+#define ILK_DISPLAY \
>+	.has_hotplug = 1, \
>+	I9XX_PIPE_OFFSETS, \
>+	I9XX_CURSOR_OFFSETS, \
>+	ILK_COLORS
>+
>+static const struct intel_display_device_info ilk_d_display = {
>+	ILK_DISPLAY,
>+};
>+
> static const struct intel_device_info ilk_d_info = {
> 	GEN5_FEATURES,
> 	PLATFORM(INTEL_IRONLAKE),
>+	.display = &ilk_d_display,
>+};
>+
>+static const struct intel_display_device_info ilk_m_display = {
>+	ILK_DISPLAY,
> };
>
> static const struct intel_device_info ilk_m_info = {
> 	GEN5_FEATURES,
> 	PLATFORM(INTEL_IRONLAKE),
>+	.display = &ilk_m_display,
> 	.is_mobile = 1,
> 	.has_rps = true,
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>@@ -461,7 +540,6 @@ static const struct intel_device_info ilk_m_info = {
> 	GEN(6), \
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>-	.display.has_hotplug = 1, \
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> 	.has_3d_pipeline = 1, \
>@@ -475,24 +553,30 @@ static const struct intel_device_info ilk_m_info = {
> 	.max_pat_index = 3, \
> 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
> 	.__runtime.ppgtt_size = 31, \
>-	I9XX_PIPE_OFFSETS, \
>-	I9XX_CURSOR_OFFSETS, \
>-	ILK_COLORS, \
> 	GEN_DEFAULT_PAGE_SIZES, \
> 	GEN_DEFAULT_REGIONS, \
> 	LEGACY_CACHELEVEL
>
>+static const struct intel_display_device_info snb_display = {
>+	.has_hotplug = 1,
>+	I9XX_PIPE_OFFSETS,
>+	I9XX_CURSOR_OFFSETS,
>+	ILK_COLORS,
>+};
>+
> #define SNB_D_PLATFORM \
> 	GEN6_FEATURES, \
> 	PLATFORM(INTEL_SANDYBRIDGE)
>
> static const struct intel_device_info snb_d_gt1_info = {
> 	SNB_D_PLATFORM,
>+	.display = &snb_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info snb_d_gt2_info = {
> 	SNB_D_PLATFORM,
>+	.display = &snb_display,
> 	.gt = 2,
> };
>
>@@ -504,11 +588,13 @@ static const struct intel_device_info snb_d_gt2_info = {
>
> static const struct intel_device_info snb_m_gt1_info = {
> 	SNB_M_PLATFORM,
>+	.display = &snb_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info snb_m_gt2_info = {
> 	SNB_M_PLATFORM,
>+	.display = &snb_display,
> 	.gt = 2,
> };
>
>@@ -516,7 +602,6 @@ static const struct intel_device_info snb_m_gt2_info = {
> 	GEN(7), \
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
>-	.display.has_hotplug = 1, \
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> 	.has_3d_pipeline = 1, \
>@@ -530,9 +615,6 @@ static const struct intel_device_info snb_m_gt2_info = {
> 	.max_pat_index = 3, \
> 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
> 	.__runtime.ppgtt_size = 31, \
>-	IVB_PIPE_OFFSETS, \
>-	IVB_CURSOR_OFFSETS, \
>-	IVB_COLORS, \
> 	GEN_DEFAULT_PAGE_SIZES, \
> 	GEN_DEFAULT_REGIONS, \
> 	LEGACY_CACHELEVEL
>@@ -542,13 +624,22 @@ static const struct intel_device_info snb_m_gt2_info = {
> 	PLATFORM(INTEL_IVYBRIDGE), \
> 	.has_l3_dpf = 1
>
>+static const struct intel_display_device_info ivb_display = {
>+	.has_hotplug = 1,
>+	IVB_PIPE_OFFSETS,
>+	IVB_CURSOR_OFFSETS,
>+	IVB_COLORS,
>+};
>+
> static const struct intel_device_info ivb_d_gt1_info = {
> 	IVB_D_PLATFORM,
>+	.display = &ivb_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info ivb_d_gt2_info = {
> 	IVB_D_PLATFORM,
>+	.display = &ivb_display,
> 	.gt = 2,
> };
>
>@@ -560,11 +651,13 @@ static const struct intel_device_info ivb_d_gt2_info = {
>
> static const struct intel_device_info ivb_m_gt1_info = {
> 	IVB_M_PLATFORM,
>+	.display = &ivb_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info ivb_m_gt2_info = {
> 	IVB_M_PLATFORM,
>+	.display = &ivb_display,
> 	.gt = 2,
> };
>
>@@ -576,18 +669,26 @@ static const struct intel_device_info ivb_q_info = {
> 	.has_l3_dpf = 1,
> };
>
>+static const struct intel_display_device_info vlv_display = {
>+	.has_gmch = 1,
>+	.has_hotplug = 1,
>+	.mmio_offset = VLV_DISPLAY_BASE,
>+	I9XX_PIPE_OFFSETS,
>+	I9XX_CURSOR_OFFSETS,
>+	I9XX_COLORS,
>+};
>+
> static const struct intel_device_info vlv_info = {
> 	PLATFORM(INTEL_VALLEYVIEW),
> 	GEN(7),
> 	.is_lp = 1,
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
>+	.display = &vlv_display,
> 	.has_runtime_pm = 1,
> 	.has_rc6 = 1,
> 	.has_reset_engine = true,
> 	.has_rps = true,
>-	.display.has_gmch = 1,
>-	.display.has_hotplug = 1,
> 	.dma_mask_size = 40,
> 	.max_pat_index = 3,
> 	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
>@@ -595,10 +696,6 @@ static const struct intel_device_info vlv_info = {
> 	.has_snoop = true,
> 	.has_coherent_ggtt = false,
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
>-	.display.mmio_offset = VLV_DISPLAY_BASE,
>-	I9XX_PIPE_OFFSETS,
>-	I9XX_CURSOR_OFFSETS,
>-	I9XX_COLORS,
> 	GEN_DEFAULT_PAGE_SIZES,
> 	GEN_DEFAULT_REGIONS,
> 	LEGACY_CACHELEVEL,
>@@ -609,11 +706,7 @@ static const struct intel_device_info vlv_info = {
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
>-	.display.has_ddi = 1, \
>-	.display.has_fpga_dbg = 1, \
>-	.display.has_dp_mst = 1, \
> 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
>-	HSW_PIPE_OFFSETS, \
> 	.has_runtime_pm = 1
>
> #define HSW_PLATFORM \
>@@ -621,18 +714,31 @@ static const struct intel_device_info vlv_info = {
> 	PLATFORM(INTEL_HASWELL), \
> 	.has_l3_dpf = 1
>
>+static const struct intel_display_device_info hsw_display = {
>+	.has_ddi = 1,
>+	.has_dp_mst = 1,
>+	.has_fpga_dbg = 1,
>+	.has_hotplug = 1,
>+	HSW_PIPE_OFFSETS,
>+	IVB_CURSOR_OFFSETS,
>+	IVB_COLORS,
>+};
>+
> static const struct intel_device_info hsw_gt1_info = {
> 	HSW_PLATFORM,
>+	.display = &hsw_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info hsw_gt2_info = {
> 	HSW_PLATFORM,
>+	.display = &hsw_display,
> 	.gt = 2,
> };
>
> static const struct intel_device_info hsw_gt3_info = {
> 	HSW_PLATFORM,
>+	.display = &hsw_display,
> 	.gt = 3,
> };
>
>@@ -645,22 +751,35 @@ static const struct intel_device_info hsw_gt3_info = {
> 	.__runtime.ppgtt_size = 48, \
> 	.has_64bit_reloc = 1
>
>+static const struct intel_display_device_info bdw_display = {
>+	.has_ddi = 1,
>+	.has_dp_mst = 1,
>+	.has_fpga_dbg = 1,
>+	.has_hotplug = 1,
>+	HSW_PIPE_OFFSETS,
>+	IVB_CURSOR_OFFSETS,
>+	IVB_COLORS,
>+};
>+
> #define BDW_PLATFORM \
> 	GEN8_FEATURES, \
> 	PLATFORM(INTEL_BROADWELL)
>
> static const struct intel_device_info bdw_gt1_info = {
> 	BDW_PLATFORM,
>+	.display = &bdw_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info bdw_gt2_info = {
> 	BDW_PLATFORM,
>+	.display = &bdw_display,
> 	.gt = 2,
> };
>
> static const struct intel_device_info bdw_rsvd_info = {
> 	BDW_PLATFORM,
>+	.display = &bdw_display,
> 	.gt = 3,
> 	/* According to the device ID those devices are GT3, they were
> 	 * previously treated as not GT3, keep it like that.
>@@ -669,17 +788,27 @@ static const struct intel_device_info bdw_rsvd_info = {
>
> static const struct intel_device_info bdw_gt3_info = {
> 	BDW_PLATFORM,
>+	.display = &bdw_display,
> 	.gt = 3,
> 	.__runtime.platform_engine_mask =
> 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
>+static const struct intel_display_device_info chv_display = {
>+	.has_hotplug = 1,
>+	.has_gmch = 1,
>+	.mmio_offset = VLV_DISPLAY_BASE,
>+	CHV_PIPE_OFFSETS,
>+	CHV_CURSOR_OFFSETS,
>+	CHV_COLORS,
>+};
>+
> static const struct intel_device_info chv_info = {
> 	PLATFORM(INTEL_CHERRYVIEW),
> 	GEN(8),
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
>-	.display.has_hotplug = 1,
>+	.display = &chv_display,
> 	.is_lp = 1,
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> 	.has_64bit_reloc = 1,
>@@ -687,7 +816,6 @@ static const struct intel_device_info chv_info = {
> 	.has_rc6 = 1,
> 	.has_rps = true,
> 	.has_logical_ring_contexts = 1,
>-	.display.has_gmch = 1,
> 	.dma_mask_size = 39,
> 	.max_pat_index = 3,
> 	.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
>@@ -695,10 +823,6 @@ static const struct intel_device_info chv_info = {
> 	.has_reset_engine = 1,
> 	.has_snoop = true,
> 	.has_coherent_ggtt = false,
>-	.display.mmio_offset = VLV_DISPLAY_BASE,
>-	CHV_PIPE_OFFSETS,
>-	CHV_CURSOR_OFFSETS,
>-	CHV_COLORS,
> 	GEN_DEFAULT_PAGE_SIZES,
> 	GEN_DEFAULT_REGIONS,
> 	LEGACY_CACHELEVEL,
>@@ -714,12 +838,22 @@ static const struct intel_device_info chv_info = {
> 	GEN9_DEFAULT_PAGE_SIZES, \
> 	.__runtime.has_dmc = 1, \
> 	.has_gt_uc = 1, \
>-	.__runtime.has_hdcp = 1, \
>-	.display.has_ipc = 1, \
>-	.display.has_psr = 1, \
>-	.display.has_psr_hw_tracking = 1, \
>-	.display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
>-	.display.dbuf.slice_mask = BIT(DBUF_S1)
>+	.__runtime.has_hdcp = 1
>+
>+static const struct intel_display_device_info skl_display = {
>+	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
>+	.dbuf.slice_mask = BIT(DBUF_S1),
>+	.has_ddi = 1,
>+	.has_dp_mst = 1,
>+	.has_fpga_dbg = 1,
>+	.has_hotplug = 1,
>+	.has_ipc = 1,
>+	.has_psr = 1,
>+	.has_psr_hw_tracking = 1,
>+	HSW_PIPE_OFFSETS,
>+	IVB_CURSOR_OFFSETS,
>+	IVB_COLORS,
>+};
>
> #define SKL_PLATFORM \
> 	GEN9_FEATURES, \
>@@ -727,11 +861,13 @@ static const struct intel_device_info chv_info = {
>
> static const struct intel_device_info skl_gt1_info = {
> 	SKL_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info skl_gt2_info = {
> 	SKL_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 2,
> };
>
>@@ -743,19 +879,19 @@ static const struct intel_device_info skl_gt2_info = {
>
> static const struct intel_device_info skl_gt3_info = {
> 	SKL_GT3_PLUS_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 3,
> };
>
> static const struct intel_device_info skl_gt4_info = {
> 	SKL_GT3_PLUS_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 4,
> };
>
> #define GEN9_LP_FEATURES \
> 	GEN(9), \
> 	.is_lp = 1, \
>-	.display.dbuf.slice_mask = BIT(DBUF_S1), \
>-	.display.has_hotplug = 1, \
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>@@ -763,17 +899,12 @@ static const struct intel_device_info skl_gt4_info = {
> 		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
> 	.has_3d_pipeline = 1, \
> 	.has_64bit_reloc = 1, \
>-	.display.has_ddi = 1, \
>-	.display.has_fpga_dbg = 1, \
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> 	.__runtime.has_hdcp = 1, \
>-	.display.has_psr = 1, \
>-	.display.has_psr_hw_tracking = 1, \
> 	.has_runtime_pm = 1, \
> 	.__runtime.has_dmc = 1, \
> 	.has_rc6 = 1, \
> 	.has_rps = true, \
>-	.display.has_dp_mst = 1, \
> 	.has_logical_ring_contexts = 1, \
> 	.has_gt_uc = 1, \
> 	.dma_mask_size = 39, \
>@@ -782,27 +913,46 @@ static const struct intel_device_info skl_gt4_info = {
> 	.has_reset_engine = 1, \
> 	.has_snoop = true, \
> 	.has_coherent_ggtt = false, \
>-	.display.has_ipc = 1, \
> 	.max_pat_index = 3, \
>-	HSW_PIPE_OFFSETS, \
>-	IVB_CURSOR_OFFSETS, \
>-	IVB_COLORS, \
> 	GEN9_DEFAULT_PAGE_SIZES, \
> 	GEN_DEFAULT_REGIONS, \
> 	LEGACY_CACHELEVEL
>
>+#define GEN9_LP_DISPLAY \
>+	.dbuf.slice_mask = BIT(DBUF_S1), \
>+	.has_dp_mst = 1, \
>+	.has_ddi = 1, \
>+	.has_fpga_dbg = 1, \
>+	.has_hotplug = 1, \
>+	.has_ipc = 1, \
>+	.has_psr = 1, \
>+	.has_psr_hw_tracking = 1, \
>+	HSW_PIPE_OFFSETS, \
>+	IVB_CURSOR_OFFSETS, \
>+	IVB_COLORS
>+
>+static const struct intel_display_device_info bxt_display = {
>+	GEN9_LP_DISPLAY,
>+	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
>+};
>+
> static const struct intel_device_info bxt_info = {
> 	GEN9_LP_FEATURES,
> 	PLATFORM(INTEL_BROXTON),
>-	.display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
>+	.display = &bxt_display,
>+};
>+
>+static const struct intel_display_device_info glk_display = {
>+	GEN9_LP_DISPLAY,
>+	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
>+	GLK_COLORS,
> };
>
> static const struct intel_device_info glk_info = {
> 	GEN9_LP_FEATURES,
> 	PLATFORM(INTEL_GEMINILAKE),
> 	.__runtime.display.ip.ver = 10,
>-	.display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
>-	GLK_COLORS,
>+	.display = &glk_display,
> };
>
> #define KBL_PLATFORM \
>@@ -811,16 +961,19 @@ static const struct intel_device_info glk_info = {
>
> static const struct intel_device_info kbl_gt1_info = {
> 	KBL_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info kbl_gt2_info = {
> 	KBL_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 2,
> };
>
> static const struct intel_device_info kbl_gt3_info = {
> 	KBL_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 3,
> 	.__runtime.platform_engine_mask =
> 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
>@@ -832,16 +985,19 @@ static const struct intel_device_info kbl_gt3_info = {
>
> static const struct intel_device_info cfl_gt1_info = {
> 	CFL_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info cfl_gt2_info = {
> 	CFL_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 2,
> };
>
> static const struct intel_device_info cfl_gt3_info = {
> 	CFL_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 3,
> 	.__runtime.platform_engine_mask =
> 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
>@@ -853,11 +1009,13 @@ static const struct intel_device_info cfl_gt3_info = {
>
> static const struct intel_device_info cml_gt1_info = {
> 	CML_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 1,
> };
>
> static const struct intel_device_info cml_gt2_info = {
> 	CML_PLATFORM,
>+	.display = &skl_display,
> 	.gt = 2,
> };
>
>@@ -869,39 +1027,51 @@ static const struct intel_device_info cml_gt2_info = {
> #define GEN11_FEATURES \
> 	GEN9_FEATURES, \
> 	GEN11_DEFAULT_PAGE_SIZES, \
>-	.display.abox_mask = BIT(0), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
>-	.display.pipe_offsets = { \
>-		[TRANSCODER_A] = PIPE_A_OFFSET, \
>-		[TRANSCODER_B] = PIPE_B_OFFSET, \
>-		[TRANSCODER_C] = PIPE_C_OFFSET, \
>-		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
>-		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
>-		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
>-	}, \
>-	.display.trans_offsets = { \
>-		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>-		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
>-		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
>-		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
>-		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
>-		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
>-	}, \
> 	GEN(11), \
>-	ICL_COLORS, \
>-	.display.dbuf.size = 2048, \
>-	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> 	.__runtime.has_dsc = 1, \
> 	.has_coherent_ggtt = false, \
> 	.has_logical_ring_elsq = 1
>
>+static const struct intel_display_device_info gen11_display = {
>+	.abox_mask = BIT(0),
>+	.dbuf.size = 2048,
>+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
>+	.has_ddi = 1,
>+	.has_dp_mst = 1,
>+	.has_fpga_dbg = 1,
>+	.has_hotplug = 1,
>+	.has_ipc = 1,
>+	.has_psr = 1,
>+	.has_psr_hw_tracking = 1,
>+	.pipe_offsets = {
>+		[TRANSCODER_A] = PIPE_A_OFFSET,
>+		[TRANSCODER_B] = PIPE_B_OFFSET,
>+		[TRANSCODER_C] = PIPE_C_OFFSET,
>+		[TRANSCODER_EDP] = PIPE_EDP_OFFSET,
>+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
>+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
>+	},
>+	.trans_offsets = {
>+		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
>+		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
>+		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
>+		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
>+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
>+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
>+	},
>+	IVB_CURSOR_OFFSETS,
>+	ICL_COLORS,
>+};
>+
> static const struct intel_device_info icl_info = {
> 	GEN11_FEATURES,
> 	PLATFORM(INTEL_ICELAKE),
> 	.__runtime.platform_engine_mask =
> 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>+	.display = &gen11_display,
> };
>
> static const struct intel_device_info ehl_info = {
>@@ -909,6 +1079,7 @@ static const struct intel_device_info ehl_info = {
> 	PLATFORM(INTEL_ELKHARTLAKE),
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> 	.__runtime.ppgtt_size = 36,
>+	.display = &gen11_display,
> };
>
> static const struct intel_device_info jsl_info = {
>@@ -916,17 +1087,34 @@ static const struct intel_device_info jsl_info = {
> 	PLATFORM(INTEL_JASPERLAKE),
> 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> 	.__runtime.ppgtt_size = 36,
>+	.display = &gen11_display,
> };
>
> #define GEN12_FEATURES \
> 	GEN11_FEATURES, \
> 	GEN(12), \
>-	.display.abox_mask = GENMASK(2, 1), \
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
>-	.display.pipe_offsets = { \
>+	TGL_CACHELEVEL, \
>+	.has_global_mocs = 1, \
>+	.has_pxp = 1, \
>+	.max_pat_index = 3
>+
>+#define XE_D_DISPLAY \
>+	.abox_mask = GENMASK(2, 1), \
>+	.dbuf.size = 2048, \
>+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
>+	.has_ddi = 1, \
>+	.has_dp_mst = 1, \
>+	.has_dsb = 1, \
>+	.has_fpga_dbg = 1, \
>+	.has_hotplug = 1, \
>+	.has_ipc = 1, \
>+	.has_psr = 1, \
>+	.has_psr_hw_tracking = 1, \
>+	.pipe_offsets = { \
> 		[TRANSCODER_A] = PIPE_A_OFFSET, \
> 		[TRANSCODER_B] = PIPE_B_OFFSET, \
> 		[TRANSCODER_C] = PIPE_C_OFFSET, \
>@@ -934,7 +1122,7 @@ static const struct intel_device_info jsl_info = {
> 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> 	}, \
>-	.display.trans_offsets = { \
>+	.trans_offsets = { \
> 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
>@@ -943,30 +1131,36 @@ static const struct intel_device_info jsl_info = {
> 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> 	}, \
> 	TGL_CURSOR_OFFSETS, \
>-	TGL_CACHELEVEL, \
>-	.has_global_mocs = 1, \
>-	.has_pxp = 1, \
>-	.display.has_dsb = 1, \
>-	.max_pat_index = 3
>+	ICL_COLORS
>+
>+static const struct intel_display_device_info tgl_display = {
>+	XE_D_DISPLAY,
>+};
>
> static const struct intel_device_info tgl_info = {
> 	GEN12_FEATURES,
> 	PLATFORM(INTEL_TIGERLAKE),
> 	.__runtime.platform_engine_mask =
> 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>+	.display = &tgl_display,
>+};
>+
>+static const struct intel_display_device_info rkl_display = {
>+	XE_D_DISPLAY,
>+	.abox_mask = BIT(0),
>+	.has_hti = 1,
>+	.has_psr_hw_tracking = 0,
> };
>
> static const struct intel_device_info rkl_info = {
> 	GEN12_FEATURES,
> 	PLATFORM(INTEL_ROCKETLAKE),
>-	.display.abox_mask = BIT(0),
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> 		BIT(TRANSCODER_C),
>-	.display.has_hti = 1,
>-	.display.has_psr_hw_tracking = 0,
> 	.__runtime.platform_engine_mask =
> 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
>+	.display = &rkl_display,
> };
>
> #define DGFX_FEATURES \
>@@ -989,43 +1183,43 @@ static const struct intel_device_info dg1_info = {
> 		BIT(VCS0) | BIT(VCS2),
> 	/* Wa_16011227922 */
> 	.__runtime.ppgtt_size = 47,
>+	.display = &tgl_display,
>+};
>+
>+static const struct intel_display_device_info adl_s_display = {
>+	XE_D_DISPLAY,
>+	.has_hti = 1,
>+	.has_psr_hw_tracking = 0,
> };
>
> static const struct intel_device_info adl_s_info = {
> 	GEN12_FEATURES,
> 	PLATFORM(INTEL_ALDERLAKE_S),
> 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>-	.display.has_hti = 1,
>-	.display.has_psr_hw_tracking = 0,
> 	.__runtime.platform_engine_mask =
> 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> 	.dma_mask_size = 39,
>+	.display = &adl_s_display,
> };
>
> #define XE_LPD_FEATURES \
>-	.display.abox_mask = GENMASK(1, 0),					\
>-	.display.color = {							\
>+	.abox_mask = GENMASK(1, 0),						\
>+	.color = {								\
> 		.degamma_lut_size = 129, .gamma_lut_size = 1024,		\
> 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
>-				     DRM_COLOR_LUT_EQUAL_CHANNELS,		\
>+		DRM_COLOR_LUT_EQUAL_CHANNELS,					\
> 	},									\
>-	.display.dbuf.size = 4096,						\
>-	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |	\
>+	.dbuf.size = 4096,							\
>+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
> 		BIT(DBUF_S4),							\
>-	.display.has_ddi = 1,							\
>-	.__runtime.has_dmc = 1,							\
>-	.display.has_dp_mst = 1,						\
>-	.display.has_dsb = 1,							\
>-	.__runtime.has_dsc = 1,							\
>-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
>-	.display.has_fpga_dbg = 1,						\
>-	.__runtime.has_hdcp = 1,						\
>-	.display.has_hotplug = 1,						\
>-	.display.has_ipc = 1,							\
>-	.display.has_psr = 1,							\
>-	.__runtime.display.ip.ver = 13,							\
>-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\
>-	.display.pipe_offsets = {						\
>+	.has_ddi = 1,								\
>+	.has_dp_mst = 1,							\
>+	.has_dsb = 1,								\
>+	.has_fpga_dbg = 1,							\
>+	.has_hotplug = 1,							\
>+	.has_ipc = 1,								\
>+	.has_psr = 1,								\
>+	.pipe_offsets = {							\
> 		[TRANSCODER_A] = PIPE_A_OFFSET,					\
> 		[TRANSCODER_B] = PIPE_B_OFFSET,					\
> 		[TRANSCODER_C] = PIPE_C_OFFSET,					\
>@@ -1033,7 +1227,7 @@ static const struct intel_device_info adl_s_info = {
> 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
> 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
> 	},									\
>-	.display.trans_offsets = {						\
>+	.trans_offsets = {						\
> 		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
> 		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
> 		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
>@@ -1043,18 +1237,31 @@ static const struct intel_device_info adl_s_info = {
> 	},									\
> 	TGL_CURSOR_OFFSETS
>
>+#define XE_LPD_RUNTIME \
>+	.__runtime.has_dmc = 1,							\
>+	.__runtime.has_dsc = 1,							\
>+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
>+	.__runtime.has_hdcp = 1,						\
>+	.__runtime.display.ip.ver = 13,							\
>+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
>+
>+static const struct intel_display_device_info xe_lpd_display = {
>+	XE_LPD_FEATURES,
>+	.has_cdclk_crawl = 1,
>+	.has_psr_hw_tracking = 0,
>+};
>+
> static const struct intel_device_info adl_p_info = {
> 	GEN12_FEATURES,
>-	XE_LPD_FEATURES,
>+	XE_LPD_RUNTIME,
> 	PLATFORM(INTEL_ALDERLAKE_P),
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> 			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
>-	.display.has_cdclk_crawl = 1,
>-	.display.has_psr_hw_tracking = 0,
> 	.__runtime.platform_engine_mask =
> 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> 	.__runtime.ppgtt_size = 48,
>+	.display = &xe_lpd_display,
> 	.dma_mask_size = 39,
> };
>
>@@ -1125,18 +1332,23 @@ static const struct intel_device_info xehpsdv_info = {
> 	.has_guc_deprivilege = 1, \
> 	.has_heci_pxp = 1, \
> 	.has_media_ratio_mode = 1, \
>-	.display.has_cdclk_squash = 1, \
> 	.__runtime.platform_engine_mask = \
> 		BIT(RCS0) | BIT(BCS0) | \
> 		BIT(VECS0) | BIT(VECS1) | \
> 		BIT(VCS0) | BIT(VCS2) | \
> 		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
>
>+static const struct intel_display_device_info xe_hpd_display = {
>+	XE_LPD_FEATURES,
>+	.has_cdclk_squash = 1,
>+};
>+
> static const struct intel_device_info dg2_info = {
> 	DG2_FEATURES,
>-	XE_LPD_FEATURES,
>+	XE_LPD_RUNTIME,
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>+	.display = &xe_hpd_display,
> };
>
> static const struct intel_device_info ats_m_info = {
>@@ -1174,11 +1386,9 @@ static const struct intel_device_info pvc_info = {
> 	PVC_CACHELEVEL,
> };
>
>-#define XE_LPDP_FEATURES	\
>-	XE_LPD_FEATURES,	\
>+#define XE_LPDP_RUNTIME	\
>+	XE_LPD_RUNTIME,	\
> 	.__runtime.display.ip.ver = 14,	\
>-	.display.has_cdclk_crawl = 1, \
>-	.display.has_cdclk_squash = 1, \
> 	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
>
> static const struct intel_gt_definition xelpmp_extra_gt[] = {
>@@ -1191,9 +1401,15 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
> 	{}
> };
>
>+static const struct intel_display_device_info xe_lpdp_display = {
>+	XE_LPD_FEATURES,
>+	.has_cdclk_crawl = 1,
>+	.has_cdclk_squash = 1,
>+};
>+
> static const struct intel_device_info mtl_info = {
> 	XE_HP_FEATURES,
>-	XE_LPDP_FEATURES,
>+	XE_LPDP_RUNTIME,
> 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> 	/*
>@@ -1204,6 +1420,7 @@ static const struct intel_device_info mtl_info = {
> 	.__runtime.graphics.ip.rel = 70,
> 	.__runtime.media.ip.ver = 13,
> 	PLATFORM(INTEL_METEORLAKE),
>+	.display = &xe_lpdp_display,
> 	.extra_gt_list = xelpmp_extra_gt,
> 	.has_flat_ccs = 0,
> 	.has_gmd_id = 1,
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index 4e23be2995bf..d0bf626d0360 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -138,7 +138,7 @@ void intel_device_info_print(const struct intel_device_info *info,
>
> 	drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
>
>-#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
>+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
> 	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
> #undef PRINT_FLAG
>
>@@ -388,6 +388,8 @@ mkwrite_device_info(struct drm_i915_private *i915)
> 	return (struct intel_device_info *)INTEL_INFO(i915);
> }
>
>+static const struct intel_display_device_info no_display = { 0 };
>+
> /**
>  * intel_device_info_runtime_init - initialize runtime info
>  * @dev_priv: the i915 device
>@@ -538,7 +540,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> 	if (!HAS_DISPLAY(dev_priv)) {
> 		dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
> 						   DRIVER_ATOMIC);
>-		memset(&info->display, 0, sizeof(info->display));
>+		info->display = &no_display;
>
> 		runtime->cpu_transcoder_mask = 0;
> 		memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index 96f6bdb04b1b..f212e02e6582 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -259,7 +259,7 @@ struct intel_device_info {
> 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
>
>-	struct intel_display_device_info display;
>+	const struct intel_display_device_info *display;
>
> 	/*
> 	 * Initial runtime info. Do not access outside of i915_driver_create().
>-- 
>2.40.0
>

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
  2023-05-18  5:24   ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
@ 2023-05-18  6:44   ` Andrzej Hajda
  1 sibling, 0 replies; 21+ messages in thread
From: Andrzej Hajda @ 2023-05-18  6:44 UTC (permalink / raw)
  To: Matt Roper, intel-gfx; +Cc: intel-xe

On 18.05.2023 05:18, Matt Roper wrote:
> Rather than embeddeding the display's device info within the main device
> info structure, just provide a pointer to the display-specific
> structure.  This is in preparation for moving the display device info
> definitions into the display code itself and for eventually allowing the
> pointer to be assigned at runtime on platforms that use GMD_ID for
> device identification.
> 
> In the future, this will also eventually allow the same display device
> info structures to be used outside the current i915 code (e.g., from the
> Xe driver).
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c    |  30 +-
>   drivers/gpu/drm/i915/display/intel_cursor.c   |   2 +-
>   drivers/gpu/drm/i915/display/intel_display.h  |   2 +-
>   .../drm/i915/display/intel_display_power.c    |   6 +-
>   .../drm/i915/display/intel_display_reg_defs.h |  14 +-
>   drivers/gpu/drm/i915/display/intel_fb_pin.c   |   2 +-
>   drivers/gpu/drm/i915/display/intel_hti.c      |   2 +-
>   drivers/gpu/drm/i915/display/skl_watermark.c  |   8 +-
>   drivers/gpu/drm/i915/i915_drv.h               |  28 +-
>   drivers/gpu/drm/i915/i915_pci.c               | 579 ++++++++++++------
>   drivers/gpu/drm/i915/intel_device_info.c      |   6 +-
>   drivers/gpu/drm/i915/intel_device_info.h      |   2 +-
>   12 files changed, 450 insertions(+), 231 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 07f1afe1d406..ba32808f434b 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)
>   	if (lut_is_legacy(gamma_lut))
>   		return 0;
>   
> -	return INTEL_INFO(i915)->display.color.gamma_lut_tests;
> +	return INTEL_INFO(i915)->display->color.gamma_lut_tests;

Looking at the number of occurences of INTEL_INFO(i915)->display we 
could define:
#define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)

but I do not know if it will be helpful in further steps in abstracting 
out display from core.

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

>   }
>   
>   static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   
> -	return INTEL_INFO(i915)->display.color.degamma_lut_tests;
> +	return INTEL_INFO(i915)->display->color.degamma_lut_tests;
>   }
>   
>   static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
> @@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
>   	if (lut_is_legacy(gamma_lut))
>   		return LEGACY_LUT_LENGTH;
>   
> -	return INTEL_INFO(i915)->display.color.gamma_lut_size;
> +	return INTEL_INFO(i915)->display->color.gamma_lut_size;
>   }
>   
>   static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>   
> -	return INTEL_INFO(i915)->display.color.degamma_lut_size;
> +	return INTEL_INFO(i915)->display->color.degamma_lut_size;
>   }
>   
>   static int check_lut_size(const struct drm_property_blob *lut, int expected)
> @@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state *crtc_state)
>   		struct drm_property_blob *gamma_lut;
>   
>   		gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
> -					       INTEL_INFO(i915)->display.color.degamma_lut_size,
> +					       INTEL_INFO(i915)->display->color.degamma_lut_size,
>   					       false);
>   		if (IS_ERR(gamma_lut))
>   			return PTR_ERR(gamma_lut);
> @@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
>   static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> +	u32 lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> @@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
>   static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> +	int i, lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> @@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
>   static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
> +	int i, lut_size = INTEL_INFO(dev_priv)->display->color.degamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> @@ -2980,7 +2980,7 @@ static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
>   static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> +	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> @@ -3044,7 +3044,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
>   static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> +	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> @@ -3228,7 +3228,7 @@ static void bdw_read_luts(struct intel_crtc_state *crtc_state)
>   static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
> +	int i, lut_size = INTEL_INFO(dev_priv)->display->color.degamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> @@ -3293,7 +3293,7 @@ static struct drm_property_blob *
>   icl_read_lut_multi_segment(struct intel_crtc *crtc)
>   {
>   	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> -	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> +	int i, lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> @@ -3471,8 +3471,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
>   
>   	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
>   
> -	gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> -	degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
> +	gamma_lut_size = INTEL_INFO(i915)->display->color.gamma_lut_size;
> +	degamma_lut_size = INTEL_INFO(i915)->display->color.degamma_lut_size;
>   	has_ctm = degamma_lut_size != 0;
>   
>   	/*
> @@ -3497,7 +3497,7 @@ int intel_color_init(struct drm_i915_private *i915)
>   	if (DISPLAY_VER(i915) != 10)
>   		return 0;
>   
> -	blob = create_linear_lut(i915, INTEL_INFO(i915)->display.color.degamma_lut_size);
> +	blob = create_linear_lut(i915, INTEL_INFO(i915)->display->color.degamma_lut_size);
>   	if (IS_ERR(blob))
>   		return PTR_ERR(blob);
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 31bef0427377..dd2def27add9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -36,7 +36,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
>   	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>   	u32 base;
>   
> -	if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
> +	if (INTEL_INFO(dev_priv)->display->cursor_needs_physical)
>   		base = sg_dma_address(obj->mm.pages->sgl);
>   	else
>   		base = intel_plane_ggtt_offset(plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 205b3929b861..aa3a21ccd7fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -113,7 +113,7 @@ enum i9xx_plane_id {
>   
>   #define for_each_dbuf_slice(__dev_priv, __slice) \
>   	for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
> -		for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
> +		for_each_if(INTEL_INFO(__dev_priv)->display->dbuf.slice_mask & BIT(__slice))
>   
>   #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
>   	for_each_dbuf_slice((__dev_priv), (__slice)) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 6ed2ece89c3f..68a7ab20ff16 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1053,7 +1053,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
>   			     u8 req_slices)
>   {
>   	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> -	u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
> +	u8 slice_mask = INTEL_INFO(dev_priv)->display->dbuf.slice_mask;
>   	enum dbuf_slice slice;
>   
>   	drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
> @@ -1113,7 +1113,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
>   
>   static void icl_mbus_init(struct drm_i915_private *dev_priv)
>   {
> -	unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
> +	unsigned long abox_regs = INTEL_INFO(dev_priv)->display->abox_mask;
>   	u32 mask, val, i;
>   
>   	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
> @@ -1568,7 +1568,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>   	enum intel_dram_type type = dev_priv->dram_info.type;
>   	u8 num_channels = dev_priv->dram_info.num_channels;
>   	const struct buddy_page_mask *table;
> -	unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
> +	unsigned long abox_mask = INTEL_INFO(dev_priv)->display->abox_mask;
>   	int config, i;
>   
>   	/* BW_BUDDY registers are not used on dgpu's beyond DG1 */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> index 755c1ea8225c..e0f82f28d8b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> @@ -8,7 +8,7 @@
>   
>   #include "i915_reg_defs.h"
>   
> -#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display.mmio_offset)
> +#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display->mmio_offset)
>   
>   #define VLV_DISPLAY_BASE		0x180000
>   
> @@ -36,14 +36,14 @@
>    * Device info offset array based helpers for groups of registers with unevenly
>    * spaced base offsets.
>    */
> -#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
> -					      INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
> +#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display->pipe_offsets[(pipe)] - \
> +					      INTEL_INFO(dev_priv)->display->pipe_offsets[PIPE_A] + \
>   					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
> -#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
> -					      INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
> +#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display->trans_offsets[(tran)] - \
> +					      INTEL_INFO(dev_priv)->display->trans_offsets[TRANSCODER_A] + \
>   					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
> -#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
> -					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
> +#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display->cursor_offsets[(pipe)] - \
> +					      INTEL_INFO(dev_priv)->display->cursor_offsets[PIPE_A] + \
>   					      DISPLAY_MMIO_BASE(dev_priv) + (reg))
>   
>   #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> index 1aca7552a85d..9ed11936d967 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> @@ -243,7 +243,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
>   	struct i915_vma *vma;
>   	bool phys_cursor =
>   		plane->id == PLANE_CURSOR &&
> -		INTEL_INFO(dev_priv)->display.cursor_needs_physical;
> +		INTEL_INFO(dev_priv)->display->cursor_needs_physical;
>   
>   	if (!intel_fb_uses_dpt(fb)) {
>   		vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
> diff --git a/drivers/gpu/drm/i915/display/intel_hti.c b/drivers/gpu/drm/i915/display/intel_hti.c
> index c518efebdf77..92a48aeef860 100644
> --- a/drivers/gpu/drm/i915/display/intel_hti.c
> +++ b/drivers/gpu/drm/i915/display/intel_hti.c
> @@ -15,7 +15,7 @@ void intel_hti_init(struct drm_i915_private *i915)
>   	 * If the platform has HTI, we need to find out whether it has reserved
>   	 * any display resources before we create our display outputs.
>   	 */
> -	if (INTEL_INFO(i915)->display.has_hti)
> +	if (INTEL_INFO(i915)->display->has_hti)
>   		i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
>   }
>   
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1c7e6468f3e3..4189eb3b8ff8 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -507,8 +507,8 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
>   
>   static int intel_dbuf_slice_size(struct drm_i915_private *i915)
>   {
> -	return INTEL_INFO(i915)->display.dbuf.size /
> -		hweight8(INTEL_INFO(i915)->display.dbuf.slice_mask);
> +	return INTEL_INFO(i915)->display->dbuf.size /
> +		hweight8(INTEL_INFO(i915)->display->dbuf.slice_mask);
>   }
>   
>   static void
> @@ -527,7 +527,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask,
>   	ddb->end = fls(slice_mask) * slice_size;
>   
>   	WARN_ON(ddb->start >= ddb->end);
> -	WARN_ON(ddb->end > INTEL_INFO(i915)->display.dbuf.size);
> +	WARN_ON(ddb->end > INTEL_INFO(i915)->display->dbuf.size);
>   }
>   
>   static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
> @@ -2625,7 +2625,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
>   			    "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
>   			    old_dbuf_state->enabled_slices,
>   			    new_dbuf_state->enabled_slices,
> -			    INTEL_INFO(i915)->display.dbuf.slice_mask,
> +			    INTEL_INFO(i915)->display->dbuf.slice_mask,
>   			    str_yes_no(old_dbuf_state->joined_mbus),
>   			    str_yes_no(new_dbuf_state->joined_mbus));
>   	}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 14c5338c96a6..116fc4441f8b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -782,9 +782,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   	((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
>   })
>   
> -#define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display.has_overlay)
> +#define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display->has_overlay)
>   #define OVERLAY_NEEDS_PHYSICAL(i915) \
> -		(INTEL_INFO(i915)->display.overlay_needs_physical)
> +		(INTEL_INFO(i915)->display->overlay_needs_physical)
>   
>   /* Early gen2 have a totally busted CS tlb and require pinned batches. */
>   #define HAS_BROKEN_CS_TLB(i915)	(IS_I830(i915) || IS_I845G(i915))
> @@ -806,8 +806,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>    */
>   #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
>   					 !(IS_I915G(i915) || IS_I915GM(i915)))
> -#define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display.supports_tv)
> -#define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display.has_hotplug)
> +#define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display->supports_tv)
> +#define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display->has_hotplug)
>   
>   #define HAS_FW_BLC(i915)	(DISPLAY_VER(i915) > 2)
>   #define HAS_FBC(i915)	(RUNTIME_INFO(i915)->fbc_mask != 0)
> @@ -817,18 +817,18 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   
>   #define HAS_IPS(i915)	(IS_HSW_ULT(i915) || IS_BROADWELL(i915))
>   
> -#define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display.has_dp_mst)
> +#define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display->has_dp_mst)
>   #define HAS_DP20(i915)	(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
>   
>   #define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
>   
> -#define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display.has_cdclk_crawl)
> -#define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display.has_cdclk_squash)
> -#define HAS_DDI(i915)		 (INTEL_INFO(i915)->display.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
> -#define HAS_PSR(i915)		 (INTEL_INFO(i915)->display.has_psr)
> +#define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display->has_cdclk_crawl)
> +#define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display->has_cdclk_squash)
> +#define HAS_DDI(i915)		 (INTEL_INFO(i915)->display->has_ddi)
> +#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display->has_fpga_dbg)
> +#define HAS_PSR(i915)		 (INTEL_INFO(i915)->display->has_psr)
>   #define HAS_PSR_HW_TRACKING(i915) \
> -	(INTEL_INFO(i915)->display.has_psr_hw_tracking)
> +	(INTEL_INFO(i915)->display->has_psr_hw_tracking)
>   #define HAS_PSR2_SEL_FETCH(i915)	 (DISPLAY_VER(i915) >= 12)
>   #define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
>   
> @@ -839,7 +839,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define HAS_RPS(i915)	(INTEL_INFO(i915)->has_rps)
>   
>   #define HAS_DMC(i915)	(RUNTIME_INFO(i915)->has_dmc)
> -#define HAS_DSB(i915)	(INTEL_INFO(i915)->display.has_dsb)
> +#define HAS_DSB(i915)	(INTEL_INFO(i915)->display->has_dsb)
>   #define HAS_DSC(__i915)		(RUNTIME_INFO(__i915)->has_dsc)
>   #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
>   
> @@ -869,7 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>    */
>   #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
>   
> -#define HAS_IPC(i915)		(INTEL_INFO(i915)->display.has_ipc)
> +#define HAS_IPC(i915)		(INTEL_INFO(i915)->display->has_ipc)
>   #define HAS_SAGV(i915)		(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
>   
>   #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
> @@ -889,7 +889,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   
>   #define HAS_GLOBAL_MOCS_REGISTERS(i915)	(INTEL_INFO(i915)->has_global_mocs)
>   
> -#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
> +#define HAS_GMCH(i915) (INTEL_INFO(i915)->display->has_gmch)
>   
>   #define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
>   
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index e4a19161afce..dd874a4db604 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -47,43 +47,43 @@
>   #define NO_DISPLAY .__runtime.pipe_mask = 0
>   
>   #define I845_PIPE_OFFSETS \
> -	.display.pipe_offsets = { \
> +	.pipe_offsets = { \
>   		[TRANSCODER_A] = PIPE_A_OFFSET,	\
>   	}, \
> -	.display.trans_offsets = { \
> +	.trans_offsets = { \
>   		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>   	}
>   
>   #define I9XX_PIPE_OFFSETS \
> -	.display.pipe_offsets = { \
> +	.pipe_offsets = { \
>   		[TRANSCODER_A] = PIPE_A_OFFSET,	\
>   		[TRANSCODER_B] = PIPE_B_OFFSET, \
>   	}, \
> -	.display.trans_offsets = { \
> +	.trans_offsets = { \
>   		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>   		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
>   	}
>   
>   #define IVB_PIPE_OFFSETS \
> -	.display.pipe_offsets = { \
> +	.pipe_offsets = { \
>   		[TRANSCODER_A] = PIPE_A_OFFSET,	\
>   		[TRANSCODER_B] = PIPE_B_OFFSET, \
>   		[TRANSCODER_C] = PIPE_C_OFFSET, \
>   	}, \
> -	.display.trans_offsets = { \
> +	.trans_offsets = { \
>   		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>   		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
>   		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
>   	}
>   
>   #define HSW_PIPE_OFFSETS \
> -	.display.pipe_offsets = { \
> +	.pipe_offsets = { \
>   		[TRANSCODER_A] = PIPE_A_OFFSET,	\
>   		[TRANSCODER_B] = PIPE_B_OFFSET, \
>   		[TRANSCODER_C] = PIPE_C_OFFSET, \
>   		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
>   	}, \
> -	.display.trans_offsets = { \
> +	.trans_offsets = { \
>   		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>   		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
>   		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> @@ -91,44 +91,44 @@
>   	}
>   
>   #define CHV_PIPE_OFFSETS \
> -	.display.pipe_offsets = { \
> +	.pipe_offsets = { \
>   		[TRANSCODER_A] = PIPE_A_OFFSET, \
>   		[TRANSCODER_B] = PIPE_B_OFFSET, \
>   		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
>   	}, \
> -	.display.trans_offsets = { \
> +	.trans_offsets = { \
>   		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>   		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
>   		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
>   	}
>   
>   #define I845_CURSOR_OFFSETS \
> -	.display.cursor_offsets = { \
> +	.cursor_offsets = { \
>   		[PIPE_A] = CURSOR_A_OFFSET, \
>   	}
>   
>   #define I9XX_CURSOR_OFFSETS \
> -	.display.cursor_offsets = { \
> +	.cursor_offsets = { \
>   		[PIPE_A] = CURSOR_A_OFFSET, \
>   		[PIPE_B] = CURSOR_B_OFFSET, \
>   	}
>   
>   #define CHV_CURSOR_OFFSETS \
> -	.display.cursor_offsets = { \
> +	.cursor_offsets = { \
>   		[PIPE_A] = CURSOR_A_OFFSET, \
>   		[PIPE_B] = CURSOR_B_OFFSET, \
>   		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
>   	}
>   
>   #define IVB_CURSOR_OFFSETS \
> -	.display.cursor_offsets = { \
> +	.cursor_offsets = { \
>   		[PIPE_A] = CURSOR_A_OFFSET, \
>   		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
>   		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
>   	}
>   
>   #define TGL_CURSOR_OFFSETS \
> -	.display.cursor_offsets = { \
> +	.cursor_offsets = { \
>   		[PIPE_A] = CURSOR_A_OFFSET, \
>   		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
>   		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
> @@ -136,29 +136,29 @@
>   	}
>   
>   #define I845_COLORS \
> -	.display.color = { .gamma_lut_size = 256 }
> +	.color = { .gamma_lut_size = 256 }
>   #define I9XX_COLORS \
> -	.display.color = { .gamma_lut_size = 129, \
> +	.color = { .gamma_lut_size = 129, \
>   		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
>   	}
>   #define ILK_COLORS \
> -	.display.color = { .gamma_lut_size = 1024 }
> +	.color = { .gamma_lut_size = 1024 }
>   #define IVB_COLORS \
> -	.display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> +	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
>   #define CHV_COLORS \
> -	.display.color = { \
> +	.color = { \
>   		.degamma_lut_size = 65, .gamma_lut_size = 257, \
>   		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
>   		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
>   	}
>   #define GLK_COLORS \
> -	.display.color = { \
> +	.color = { \
>   		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
>   		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
>   				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
>   	}
>   #define ICL_COLORS \
> -	.display.color = { \
> +	.color = { \
>   		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
>   		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
>   				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
> @@ -205,15 +205,24 @@
>   #define GEN_DEFAULT_REGIONS \
>   	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
>   
> +#define I830_DISPLAY \
> +	.has_overlay = 1, \
> +	.cursor_needs_physical = 1, \
> +	.overlay_needs_physical = 1, \
> +	.has_gmch = 1, \
> +	I9XX_PIPE_OFFSETS, \
> +	I9XX_CURSOR_OFFSETS, \
> +	I9XX_COLORS
> +
> +static const struct intel_display_device_info i830_display = {
> +	I830_DISPLAY,
> +};
> +
>   #define I830_FEATURES \
>   	GEN(2), \
>   	.is_mobile = 1, \
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> -	.display.has_overlay = 1, \
> -	.display.cursor_needs_physical = 1, \
> -	.display.overlay_needs_physical = 1, \
> -	.display.has_gmch = 1, \
>   	.gpu_reset_clobbers_display = true, \
>   	.has_3d_pipeline = 1, \
>   	.hws_needs_physical = 1, \
> @@ -223,20 +232,26 @@
>   	.has_coherent_ggtt = false, \
>   	.dma_mask_size = 32, \
>   	.max_pat_index = 3, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS, \
>   	GEN_DEFAULT_PAGE_SIZES, \
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
>   
> +#define I845_DISPLAY \
> +	.has_overlay = 1, \
> +	.overlay_needs_physical = 1, \
> +	.has_gmch = 1, \
> +	I845_PIPE_OFFSETS, \
> +	I845_CURSOR_OFFSETS, \
> +	I845_COLORS
> +
> +static const struct intel_display_device_info i845_display = {
> +	I845_DISPLAY,
> +};
> +
>   #define I845_FEATURES \
>   	GEN(2), \
>   	.__runtime.pipe_mask = BIT(PIPE_A), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
> -	.display.has_overlay = 1, \
> -	.display.overlay_needs_physical = 1, \
> -	.display.has_gmch = 1, \
>   	.has_3d_pipeline = 1, \
>   	.gpu_reset_clobbers_display = true, \
>   	.hws_needs_physical = 1, \
> @@ -246,9 +261,6 @@
>   	.has_coherent_ggtt = false, \
>   	.dma_mask_size = 32, \
>   	.max_pat_index = 3, \
> -	I845_PIPE_OFFSETS, \
> -	I845_CURSOR_OFFSETS, \
> -	I845_COLORS, \
>   	GEN_DEFAULT_PAGE_SIZES, \
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
> @@ -256,30 +268,81 @@
>   static const struct intel_device_info i830_info = {
>   	I830_FEATURES,
>   	PLATFORM(INTEL_I830),
> +	.display = &i830_display,
>   };
>   
>   static const struct intel_device_info i845g_info = {
>   	I845_FEATURES,
>   	PLATFORM(INTEL_I845G),
> +	.display = &i845_display,
> +};
> +
> +static const struct intel_display_device_info i85x_display = {
> +	I830_DISPLAY,
>   };
>   
>   static const struct intel_device_info i85x_info = {
>   	I830_FEATURES,
>   	PLATFORM(INTEL_I85X),
> +	.display = &i85x_display,
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
> +static const struct intel_display_device_info i865g_display = {
> +	I845_DISPLAY,
> +};
> +
>   static const struct intel_device_info i865g_info = {
>   	I845_FEATURES,
>   	PLATFORM(INTEL_I865G),
> +	.display = &i865g_display,
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
> +#define GEN3_DISPLAY \
> +	.has_gmch = 1, \
> +	.has_overlay = 1, \
> +	I9XX_PIPE_OFFSETS, \
> +	I9XX_CURSOR_OFFSETS, \
> +	I9XX_COLORS
> +
> +static const struct intel_display_device_info i915g_display = {
> +	GEN3_DISPLAY,
> +	.cursor_needs_physical = 1,
> +	.overlay_needs_physical = 1,
> +};
> +
> +static const struct intel_display_device_info i915gm_display = {
> +	GEN3_DISPLAY,
> +	.cursor_needs_physical = 1,
> +	.overlay_needs_physical = 1,
> +	.supports_tv = 1,
> +};
> +
> +static const struct intel_display_device_info i945g_display = {
> +	GEN3_DISPLAY,
> +	.has_hotplug = 1,
> +	.cursor_needs_physical = 1,
> +	.overlay_needs_physical = 1,
> +};
> +
> +static const struct intel_display_device_info i945gm_display = {
> +	GEN3_DISPLAY,
> +	.has_hotplug = 1,
> +	.cursor_needs_physical = 1,
> +	.overlay_needs_physical = 1,
> +	.supports_tv = 1,
> +};
> +
> +static const struct intel_display_device_info g33_display = {
> +	GEN3_DISPLAY,
> +	.has_hotplug = 1,
> +};
> +
>   #define GEN3_FEATURES \
>   	GEN(3), \
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> -	.display.has_gmch = 1, \
>   	.gpu_reset_clobbers_display = true, \
>   	.__runtime.platform_engine_mask = BIT(RCS0), \
>   	.has_3d_pipeline = 1, \
> @@ -287,9 +350,6 @@ static const struct intel_device_info i865g_info = {
>   	.has_coherent_ggtt = true, \
>   	.dma_mask_size = 32, \
>   	.max_pat_index = 3, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS, \
>   	GEN_DEFAULT_PAGE_SIZES, \
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
> @@ -297,10 +357,8 @@ static const struct intel_device_info i865g_info = {
>   static const struct intel_device_info i915g_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_I915G),
> +	.display = &i915g_display,
>   	.has_coherent_ggtt = false,
> -	.display.cursor_needs_physical = 1,
> -	.display.has_overlay = 1,
> -	.display.overlay_needs_physical = 1,
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
>   };
> @@ -308,11 +366,8 @@ static const struct intel_device_info i915g_info = {
>   static const struct intel_device_info i915gm_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_I915GM),
> +	.display = &i915gm_display,
>   	.is_mobile = 1,
> -	.display.cursor_needs_physical = 1,
> -	.display.has_overlay = 1,
> -	.display.overlay_needs_physical = 1,
> -	.display.supports_tv = 1,
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
> @@ -321,10 +376,7 @@ static const struct intel_device_info i915gm_info = {
>   static const struct intel_device_info i945g_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_I945G),
> -	.display.has_hotplug = 1,
> -	.display.cursor_needs_physical = 1,
> -	.display.has_overlay = 1,
> -	.display.overlay_needs_physical = 1,
> +	.display = &i945g_display,
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
>   };
> @@ -332,12 +384,8 @@ static const struct intel_device_info i945g_info = {
>   static const struct intel_device_info i945gm_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_I945GM),
> +	.display = &i945gm_display,
>   	.is_mobile = 1,
> -	.display.has_hotplug = 1,
> -	.display.cursor_needs_physical = 1,
> -	.display.has_overlay = 1,
> -	.display.overlay_needs_physical = 1,
> -	.display.supports_tv = 1,
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
> @@ -346,16 +394,14 @@ static const struct intel_device_info i945gm_info = {
>   static const struct intel_device_info g33_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_G33),
> -	.display.has_hotplug = 1,
> -	.display.has_overlay = 1,
> +	.display = &g33_display,
>   	.dma_mask_size = 36,
>   };
>   
>   static const struct intel_device_info pnv_g_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_PINEVIEW),
> -	.display.has_hotplug = 1,
> -	.display.has_overlay = 1,
> +	.display = &g33_display,
>   	.dma_mask_size = 36,
>   };
>   
> @@ -363,17 +409,41 @@ static const struct intel_device_info pnv_m_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_PINEVIEW),
>   	.is_mobile = 1,
> -	.display.has_hotplug = 1,
> -	.display.has_overlay = 1,
> +	.display = &g33_display,
>   	.dma_mask_size = 36,
>   };
>   
> +#define GEN4_DISPLAY \
> +	.has_hotplug = 1, \
> +	.has_gmch = 1, \
> +	I9XX_PIPE_OFFSETS, \
> +	I9XX_CURSOR_OFFSETS, \
> +	I9XX_COLORS
> +
> +static const struct intel_display_device_info i965g_display = {
> +	GEN4_DISPLAY,
> +	.has_overlay = 1,
> +};
> +
> +static const struct intel_display_device_info i965gm_display = {
> +	GEN4_DISPLAY,
> +	.has_overlay = 1,
> +	.supports_tv = 1,
> +};
> +
> +static const struct intel_display_device_info g45_display = {
> +	GEN4_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info gm45_display = {
> +	GEN4_DISPLAY,
> +	.supports_tv = 1,
> +};
> +
>   #define GEN4_FEATURES \
>   	GEN(4), \
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> -	.display.has_hotplug = 1, \
> -	.display.has_gmch = 1, \
>   	.gpu_reset_clobbers_display = true, \
>   	.__runtime.platform_engine_mask = BIT(RCS0), \
>   	.has_3d_pipeline = 1, \
> @@ -381,9 +451,6 @@ static const struct intel_device_info pnv_m_info = {
>   	.has_coherent_ggtt = true, \
>   	.dma_mask_size = 36, \
>   	.max_pat_index = 3, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS, \
>   	GEN_DEFAULT_PAGE_SIZES, \
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
> @@ -391,7 +458,7 @@ static const struct intel_device_info pnv_m_info = {
>   static const struct intel_device_info i965g_info = {
>   	GEN4_FEATURES,
>   	PLATFORM(INTEL_I965G),
> -	.display.has_overlay = 1,
> +	.display = &i965g_display,
>   	.hws_needs_physical = 1,
>   	.has_snoop = false,
>   };
> @@ -399,10 +466,9 @@ static const struct intel_device_info i965g_info = {
>   static const struct intel_device_info i965gm_info = {
>   	GEN4_FEATURES,
>   	PLATFORM(INTEL_I965GM),
> +	.display = &i965gm_display,
>   	.is_mobile = 1,
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -	.display.has_overlay = 1,
> -	.display.supports_tv = 1,
>   	.hws_needs_physical = 1,
>   	.has_snoop = false,
>   };
> @@ -411,6 +477,7 @@ static const struct intel_device_info g45_info = {
>   	GEN4_FEATURES,
>   	PLATFORM(INTEL_G45),
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> +	.display = &g45_display,
>   	.gpu_reset_clobbers_display = false,
>   };
>   
> @@ -419,8 +486,8 @@ static const struct intel_device_info gm45_info = {
>   	PLATFORM(INTEL_GM45),
>   	.is_mobile = 1,
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -	.display.supports_tv = 1,
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> +	.display = &gm45_display,
>   	.gpu_reset_clobbers_display = false,
>   };
>   
> @@ -428,7 +495,6 @@ static const struct intel_device_info gm45_info = {
>   	GEN(5), \
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> -	.display.has_hotplug = 1, \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
>   	.has_3d_pipeline = 1, \
>   	.has_snoop = true, \
> @@ -437,21 +503,34 @@ static const struct intel_device_info gm45_info = {
>   	.has_rc6 = 0, \
>   	.dma_mask_size = 36, \
>   	.max_pat_index = 3, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	ILK_COLORS, \
>   	GEN_DEFAULT_PAGE_SIZES, \
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
>   
> +#define ILK_DISPLAY \
> +	.has_hotplug = 1, \
> +	I9XX_PIPE_OFFSETS, \
> +	I9XX_CURSOR_OFFSETS, \
> +	ILK_COLORS
> +
> +static const struct intel_display_device_info ilk_d_display = {
> +	ILK_DISPLAY,
> +};
> +
>   static const struct intel_device_info ilk_d_info = {
>   	GEN5_FEATURES,
>   	PLATFORM(INTEL_IRONLAKE),
> +	.display = &ilk_d_display,
> +};
> +
> +static const struct intel_display_device_info ilk_m_display = {
> +	ILK_DISPLAY,
>   };
>   
>   static const struct intel_device_info ilk_m_info = {
>   	GEN5_FEATURES,
>   	PLATFORM(INTEL_IRONLAKE),
> +	.display = &ilk_m_display,
>   	.is_mobile = 1,
>   	.has_rps = true,
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> @@ -461,7 +540,6 @@ static const struct intel_device_info ilk_m_info = {
>   	GEN(6), \
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> -	.display.has_hotplug = 1, \
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   	.has_3d_pipeline = 1, \
> @@ -475,24 +553,30 @@ static const struct intel_device_info ilk_m_info = {
>   	.max_pat_index = 3, \
>   	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
>   	.__runtime.ppgtt_size = 31, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	ILK_COLORS, \
>   	GEN_DEFAULT_PAGE_SIZES, \
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
>   
> +static const struct intel_display_device_info snb_display = {
> +	.has_hotplug = 1,
> +	I9XX_PIPE_OFFSETS,
> +	I9XX_CURSOR_OFFSETS,
> +	ILK_COLORS,
> +};
> +
>   #define SNB_D_PLATFORM \
>   	GEN6_FEATURES, \
>   	PLATFORM(INTEL_SANDYBRIDGE)
>   
>   static const struct intel_device_info snb_d_gt1_info = {
>   	SNB_D_PLATFORM,
> +	.display = &snb_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info snb_d_gt2_info = {
>   	SNB_D_PLATFORM,
> +	.display = &snb_display,
>   	.gt = 2,
>   };
>   
> @@ -504,11 +588,13 @@ static const struct intel_device_info snb_d_gt2_info = {
>   
>   static const struct intel_device_info snb_m_gt1_info = {
>   	SNB_M_PLATFORM,
> +	.display = &snb_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info snb_m_gt2_info = {
>   	SNB_M_PLATFORM,
> +	.display = &snb_display,
>   	.gt = 2,
>   };
>   
> @@ -516,7 +602,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>   	GEN(7), \
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> -	.display.has_hotplug = 1, \
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   	.has_3d_pipeline = 1, \
> @@ -530,9 +615,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>   	.max_pat_index = 3, \
>   	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
>   	.__runtime.ppgtt_size = 31, \
> -	IVB_PIPE_OFFSETS, \
> -	IVB_CURSOR_OFFSETS, \
> -	IVB_COLORS, \
>   	GEN_DEFAULT_PAGE_SIZES, \
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
> @@ -542,13 +624,22 @@ static const struct intel_device_info snb_m_gt2_info = {
>   	PLATFORM(INTEL_IVYBRIDGE), \
>   	.has_l3_dpf = 1
>   
> +static const struct intel_display_device_info ivb_display = {
> +	.has_hotplug = 1,
> +	IVB_PIPE_OFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +	IVB_COLORS,
> +};
> +
>   static const struct intel_device_info ivb_d_gt1_info = {
>   	IVB_D_PLATFORM,
> +	.display = &ivb_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info ivb_d_gt2_info = {
>   	IVB_D_PLATFORM,
> +	.display = &ivb_display,
>   	.gt = 2,
>   };
>   
> @@ -560,11 +651,13 @@ static const struct intel_device_info ivb_d_gt2_info = {
>   
>   static const struct intel_device_info ivb_m_gt1_info = {
>   	IVB_M_PLATFORM,
> +	.display = &ivb_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info ivb_m_gt2_info = {
>   	IVB_M_PLATFORM,
> +	.display = &ivb_display,
>   	.gt = 2,
>   };
>   
> @@ -576,18 +669,26 @@ static const struct intel_device_info ivb_q_info = {
>   	.has_l3_dpf = 1,
>   };
>   
> +static const struct intel_display_device_info vlv_display = {
> +	.has_gmch = 1,
> +	.has_hotplug = 1,
> +	.mmio_offset = VLV_DISPLAY_BASE,
> +	I9XX_PIPE_OFFSETS,
> +	I9XX_CURSOR_OFFSETS,
> +	I9XX_COLORS,
> +};
> +
>   static const struct intel_device_info vlv_info = {
>   	PLATFORM(INTEL_VALLEYVIEW),
>   	GEN(7),
>   	.is_lp = 1,
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> +	.display = &vlv_display,
>   	.has_runtime_pm = 1,
>   	.has_rc6 = 1,
>   	.has_reset_engine = true,
>   	.has_rps = true,
> -	.display.has_gmch = 1,
> -	.display.has_hotplug = 1,
>   	.dma_mask_size = 40,
>   	.max_pat_index = 3,
>   	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
> @@ -595,10 +696,6 @@ static const struct intel_device_info vlv_info = {
>   	.has_snoop = true,
>   	.has_coherent_ggtt = false,
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
> -	.display.mmio_offset = VLV_DISPLAY_BASE,
> -	I9XX_PIPE_OFFSETS,
> -	I9XX_CURSOR_OFFSETS,
> -	I9XX_COLORS,
>   	GEN_DEFAULT_PAGE_SIZES,
>   	GEN_DEFAULT_REGIONS,
>   	LEGACY_CACHELEVEL,
> @@ -609,11 +706,7 @@ static const struct intel_device_info vlv_info = {
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>   		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
> -	.display.has_ddi = 1, \
> -	.display.has_fpga_dbg = 1, \
> -	.display.has_dp_mst = 1, \
>   	.has_rc6p = 0 /* RC6p removed-by HSW */, \
> -	HSW_PIPE_OFFSETS, \
>   	.has_runtime_pm = 1
>   
>   #define HSW_PLATFORM \
> @@ -621,18 +714,31 @@ static const struct intel_device_info vlv_info = {
>   	PLATFORM(INTEL_HASWELL), \
>   	.has_l3_dpf = 1
>   
> +static const struct intel_display_device_info hsw_display = {
> +	.has_ddi = 1,
> +	.has_dp_mst = 1,
> +	.has_fpga_dbg = 1,
> +	.has_hotplug = 1,
> +	HSW_PIPE_OFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +	IVB_COLORS,
> +};
> +
>   static const struct intel_device_info hsw_gt1_info = {
>   	HSW_PLATFORM,
> +	.display = &hsw_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info hsw_gt2_info = {
>   	HSW_PLATFORM,
> +	.display = &hsw_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info hsw_gt3_info = {
>   	HSW_PLATFORM,
> +	.display = &hsw_display,
>   	.gt = 3,
>   };
>   
> @@ -645,22 +751,35 @@ static const struct intel_device_info hsw_gt3_info = {
>   	.__runtime.ppgtt_size = 48, \
>   	.has_64bit_reloc = 1
>   
> +static const struct intel_display_device_info bdw_display = {
> +	.has_ddi = 1,
> +	.has_dp_mst = 1,
> +	.has_fpga_dbg = 1,
> +	.has_hotplug = 1,
> +	HSW_PIPE_OFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +	IVB_COLORS,
> +};
> +
>   #define BDW_PLATFORM \
>   	GEN8_FEATURES, \
>   	PLATFORM(INTEL_BROADWELL)
>   
>   static const struct intel_device_info bdw_gt1_info = {
>   	BDW_PLATFORM,
> +	.display = &bdw_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info bdw_gt2_info = {
>   	BDW_PLATFORM,
> +	.display = &bdw_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info bdw_rsvd_info = {
>   	BDW_PLATFORM,
> +	.display = &bdw_display,
>   	.gt = 3,
>   	/* According to the device ID those devices are GT3, they were
>   	 * previously treated as not GT3, keep it like that.
> @@ -669,17 +788,27 @@ static const struct intel_device_info bdw_rsvd_info = {
>   
>   static const struct intel_device_info bdw_gt3_info = {
>   	BDW_PLATFORM,
> +	.display = &bdw_display,
>   	.gt = 3,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
>   };
>   
> +static const struct intel_display_device_info chv_display = {
> +	.has_hotplug = 1,
> +	.has_gmch = 1,
> +	.mmio_offset = VLV_DISPLAY_BASE,
> +	CHV_PIPE_OFFSETS,
> +	CHV_CURSOR_OFFSETS,
> +	CHV_COLORS,
> +};
> +
>   static const struct intel_device_info chv_info = {
>   	PLATFORM(INTEL_CHERRYVIEW),
>   	GEN(8),
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> -	.display.has_hotplug = 1,
> +	.display = &chv_display,
>   	.is_lp = 1,
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
>   	.has_64bit_reloc = 1,
> @@ -687,7 +816,6 @@ static const struct intel_device_info chv_info = {
>   	.has_rc6 = 1,
>   	.has_rps = true,
>   	.has_logical_ring_contexts = 1,
> -	.display.has_gmch = 1,
>   	.dma_mask_size = 39,
>   	.max_pat_index = 3,
>   	.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
> @@ -695,10 +823,6 @@ static const struct intel_device_info chv_info = {
>   	.has_reset_engine = 1,
>   	.has_snoop = true,
>   	.has_coherent_ggtt = false,
> -	.display.mmio_offset = VLV_DISPLAY_BASE,
> -	CHV_PIPE_OFFSETS,
> -	CHV_CURSOR_OFFSETS,
> -	CHV_COLORS,
>   	GEN_DEFAULT_PAGE_SIZES,
>   	GEN_DEFAULT_REGIONS,
>   	LEGACY_CACHELEVEL,
> @@ -714,12 +838,22 @@ static const struct intel_device_info chv_info = {
>   	GEN9_DEFAULT_PAGE_SIZES, \
>   	.__runtime.has_dmc = 1, \
>   	.has_gt_uc = 1, \
> -	.__runtime.has_hdcp = 1, \
> -	.display.has_ipc = 1, \
> -	.display.has_psr = 1, \
> -	.display.has_psr_hw_tracking = 1, \
> -	.display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> -	.display.dbuf.slice_mask = BIT(DBUF_S1)
> +	.__runtime.has_hdcp = 1
> +
> +static const struct intel_display_device_info skl_display = {
> +	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> +	.dbuf.slice_mask = BIT(DBUF_S1),
> +	.has_ddi = 1,
> +	.has_dp_mst = 1,
> +	.has_fpga_dbg = 1,
> +	.has_hotplug = 1,
> +	.has_ipc = 1,
> +	.has_psr = 1,
> +	.has_psr_hw_tracking = 1,
> +	HSW_PIPE_OFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +	IVB_COLORS,
> +};
>   
>   #define SKL_PLATFORM \
>   	GEN9_FEATURES, \
> @@ -727,11 +861,13 @@ static const struct intel_device_info chv_info = {
>   
>   static const struct intel_device_info skl_gt1_info = {
>   	SKL_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info skl_gt2_info = {
>   	SKL_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 2,
>   };
>   
> @@ -743,19 +879,19 @@ static const struct intel_device_info skl_gt2_info = {
>   
>   static const struct intel_device_info skl_gt3_info = {
>   	SKL_GT3_PLUS_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 3,
>   };
>   
>   static const struct intel_device_info skl_gt4_info = {
>   	SKL_GT3_PLUS_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 4,
>   };
>   
>   #define GEN9_LP_FEATURES \
>   	GEN(9), \
>   	.is_lp = 1, \
> -	.display.dbuf.slice_mask = BIT(DBUF_S1), \
> -	.display.has_hotplug = 1, \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> @@ -763,17 +899,12 @@ static const struct intel_device_info skl_gt4_info = {
>   		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
>   	.has_3d_pipeline = 1, \
>   	.has_64bit_reloc = 1, \
> -	.display.has_ddi = 1, \
> -	.display.has_fpga_dbg = 1, \
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
>   	.__runtime.has_hdcp = 1, \
> -	.display.has_psr = 1, \
> -	.display.has_psr_hw_tracking = 1, \
>   	.has_runtime_pm = 1, \
>   	.__runtime.has_dmc = 1, \
>   	.has_rc6 = 1, \
>   	.has_rps = true, \
> -	.display.has_dp_mst = 1, \
>   	.has_logical_ring_contexts = 1, \
>   	.has_gt_uc = 1, \
>   	.dma_mask_size = 39, \
> @@ -782,27 +913,46 @@ static const struct intel_device_info skl_gt4_info = {
>   	.has_reset_engine = 1, \
>   	.has_snoop = true, \
>   	.has_coherent_ggtt = false, \
> -	.display.has_ipc = 1, \
>   	.max_pat_index = 3, \
> -	HSW_PIPE_OFFSETS, \
> -	IVB_CURSOR_OFFSETS, \
> -	IVB_COLORS, \
>   	GEN9_DEFAULT_PAGE_SIZES, \
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
>   
> +#define GEN9_LP_DISPLAY \
> +	.dbuf.slice_mask = BIT(DBUF_S1), \
> +	.has_dp_mst = 1, \
> +	.has_ddi = 1, \
> +	.has_fpga_dbg = 1, \
> +	.has_hotplug = 1, \
> +	.has_ipc = 1, \
> +	.has_psr = 1, \
> +	.has_psr_hw_tracking = 1, \
> +	HSW_PIPE_OFFSETS, \
> +	IVB_CURSOR_OFFSETS, \
> +	IVB_COLORS
> +
> +static const struct intel_display_device_info bxt_display = {
> +	GEN9_LP_DISPLAY,
> +	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> +};
> +
>   static const struct intel_device_info bxt_info = {
>   	GEN9_LP_FEATURES,
>   	PLATFORM(INTEL_BROXTON),
> -	.display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> +	.display = &bxt_display,
> +};
> +
> +static const struct intel_display_device_info glk_display = {
> +	GEN9_LP_DISPLAY,
> +	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> +	GLK_COLORS,
>   };
>   
>   static const struct intel_device_info glk_info = {
>   	GEN9_LP_FEATURES,
>   	PLATFORM(INTEL_GEMINILAKE),
>   	.__runtime.display.ip.ver = 10,
> -	.display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> -	GLK_COLORS,
> +	.display = &glk_display,
>   };
>   
>   #define KBL_PLATFORM \
> @@ -811,16 +961,19 @@ static const struct intel_device_info glk_info = {
>   
>   static const struct intel_device_info kbl_gt1_info = {
>   	KBL_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info kbl_gt2_info = {
>   	KBL_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info kbl_gt3_info = {
>   	KBL_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 3,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> @@ -832,16 +985,19 @@ static const struct intel_device_info kbl_gt3_info = {
>   
>   static const struct intel_device_info cfl_gt1_info = {
>   	CFL_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info cfl_gt2_info = {
>   	CFL_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info cfl_gt3_info = {
>   	CFL_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 3,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> @@ -853,11 +1009,13 @@ static const struct intel_device_info cfl_gt3_info = {
>   
>   static const struct intel_device_info cml_gt1_info = {
>   	CML_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info cml_gt2_info = {
>   	CML_PLATFORM,
> +	.display = &skl_display,
>   	.gt = 2,
>   };
>   
> @@ -869,39 +1027,51 @@ static const struct intel_device_info cml_gt2_info = {
>   #define GEN11_FEATURES \
>   	GEN9_FEATURES, \
>   	GEN11_DEFAULT_PAGE_SIZES, \
> -	.display.abox_mask = BIT(0), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>   		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
>   		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> -	.display.pipe_offsets = { \
> -		[TRANSCODER_A] = PIPE_A_OFFSET, \
> -		[TRANSCODER_B] = PIPE_B_OFFSET, \
> -		[TRANSCODER_C] = PIPE_C_OFFSET, \
> -		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> -		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> -		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> -	}, \
> -	.display.trans_offsets = { \
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> -		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> -		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> -		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> -		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> -		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> -	}, \
>   	GEN(11), \
> -	ICL_COLORS, \
> -	.display.dbuf.size = 2048, \
> -	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
>   	.__runtime.has_dsc = 1, \
>   	.has_coherent_ggtt = false, \
>   	.has_logical_ring_elsq = 1
>   
> +static const struct intel_display_device_info gen11_display = {
> +	.abox_mask = BIT(0),
> +	.dbuf.size = 2048,
> +	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
> +	.has_ddi = 1,
> +	.has_dp_mst = 1,
> +	.has_fpga_dbg = 1,
> +	.has_hotplug = 1,
> +	.has_ipc = 1,
> +	.has_psr = 1,
> +	.has_psr_hw_tracking = 1,
> +	.pipe_offsets = {
> +		[TRANSCODER_A] = PIPE_A_OFFSET,
> +		[TRANSCODER_B] = PIPE_B_OFFSET,
> +		[TRANSCODER_C] = PIPE_C_OFFSET,
> +		[TRANSCODER_EDP] = PIPE_EDP_OFFSET,
> +		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> +		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> +	},
> +	.trans_offsets = {
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
> +		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
> +		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
> +		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> +		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> +	},
> +	IVB_CURSOR_OFFSETS,
> +	ICL_COLORS,
> +};
> +
>   static const struct intel_device_info icl_info = {
>   	GEN11_FEATURES,
>   	PLATFORM(INTEL_ICELAKE),
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> +	.display = &gen11_display,
>   };
>   
>   static const struct intel_device_info ehl_info = {
> @@ -909,6 +1079,7 @@ static const struct intel_device_info ehl_info = {
>   	PLATFORM(INTEL_ELKHARTLAKE),
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>   	.__runtime.ppgtt_size = 36,
> +	.display = &gen11_display,
>   };
>   
>   static const struct intel_device_info jsl_info = {
> @@ -916,17 +1087,34 @@ static const struct intel_device_info jsl_info = {
>   	PLATFORM(INTEL_JASPERLAKE),
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>   	.__runtime.ppgtt_size = 36,
> +	.display = &gen11_display,
>   };
>   
>   #define GEN12_FEATURES \
>   	GEN11_FEATURES, \
>   	GEN(12), \
> -	.display.abox_mask = GENMASK(2, 1), \
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>   		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
>   		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> -	.display.pipe_offsets = { \
> +	TGL_CACHELEVEL, \
> +	.has_global_mocs = 1, \
> +	.has_pxp = 1, \
> +	.max_pat_index = 3
> +
> +#define XE_D_DISPLAY \
> +	.abox_mask = GENMASK(2, 1), \
> +	.dbuf.size = 2048, \
> +	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> +	.has_ddi = 1, \
> +	.has_dp_mst = 1, \
> +	.has_dsb = 1, \
> +	.has_fpga_dbg = 1, \
> +	.has_hotplug = 1, \
> +	.has_ipc = 1, \
> +	.has_psr = 1, \
> +	.has_psr_hw_tracking = 1, \
> +	.pipe_offsets = { \
>   		[TRANSCODER_A] = PIPE_A_OFFSET, \
>   		[TRANSCODER_B] = PIPE_B_OFFSET, \
>   		[TRANSCODER_C] = PIPE_C_OFFSET, \
> @@ -934,7 +1122,7 @@ static const struct intel_device_info jsl_info = {
>   		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
>   		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
>   	}, \
> -	.display.trans_offsets = { \
> +	.trans_offsets = { \
>   		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>   		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
>   		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> @@ -943,30 +1131,36 @@ static const struct intel_device_info jsl_info = {
>   		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
>   	}, \
>   	TGL_CURSOR_OFFSETS, \
> -	TGL_CACHELEVEL, \
> -	.has_global_mocs = 1, \
> -	.has_pxp = 1, \
> -	.display.has_dsb = 1, \
> -	.max_pat_index = 3
> +	ICL_COLORS
> +
> +static const struct intel_display_device_info tgl_display = {
> +	XE_D_DISPLAY,
> +};
>   
>   static const struct intel_device_info tgl_info = {
>   	GEN12_FEATURES,
>   	PLATFORM(INTEL_TIGERLAKE),
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> +	.display = &tgl_display,
> +};
> +
> +static const struct intel_display_device_info rkl_display = {
> +	XE_D_DISPLAY,
> +	.abox_mask = BIT(0),
> +	.has_hti = 1,
> +	.has_psr_hw_tracking = 0,
>   };
>   
>   static const struct intel_device_info rkl_info = {
>   	GEN12_FEATURES,
>   	PLATFORM(INTEL_ROCKETLAKE),
> -	.display.abox_mask = BIT(0),
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>   		BIT(TRANSCODER_C),
> -	.display.has_hti = 1,
> -	.display.has_psr_hw_tracking = 0,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
> +	.display = &rkl_display,
>   };
>   
>   #define DGFX_FEATURES \
> @@ -989,43 +1183,43 @@ static const struct intel_device_info dg1_info = {
>   		BIT(VCS0) | BIT(VCS2),
>   	/* Wa_16011227922 */
>   	.__runtime.ppgtt_size = 47,
> +	.display = &tgl_display,
> +};
> +
> +static const struct intel_display_device_info adl_s_display = {
> +	XE_D_DISPLAY,
> +	.has_hti = 1,
> +	.has_psr_hw_tracking = 0,
>   };
>   
>   static const struct intel_device_info adl_s_info = {
>   	GEN12_FEATURES,
>   	PLATFORM(INTEL_ALDERLAKE_S),
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> -	.display.has_hti = 1,
> -	.display.has_psr_hw_tracking = 0,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>   	.dma_mask_size = 39,
> +	.display = &adl_s_display,
>   };
>   
>   #define XE_LPD_FEATURES \
> -	.display.abox_mask = GENMASK(1, 0),					\
> -	.display.color = {							\
> +	.abox_mask = GENMASK(1, 0),						\
> +	.color = {								\
>   		.degamma_lut_size = 129, .gamma_lut_size = 1024,		\
>   		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
> -				     DRM_COLOR_LUT_EQUAL_CHANNELS,		\
> +		DRM_COLOR_LUT_EQUAL_CHANNELS,					\
>   	},									\
> -	.display.dbuf.size = 4096,						\
> -	.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |	\
> +	.dbuf.size = 4096,							\
> +	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
>   		BIT(DBUF_S4),							\
> -	.display.has_ddi = 1,							\
> -	.__runtime.has_dmc = 1,							\
> -	.display.has_dp_mst = 1,						\
> -	.display.has_dsb = 1,							\
> -	.__runtime.has_dsc = 1,							\
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
> -	.display.has_fpga_dbg = 1,						\
> -	.__runtime.has_hdcp = 1,						\
> -	.display.has_hotplug = 1,						\
> -	.display.has_ipc = 1,							\
> -	.display.has_psr = 1,							\
> -	.__runtime.display.ip.ver = 13,							\
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\
> -	.display.pipe_offsets = {						\
> +	.has_ddi = 1,								\
> +	.has_dp_mst = 1,							\
> +	.has_dsb = 1,								\
> +	.has_fpga_dbg = 1,							\
> +	.has_hotplug = 1,							\
> +	.has_ipc = 1,								\
> +	.has_psr = 1,								\
> +	.pipe_offsets = {							\
>   		[TRANSCODER_A] = PIPE_A_OFFSET,					\
>   		[TRANSCODER_B] = PIPE_B_OFFSET,					\
>   		[TRANSCODER_C] = PIPE_C_OFFSET,					\
> @@ -1033,7 +1227,7 @@ static const struct intel_device_info adl_s_info = {
>   		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
>   		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
>   	},									\
> -	.display.trans_offsets = {						\
> +	.trans_offsets = {						\
>   		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
>   		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
>   		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
> @@ -1043,18 +1237,31 @@ static const struct intel_device_info adl_s_info = {
>   	},									\
>   	TGL_CURSOR_OFFSETS
>   
> +#define XE_LPD_RUNTIME \
> +	.__runtime.has_dmc = 1,							\
> +	.__runtime.has_dsc = 1,							\
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
> +	.__runtime.has_hdcp = 1,						\
> +	.__runtime.display.ip.ver = 13,							\
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
> +
> +static const struct intel_display_device_info xe_lpd_display = {
> +	XE_LPD_FEATURES,
> +	.has_cdclk_crawl = 1,
> +	.has_psr_hw_tracking = 0,
> +};
> +
>   static const struct intel_device_info adl_p_info = {
>   	GEN12_FEATURES,
> -	XE_LPD_FEATURES,
> +	XE_LPD_RUNTIME,
>   	PLATFORM(INTEL_ALDERLAKE_P),
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>   			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
>   			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> -	.display.has_cdclk_crawl = 1,
> -	.display.has_psr_hw_tracking = 0,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>   	.__runtime.ppgtt_size = 48,
> +	.display = &xe_lpd_display,
>   	.dma_mask_size = 39,
>   };
>   
> @@ -1125,18 +1332,23 @@ static const struct intel_device_info xehpsdv_info = {
>   	.has_guc_deprivilege = 1, \
>   	.has_heci_pxp = 1, \
>   	.has_media_ratio_mode = 1, \
> -	.display.has_cdclk_squash = 1, \
>   	.__runtime.platform_engine_mask = \
>   		BIT(RCS0) | BIT(BCS0) | \
>   		BIT(VECS0) | BIT(VECS1) | \
>   		BIT(VCS0) | BIT(VCS2) | \
>   		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
>   
> +static const struct intel_display_device_info xe_hpd_display = {
> +	XE_LPD_FEATURES,
> +	.has_cdclk_squash = 1,
> +};
> +
>   static const struct intel_device_info dg2_info = {
>   	DG2_FEATURES,
> -	XE_LPD_FEATURES,
> +	XE_LPD_RUNTIME,
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>   			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +	.display = &xe_hpd_display,
>   };
>   
>   static const struct intel_device_info ats_m_info = {
> @@ -1174,11 +1386,9 @@ static const struct intel_device_info pvc_info = {
>   	PVC_CACHELEVEL,
>   };
>   
> -#define XE_LPDP_FEATURES	\
> -	XE_LPD_FEATURES,	\
> +#define XE_LPDP_RUNTIME	\
> +	XE_LPD_RUNTIME,	\
>   	.__runtime.display.ip.ver = 14,	\
> -	.display.has_cdclk_crawl = 1, \
> -	.display.has_cdclk_squash = 1, \
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
>   
>   static const struct intel_gt_definition xelpmp_extra_gt[] = {
> @@ -1191,9 +1401,15 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
>   	{}
>   };
>   
> +static const struct intel_display_device_info xe_lpdp_display = {
> +	XE_LPD_FEATURES,
> +	.has_cdclk_crawl = 1,
> +	.has_cdclk_squash = 1,
> +};
> +
>   static const struct intel_device_info mtl_info = {
>   	XE_HP_FEATURES,
> -	XE_LPDP_FEATURES,
> +	XE_LPDP_RUNTIME,
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>   			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>   	/*
> @@ -1204,6 +1420,7 @@ static const struct intel_device_info mtl_info = {
>   	.__runtime.graphics.ip.rel = 70,
>   	.__runtime.media.ip.ver = 13,
>   	PLATFORM(INTEL_METEORLAKE),
> +	.display = &xe_lpdp_display,
>   	.extra_gt_list = xelpmp_extra_gt,
>   	.has_flat_ccs = 0,
>   	.has_gmd_id = 1,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 4e23be2995bf..d0bf626d0360 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -138,7 +138,7 @@ void intel_device_info_print(const struct intel_device_info *info,
>   
>   	drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
>   
> -#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
> +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
>   	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
>   #undef PRINT_FLAG
>   
> @@ -388,6 +388,8 @@ mkwrite_device_info(struct drm_i915_private *i915)
>   	return (struct intel_device_info *)INTEL_INFO(i915);
>   }
>   
> +static const struct intel_display_device_info no_display = { 0 };
> +
>   /**
>    * intel_device_info_runtime_init - initialize runtime info
>    * @dev_priv: the i915 device
> @@ -538,7 +540,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   	if (!HAS_DISPLAY(dev_priv)) {
>   		dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
>   						   DRIVER_ATOMIC);
> -		memset(&info->display, 0, sizeof(info->display));
> +		info->display = &no_display;
>   
>   		runtime->cpu_transcoder_mask = 0;
>   		memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 96f6bdb04b1b..f212e02e6582 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -259,7 +259,7 @@ struct intel_device_info {
>   	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
>   #undef DEFINE_FLAG
>   
> -	struct intel_display_device_info display;
> +	const struct intel_display_device_info *display;
>   
>   	/*
>   	 * Initial runtime info. Do not access outside of i915_driver_create().


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH 3/5] drm/i915/display: Move display runtime info to display structure
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header " Matt Roper
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
@ 2023-05-18  3:18 ` Matt Roper
  2023-05-18  7:56   ` Andrzej Hajda
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 4/5] drm/i915/display: Make display responsible for probing its own IP Matt Roper
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Matt Roper @ 2023-05-18  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Matt Roper, intel-xe

Move the runtime info specific to display into display-specific
structures as has already been done with the constant display info.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_cursor.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   8 +-
 .../drm/i915/display/intel_display_device.h   |  23 ++
 drivers/gpu/drm/i915/display/intel_fbc.c      |   6 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   2 +-
 .../drm/i915/display/skl_universal_plane.c    |   2 +-
 drivers/gpu/drm/i915/i915_drv.h               |  17 +-
 drivers/gpu/drm/i915/i915_pci.c               | 221 +++++++++++-------
 drivers/gpu/drm/i915/intel_device_info.c      | 101 ++++----
 drivers/gpu/drm/i915/intel_device_info.h      |  18 --
 drivers/gpu/drm/i915/intel_step.c             |   8 +-
 13 files changed, 245 insertions(+), 167 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 93c3226b98c9..182c6dd64f47 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -306,7 +306,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 		return PTR_ERR(crtc);
 
 	crtc->pipe = pipe;
-	crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
+	crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
 
 	if (DISPLAY_VER(dev_priv) >= 9)
 		primary = skl_universal_plane_create(dev_priv, pipe,
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index dd2def27add9..093fc881ddc1 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -814,7 +814,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
 						   DRM_MODE_ROTATE_0 |
 						   DRM_MODE_ROTATE_180);
 
-	zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
+	zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
 	drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
 
 	if (DISPLAY_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 09320e14d75c..f1130e2c3542 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3366,7 +3366,7 @@ static u8 bigjoiner_pipes(struct drm_i915_private *i915)
 	else
 		pipes = 0;
 
-	return pipes & RUNTIME_INFO(i915)->pipe_mask;
+	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
 }
 
 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index aa3a21ccd7fe..c744c021af23 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -105,7 +105,7 @@ enum i9xx_plane_id {
 };
 
 #define plane_name(p) ((p) + 'A')
-#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
+#define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 
 #define for_each_plane_id_on_crtc(__crtc, __p) \
 	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
@@ -221,7 +221,7 @@ enum phy_fia {
 
 #define for_each_pipe(__dev_priv, __p) \
 	for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
-		for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
+		for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
 
 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 	for_each_pipe(__dev_priv, __p) \
@@ -229,7 +229,7 @@ enum phy_fia {
 
 #define for_each_cpu_transcoder(__dev_priv, __t) \
 	for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)	\
-		for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
+		for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
 
 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 	for_each_cpu_transcoder(__dev_priv, __t) \
@@ -237,7 +237,7 @@ enum phy_fia {
 
 #define for_each_sprite(__dev_priv, __p, __s)				\
 	for ((__s) = 0;							\
-	     (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];	\
+	     (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];	\
 	     (__s)++)
 
 #define for_each_port(__port) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index c689d582dbf1..241f39b13f2f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -29,7 +29,30 @@
 	func(overlay_needs_physical); \
 	func(supports_tv);
 
+struct intel_display_runtime_info {
+	struct {
+		u16 ver;
+		u16 rel;
+		u16 step;
+	} ip;
+
+	u8 pipe_mask;
+	u8 cpu_transcoder_mask;
+
+	u8 num_sprites[I915_MAX_PIPES];
+	u8 num_scalers[I915_MAX_PIPES];
+
+	u8 fbc_mask;
+
+	bool has_hdcp;
+	bool has_dmc;
+	bool has_dsc;
+};
+
 struct intel_display_device_info {
+	/* Initial runtime info. */
+	const struct intel_display_runtime_info __runtime;
+
 	u8 abox_mask;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 11bb8cf9c9d0..1966f9396201 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -56,7 +56,7 @@
 
 #define for_each_fbc_id(__dev_priv, __fbc_id) \
 	for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
-		for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
+		for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
 
 #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
 	for_each_fbc_id((__dev_priv), (__fbc_id)) \
@@ -1708,10 +1708,10 @@ void intel_fbc_init(struct drm_i915_private *i915)
 	enum intel_fbc_id fbc_id;
 
 	if (!drm_mm_initialized(&i915->mm.stolen))
-		RUNTIME_INFO(i915)->fbc_mask = 0;
+		DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
 
 	if (need_fbc_vtd_wa(i915))
-		RUNTIME_INFO(i915)->fbc_mask = 0;
+		DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
 
 	i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
 	drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index dd539106ee5a..1f96d1fa68e0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1103,7 +1103,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
 
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 {
-	return RUNTIME_INFO(dev_priv)->has_hdcp &&
+	return DISPLAY_RUNTIME_INFO(dev_priv)->has_hdcp &&
 		(DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
 }
 
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 110401aab038..36070d86550f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1944,7 +1944,7 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
 			      enum intel_fbc_id fbc_id, enum plane_id plane_id)
 {
-	if ((RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
+	if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
 		return false;
 
 	return plane_id == PLANE_PRIMARY;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 116fc4441f8b..d312314b212e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -205,6 +205,7 @@ struct drm_i915_private {
 
 	const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 	struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
+	struct intel_display_runtime_info __display_runtime; /* Access with DISPLAY_RUNTIME_INFO() */
 	struct intel_driver_caps caps;
 
 	struct i915_dsm dsm;
@@ -408,7 +409,9 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 
 #define INTEL_INFO(i915)	(&(i915)->__info)
+#define DISPLAY_INFO(i915)	(INTEL_INFO(i915)->display)
 #define RUNTIME_INFO(i915)	(&(i915)->__runtime)
+#define DISPLAY_RUNTIME_INFO(i915)	(&(i915)->__display_runtime)
 #define DRIVER_CAPS(i915)	(&(i915)->caps)
 
 #define INTEL_DEVID(i915)	(RUNTIME_INFO(i915)->device_id)
@@ -427,7 +430,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 #define IS_MEDIA_VER(i915, from, until) \
 	(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 
-#define DISPLAY_VER(i915)	(RUNTIME_INFO(i915)->display.ip.ver)
+#define DISPLAY_VER(i915)	(DISPLAY_RUNTIME_INFO(i915)->ip.ver)
 #define IS_DISPLAY_VER(i915, from, until) \
 	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 
@@ -810,7 +813,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display->has_hotplug)
 
 #define HAS_FW_BLC(i915)	(DISPLAY_VER(i915) > 2)
-#define HAS_FBC(i915)	(RUNTIME_INFO(i915)->fbc_mask != 0)
+#define HAS_FBC(i915)	(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
 #define HAS_CUR_FBC(i915)	(!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
 
 #define HAS_DPT(i915)	(DISPLAY_VER(i915) >= 13)
@@ -830,7 +833,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_PSR_HW_TRACKING(i915) \
 	(INTEL_INFO(i915)->display->has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(i915)	 (DISPLAY_VER(i915) >= 12)
-#define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
+#define HAS_TRANSCODER(i915, trans)	 ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
 
 #define HAS_RC6(i915)		 (INTEL_INFO(i915)->has_rc6)
 #define HAS_RC6p(i915)		 (INTEL_INFO(i915)->has_rc6p)
@@ -838,9 +841,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_RPS(i915)	(INTEL_INFO(i915)->has_rps)
 
-#define HAS_DMC(i915)	(RUNTIME_INFO(i915)->has_dmc)
+#define HAS_DMC(i915)	(DISPLAY_RUNTIME_INFO(i915)->has_dmc)
 #define HAS_DSB(i915)	(INTEL_INFO(i915)->display->has_dsb)
-#define HAS_DSC(__i915)		(RUNTIME_INFO(__i915)->has_dsc)
+#define HAS_DSC(__i915)		(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 
 #define HAS_HECI_PXP(i915) \
@@ -902,9 +905,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
 				 2 : HAS_L3_DPF(i915))
 
-#define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask))
+#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
 
-#define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0)
+#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
 
 #define HAS_VRR(i915)	(DISPLAY_VER(i915) >= 11)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index dd874a4db604..8b19df1294de 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -41,10 +41,11 @@
 #define PLATFORM(x) .platform = (x)
 #define GEN(x) \
 	.__runtime.graphics.ip.ver = (x), \
-	.__runtime.media.ip.ver = (x), \
-	.__runtime.display.ip.ver = (x)
+	.__runtime.media.ip.ver = (x)
 
-#define NO_DISPLAY .__runtime.pipe_mask = 0
+static const struct intel_display_device_info no_display = { 0 };
+
+#define NO_DISPLAY .display = &no_display
 
 #define I845_PIPE_OFFSETS \
 	.pipe_offsets = { \
@@ -212,7 +213,11 @@
 	.has_gmch = 1, \
 	I9XX_PIPE_OFFSETS, \
 	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS
+	I9XX_COLORS, \
+	\
+	.__runtime.ip.ver = 2, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
 
 static const struct intel_display_device_info i830_display = {
 	I830_DISPLAY,
@@ -221,8 +226,6 @@ static const struct intel_display_device_info i830_display = {
 #define I830_FEATURES \
 	GEN(2), \
 	.is_mobile = 1, \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 	.gpu_reset_clobbers_display = true, \
 	.has_3d_pipeline = 1, \
 	.hws_needs_physical = 1, \
@@ -242,7 +245,11 @@ static const struct intel_display_device_info i830_display = {
 	.has_gmch = 1, \
 	I845_PIPE_OFFSETS, \
 	I845_CURSOR_OFFSETS, \
-	I845_COLORS
+	I845_COLORS, \
+	\
+	.__runtime.ip.ver = 2, \
+	.__runtime.pipe_mask = BIT(PIPE_A), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A)
 
 static const struct intel_display_device_info i845_display = {
 	I845_DISPLAY,
@@ -250,8 +257,6 @@ static const struct intel_display_device_info i845_display = {
 
 #define I845_FEATURES \
 	GEN(2), \
-	.__runtime.pipe_mask = BIT(PIPE_A), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
 	.has_3d_pipeline = 1, \
 	.gpu_reset_clobbers_display = true, \
 	.hws_needs_physical = 1, \
@@ -279,24 +284,26 @@ static const struct intel_device_info i845g_info = {
 
 static const struct intel_display_device_info i85x_display = {
 	I830_DISPLAY,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info i85x_info = {
 	I830_FEATURES,
 	PLATFORM(INTEL_I85X),
 	.display = &i85x_display,
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_display_device_info i865g_display = {
 	I845_DISPLAY,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info i865g_info = {
 	I845_FEATURES,
 	PLATFORM(INTEL_I865G),
 	.display = &i865g_display,
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 #define GEN3_DISPLAY \
@@ -304,7 +311,11 @@ static const struct intel_device_info i865g_info = {
 	.has_overlay = 1, \
 	I9XX_PIPE_OFFSETS, \
 	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS
+	I9XX_COLORS, \
+	\
+	.__runtime.ip.ver = 3, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
 
 static const struct intel_display_device_info i915g_display = {
 	GEN3_DISPLAY,
@@ -317,6 +328,8 @@ static const struct intel_display_device_info i915gm_display = {
 	.cursor_needs_physical = 1,
 	.overlay_needs_physical = 1,
 	.supports_tv = 1,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_display_device_info i945g_display = {
@@ -332,6 +345,8 @@ static const struct intel_display_device_info i945gm_display = {
 	.cursor_needs_physical = 1,
 	.overlay_needs_physical = 1,
 	.supports_tv = 1,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_display_device_info g33_display = {
@@ -341,8 +356,6 @@ static const struct intel_display_device_info g33_display = {
 
 #define GEN3_FEATURES \
 	GEN(3), \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 	.gpu_reset_clobbers_display = true, \
 	.__runtime.platform_engine_mask = BIT(RCS0), \
 	.has_3d_pipeline = 1, \
@@ -368,7 +381,6 @@ static const struct intel_device_info i915gm_info = {
 	PLATFORM(INTEL_I915GM),
 	.display = &i915gm_display,
 	.is_mobile = 1,
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
@@ -386,7 +398,6 @@ static const struct intel_device_info i945gm_info = {
 	PLATFORM(INTEL_I945GM),
 	.display = &i945gm_display,
 	.is_mobile = 1,
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
@@ -418,7 +429,11 @@ static const struct intel_device_info pnv_m_info = {
 	.has_gmch = 1, \
 	I9XX_PIPE_OFFSETS, \
 	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS
+	I9XX_COLORS, \
+	\
+	.__runtime.ip.ver = 4, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
 
 static const struct intel_display_device_info i965g_display = {
 	GEN4_DISPLAY,
@@ -429,6 +444,8 @@ static const struct intel_display_device_info i965gm_display = {
 	GEN4_DISPLAY,
 	.has_overlay = 1,
 	.supports_tv = 1,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_display_device_info g45_display = {
@@ -438,12 +455,12 @@ static const struct intel_display_device_info g45_display = {
 static const struct intel_display_device_info gm45_display = {
 	GEN4_DISPLAY,
 	.supports_tv = 1,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 #define GEN4_FEATURES \
 	GEN(4), \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 	.gpu_reset_clobbers_display = true, \
 	.__runtime.platform_engine_mask = BIT(RCS0), \
 	.has_3d_pipeline = 1, \
@@ -468,7 +485,6 @@ static const struct intel_device_info i965gm_info = {
 	PLATFORM(INTEL_I965GM),
 	.display = &i965gm_display,
 	.is_mobile = 1,
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 	.hws_needs_physical = 1,
 	.has_snoop = false,
 };
@@ -485,7 +501,6 @@ static const struct intel_device_info gm45_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_GM45),
 	.is_mobile = 1,
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 	.display = &gm45_display,
 	.gpu_reset_clobbers_display = false,
@@ -493,8 +508,6 @@ static const struct intel_device_info gm45_info = {
 
 #define GEN5_FEATURES \
 	GEN(5), \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 	.has_3d_pipeline = 1, \
 	.has_snoop = true, \
@@ -511,7 +524,11 @@ static const struct intel_device_info gm45_info = {
 	.has_hotplug = 1, \
 	I9XX_PIPE_OFFSETS, \
 	I9XX_CURSOR_OFFSETS, \
-	ILK_COLORS
+	ILK_COLORS, \
+	\
+	.__runtime.ip.ver = 5, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
 
 static const struct intel_display_device_info ilk_d_display = {
 	ILK_DISPLAY,
@@ -525,6 +542,8 @@ static const struct intel_device_info ilk_d_info = {
 
 static const struct intel_display_device_info ilk_m_display = {
 	ILK_DISPLAY,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info ilk_m_info = {
@@ -533,14 +552,10 @@ static const struct intel_device_info ilk_m_info = {
 	.display = &ilk_m_display,
 	.is_mobile = 1,
 	.has_rps = true,
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 #define GEN6_FEATURES \
 	GEN(6), \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 	.has_3d_pipeline = 1, \
 	.has_coherent_ggtt = true, \
@@ -562,6 +577,11 @@ static const struct intel_display_device_info snb_display = {
 	I9XX_PIPE_OFFSETS,
 	I9XX_CURSOR_OFFSETS,
 	ILK_COLORS,
+
+	.__runtime.ip.ver = 6,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 #define SNB_D_PLATFORM \
@@ -600,9 +620,6 @@ static const struct intel_device_info snb_m_gt2_info = {
 
 #define GEN7_FEATURES  \
 	GEN(7), \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 	.has_3d_pipeline = 1, \
 	.has_coherent_ggtt = true, \
@@ -629,6 +646,12 @@ static const struct intel_display_device_info ivb_display = {
 	IVB_PIPE_OFFSETS,
 	IVB_CURSOR_OFFSETS,
 	IVB_COLORS,
+
+	.__runtime.ip.ver = 7,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info ivb_d_gt1_info = {
@@ -676,14 +699,16 @@ static const struct intel_display_device_info vlv_display = {
 	I9XX_PIPE_OFFSETS,
 	I9XX_CURSOR_OFFSETS,
 	I9XX_COLORS,
+
+	.__runtime.ip.ver = 7,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 };
 
 static const struct intel_device_info vlv_info = {
 	PLATFORM(INTEL_VALLEYVIEW),
 	GEN(7),
 	.is_lp = 1,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 	.display = &vlv_display,
 	.has_runtime_pm = 1,
 	.has_rc6 = 1,
@@ -704,8 +729,6 @@ static const struct intel_device_info vlv_info = {
 #define G75_FEATURES  \
 	GEN7_FEATURES, \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
 	.has_runtime_pm = 1
 
@@ -722,6 +745,12 @@ static const struct intel_display_device_info hsw_display = {
 	HSW_PIPE_OFFSETS,
 	IVB_CURSOR_OFFSETS,
 	IVB_COLORS,
+
+	.__runtime.ip.ver = 7,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info hsw_gt1_info = {
@@ -759,6 +788,12 @@ static const struct intel_display_device_info bdw_display = {
 	HSW_PIPE_OFFSETS,
 	IVB_CURSOR_OFFSETS,
 	IVB_COLORS,
+
+	.__runtime.ip.ver = 8,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 #define BDW_PLATFORM \
@@ -801,13 +836,16 @@ static const struct intel_display_device_info chv_display = {
 	CHV_PIPE_OFFSETS,
 	CHV_CURSOR_OFFSETS,
 	CHV_COLORS,
+
+	.__runtime.ip.ver = 8,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C),
 };
 
 static const struct intel_device_info chv_info = {
 	PLATFORM(INTEL_CHERRYVIEW),
 	GEN(8),
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 	.display = &chv_display,
 	.is_lp = 1,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
@@ -836,9 +874,7 @@ static const struct intel_device_info chv_info = {
 	GEN8_FEATURES, \
 	GEN(9), \
 	GEN9_DEFAULT_PAGE_SIZES, \
-	.__runtime.has_dmc = 1, \
-	.has_gt_uc = 1, \
-	.__runtime.has_hdcp = 1
+	.has_gt_uc = 1
 
 static const struct intel_display_device_info skl_display = {
 	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
@@ -853,6 +889,14 @@ static const struct intel_display_device_info skl_display = {
 	HSW_PIPE_OFFSETS,
 	IVB_CURSOR_OFFSETS,
 	IVB_COLORS,
+
+	.__runtime.ip.ver = 9,
+	.__runtime.has_dmc = 1,
+	.__runtime.has_hdcp = 1,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 #define SKL_PLATFORM \
@@ -893,16 +937,9 @@ static const struct intel_device_info skl_gt4_info = {
 	GEN(9), \
 	.is_lp = 1, \
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
-		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 	.has_3d_pipeline = 1, \
 	.has_64bit_reloc = 1, \
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
-	.__runtime.has_hdcp = 1, \
 	.has_runtime_pm = 1, \
-	.__runtime.has_dmc = 1, \
 	.has_rc6 = 1, \
 	.has_rps = true, \
 	.has_logical_ring_contexts = 1, \
@@ -929,11 +966,21 @@ static const struct intel_device_info skl_gt4_info = {
 	.has_psr_hw_tracking = 1, \
 	HSW_PIPE_OFFSETS, \
 	IVB_CURSOR_OFFSETS, \
-	IVB_COLORS
+	IVB_COLORS, \
+	\
+	.__runtime.has_dmc = 1, \
+	.__runtime.has_hdcp = 1, \
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
+		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
 
 static const struct intel_display_device_info bxt_display = {
 	GEN9_LP_DISPLAY,
 	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+
+	.__runtime.ip.ver = 9,
 };
 
 static const struct intel_device_info bxt_info = {
@@ -946,12 +993,13 @@ static const struct intel_display_device_info glk_display = {
 	GEN9_LP_DISPLAY,
 	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 	GLK_COLORS,
+
+	.__runtime.ip.ver = 10,
 };
 
 static const struct intel_device_info glk_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
-	.__runtime.display.ip.ver = 10,
 	.display = &glk_display,
 };
 
@@ -1027,11 +1075,7 @@ static const struct intel_device_info cml_gt2_info = {
 #define GEN11_FEATURES \
 	GEN9_FEATURES, \
 	GEN11_DEFAULT_PAGE_SIZES, \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
-		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 	GEN(11), \
-	.__runtime.has_dsc = 1, \
 	.has_coherent_ggtt = false, \
 	.has_logical_ring_elsq = 1
 
@@ -1064,6 +1108,16 @@ static const struct intel_display_device_info gen11_display = {
 	},
 	IVB_CURSOR_OFFSETS,
 	ICL_COLORS,
+
+	.__runtime.ip.ver = 11,
+	.__runtime.has_dmc = 1,
+	.__runtime.has_dsc = 1, \
+	.__runtime.has_hdcp = 1,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
+		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info icl_info = {
@@ -1093,10 +1147,6 @@ static const struct intel_device_info jsl_info = {
 #define GEN12_FEATURES \
 	GEN11_FEATURES, \
 	GEN(12), \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
-		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 	TGL_CACHELEVEL, \
 	.has_global_mocs = 1, \
 	.has_pxp = 1, \
@@ -1131,7 +1181,17 @@ static const struct intel_device_info jsl_info = {
 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 	}, \
 	TGL_CURSOR_OFFSETS, \
-	ICL_COLORS
+	ICL_COLORS, \
+	\
+	.__runtime.ip.ver = 12, \
+	.__runtime.has_dmc = 1, \
+	.__runtime.has_dsc = 1, \
+	.__runtime.has_hdcp = 1, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
+		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A)
 
 static const struct intel_display_device_info tgl_display = {
 	XE_D_DISPLAY,
@@ -1150,14 +1210,15 @@ static const struct intel_display_device_info rkl_display = {
 	.abox_mask = BIT(0),
 	.has_hti = 1,
 	.has_psr_hw_tracking = 0,
+
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C),
 };
 
 static const struct intel_device_info rkl_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_ROCKETLAKE),
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-		BIT(TRANSCODER_C),
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 	.display = &rkl_display,
@@ -1176,7 +1237,6 @@ static const struct intel_device_info dg1_info = {
 	DGFX_FEATURES,
 	.__runtime.graphics.ip.rel = 10,
 	PLATFORM(INTEL_DG1),
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.require_force_probe = 1,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
@@ -1195,7 +1255,6 @@ static const struct intel_display_device_info adl_s_display = {
 static const struct intel_device_info adl_s_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_ALDERLAKE_S),
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.dma_mask_size = 39,
@@ -1235,29 +1294,28 @@ static const struct intel_device_info adl_s_info = {
 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
 	},									\
-	TGL_CURSOR_OFFSETS
-
-#define XE_LPD_RUNTIME \
+	TGL_CURSOR_OFFSETS,							\
+										\
+	.__runtime.ip.ver = 13,							\
 	.__runtime.has_dmc = 1,							\
 	.__runtime.has_dsc = 1,							\
 	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
 	.__runtime.has_hdcp = 1,						\
-	.__runtime.display.ip.ver = 13,							\
 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
 
 static const struct intel_display_device_info xe_lpd_display = {
 	XE_LPD_FEATURES,
 	.has_cdclk_crawl = 1,
 	.has_psr_hw_tracking = 0,
-};
 
-static const struct intel_device_info adl_p_info = {
-	GEN12_FEATURES,
-	XE_LPD_RUNTIME,
-	PLATFORM(INTEL_ALDERLAKE_P),
 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
 			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
+};
+
+static const struct intel_device_info adl_p_info = {
+	GEN12_FEATURES,
+	PLATFORM(INTEL_ALDERLAKE_P),
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.__runtime.ppgtt_size = 48,
@@ -1341,13 +1399,13 @@ static const struct intel_device_info xehpsdv_info = {
 static const struct intel_display_device_info xe_hpd_display = {
 	XE_LPD_FEATURES,
 	.has_cdclk_squash = 1,
+
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 };
 
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
-	XE_LPD_RUNTIME,
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 	.display = &xe_hpd_display,
 };
 
@@ -1386,11 +1444,6 @@ static const struct intel_device_info pvc_info = {
 	PVC_CACHELEVEL,
 };
 
-#define XE_LPDP_RUNTIME	\
-	XE_LPD_RUNTIME,	\
-	.__runtime.display.ip.ver = 14,	\
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
-
 static const struct intel_gt_definition xelpmp_extra_gt[] = {
 	{
 		.type = GT_MEDIA,
@@ -1405,13 +1458,15 @@ static const struct intel_display_device_info xe_lpdp_display = {
 	XE_LPD_FEATURES,
 	.has_cdclk_crawl = 1,
 	.has_cdclk_squash = 1,
+
+	.__runtime.ip.ver = 14,
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 };
 
 static const struct intel_device_info mtl_info = {
 	XE_HP_FEATURES,
-	XE_LPDP_RUNTIME,
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 	/*
 	 * Real graphics IP version will be obtained from hardware GMD_ID
 	 * register.  Value provided here is just for sanity checking.
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d0bf626d0360..e10907ddbade 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -95,6 +95,9 @@ void intel_device_info_print(const struct intel_device_info *info,
 			     const struct intel_runtime_info *runtime,
 			     struct drm_printer *p)
 {
+	const struct intel_display_runtime_info *display_runtime =
+		&info->display->__runtime;
+
 	if (runtime->graphics.ip.rel)
 		drm_printf(p, "graphics version: %u.%02u\n",
 			   runtime->graphics.ip.ver,
@@ -111,13 +114,13 @@ void intel_device_info_print(const struct intel_device_info *info,
 		drm_printf(p, "media version: %u\n",
 			   runtime->media.ip.ver);
 
-	if (runtime->display.ip.rel)
+	if (display_runtime->ip.rel)
 		drm_printf(p, "display version: %u.%02u\n",
-			   runtime->display.ip.ver,
-			   runtime->display.ip.rel);
+			   display_runtime->ip.ver,
+			   display_runtime->ip.rel);
 	else
 		drm_printf(p, "display version: %u\n",
-			   runtime->display.ip.ver);
+			   display_runtime->ip.ver);
 
 	drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
 	drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));
@@ -142,9 +145,9 @@ void intel_device_info_print(const struct intel_device_info *info,
 	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
 #undef PRINT_FLAG
 
-	drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
-	drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
-	drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
+	drm_printf(p, "has_hdcp: %s\n", str_yes_no(display_runtime->has_hdcp));
+	drm_printf(p, "has_dmc: %s\n", str_yes_no(display_runtime->has_dmc));
+	drm_printf(p, "has_dsc: %s\n", str_yes_no(display_runtime->has_dsc));
 
 	drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 }
@@ -342,6 +345,7 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
 static void intel_ipver_early_init(struct drm_i915_private *i915)
 {
 	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
+	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
 
 	if (!HAS_GMD_ID(i915)) {
 		drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
@@ -363,7 +367,7 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
 		RUNTIME_INFO(i915)->graphics.ip.rel = 70;
 	}
 	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
-		    &runtime->display.ip);
+		    (struct intel_ip_version *)&display_runtime->ip);
 	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
 		    &runtime->media.ip);
 }
@@ -410,32 +414,34 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
+	struct intel_display_runtime_info *display_runtime =
+		DISPLAY_RUNTIME_INFO(dev_priv);
 	enum pipe pipe;
 
 	/* Wa_14011765242: adl-s A0,A1 */
 	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
 		for_each_pipe(dev_priv, pipe)
-			runtime->num_scalers[pipe] = 0;
+			display_runtime->num_scalers[pipe] = 0;
 	else if (DISPLAY_VER(dev_priv) >= 11) {
 		for_each_pipe(dev_priv, pipe)
-			runtime->num_scalers[pipe] = 2;
+			display_runtime->num_scalers[pipe] = 2;
 	} else if (DISPLAY_VER(dev_priv) >= 9) {
-		runtime->num_scalers[PIPE_A] = 2;
-		runtime->num_scalers[PIPE_B] = 2;
-		runtime->num_scalers[PIPE_C] = 1;
+		display_runtime->num_scalers[PIPE_A] = 2;
+		display_runtime->num_scalers[PIPE_B] = 2;
+		display_runtime->num_scalers[PIPE_C] = 1;
 	}
 
 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
 	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		for_each_pipe(dev_priv, pipe)
-			runtime->num_sprites[pipe] = 4;
+			display_runtime->num_sprites[pipe] = 4;
 	else if (DISPLAY_VER(dev_priv) >= 11)
 		for_each_pipe(dev_priv, pipe)
-			runtime->num_sprites[pipe] = 6;
+			display_runtime->num_sprites[pipe] = 6;
 	else if (DISPLAY_VER(dev_priv) == 10)
 		for_each_pipe(dev_priv, pipe)
-			runtime->num_sprites[pipe] = 3;
+			display_runtime->num_sprites[pipe] = 3;
 	else if (IS_BROXTON(dev_priv)) {
 		/*
 		 * Skylake and Broxton currently don't expose the topmost plane as its
@@ -446,15 +452,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		 * down the line.
 		 */
 
-		runtime->num_sprites[PIPE_A] = 2;
-		runtime->num_sprites[PIPE_B] = 2;
-		runtime->num_sprites[PIPE_C] = 1;
+		display_runtime->num_sprites[PIPE_A] = 2;
+		display_runtime->num_sprites[PIPE_B] = 2;
+		display_runtime->num_sprites[PIPE_C] = 1;
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
-			runtime->num_sprites[pipe] = 2;
+			display_runtime->num_sprites[pipe] = 2;
 	} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
-			runtime->num_sprites[pipe] = 1;
+			display_runtime->num_sprites[pipe] = 1;
 	}
 
 	if (HAS_DISPLAY(dev_priv) &&
@@ -462,7 +468,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	    !(intel_de_read(dev_priv, GU_CNTL_PROTECTED) & DEPRESENT)) {
 		drm_info(&dev_priv->drm, "Display not present, disabling\n");
 
-		runtime->pipe_mask = 0;
+		display_runtime->pipe_mask = 0;
 	}
 
 	if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
@@ -485,47 +491,47 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 			drm_info(&dev_priv->drm,
 				 "Display fused off, disabling\n");
-			runtime->pipe_mask = 0;
+			display_runtime->pipe_mask = 0;
 		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 			drm_info(&dev_priv->drm, "PipeC fused off\n");
-			runtime->pipe_mask &= ~BIT(PIPE_C);
-			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+			display_runtime->pipe_mask &= ~BIT(PIPE_C);
+			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 		}
 	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
 		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 
 		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
-			runtime->pipe_mask &= ~BIT(PIPE_A);
-			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
-			runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
+			display_runtime->pipe_mask &= ~BIT(PIPE_A);
+			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
+			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
 		}
 		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
-			runtime->pipe_mask &= ~BIT(PIPE_B);
-			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
+			display_runtime->pipe_mask &= ~BIT(PIPE_B);
+			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
 		}
 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
-			runtime->pipe_mask &= ~BIT(PIPE_C);
-			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+			display_runtime->pipe_mask &= ~BIT(PIPE_C);
+			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 		}
 
 		if (DISPLAY_VER(dev_priv) >= 12 &&
 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
-			runtime->pipe_mask &= ~BIT(PIPE_D);
-			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
+			display_runtime->pipe_mask &= ~BIT(PIPE_D);
+			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
 		}
 
 		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
-			runtime->has_hdcp = 0;
+			display_runtime->has_hdcp = 0;
 
 		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
-			runtime->fbc_mask = 0;
+			display_runtime->fbc_mask = 0;
 
 		if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
-			runtime->has_dmc = 0;
+			display_runtime->has_dmc = 0;
 
 		if (IS_DISPLAY_VER(dev_priv, 10, 12) &&
 		    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
-			runtime->has_dsc = 0;
+			display_runtime->has_dsc = 0;
 	}
 
 	if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
@@ -542,13 +548,13 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 						   DRIVER_ATOMIC);
 		info->display = &no_display;
 
-		runtime->cpu_transcoder_mask = 0;
-		memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
-		memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
-		runtime->fbc_mask = 0;
-		runtime->has_hdcp = false;
-		runtime->has_dmc = false;
-		runtime->has_dsc = false;
+		display_runtime->cpu_transcoder_mask = 0;
+		memset(display_runtime->num_sprites, 0, sizeof(display_runtime->num_sprites));
+		memset(display_runtime->num_scalers, 0, sizeof(display_runtime->num_scalers));
+		display_runtime->fbc_mask = 0;
+		display_runtime->has_hdcp = false;
+		display_runtime->has_dmc = false;
+		display_runtime->has_dsc = false;
 	}
 
 	/* Disable nuclear pageflip by default on pre-g4x */
@@ -568,6 +574,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
 {
 	struct intel_device_info *info;
 	struct intel_runtime_info *runtime;
+	struct intel_display_runtime_info *display_runtime;
 
 	/* Setup the write-once "constant" device info */
 	info = mkwrite_device_info(i915);
@@ -576,6 +583,10 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
 	/* Initialize initial runtime info from static const data and pdev. */
 	runtime = RUNTIME_INFO(i915);
 	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
+	display_runtime = DISPLAY_RUNTIME_INFO(i915);
+	memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
+	       sizeof(*display_runtime));
+
 	runtime->device_id = device_id;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index f212e02e6582..069291b3bd37 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -199,9 +199,6 @@ struct intel_runtime_info {
 	struct {
 		struct intel_ip_version ip;
 	} media;
-	struct {
-		struct intel_ip_version ip;
-	} display;
 
 	/*
 	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
@@ -229,21 +226,6 @@ struct intel_runtime_info {
 	u32 memory_regions; /* regions supported by the HW */
 
 	bool has_pooled_eu;
-
-	/* display */
-	struct {
-		u8 pipe_mask;
-		u8 cpu_transcoder_mask;
-
-		u8 num_sprites[I915_MAX_PIPES];
-		u8 num_scalers[I915_MAX_PIPES];
-
-		u8 fbc_mask;
-
-		bool has_hdcp;
-		bool has_dmc;
-		bool has_dsc;
-	};
 };
 
 struct intel_device_info {
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 84a6fe736a3b..8a9ff6227e53 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -166,8 +166,12 @@ void intel_step_init(struct drm_i915_private *i915)
 						       &RUNTIME_INFO(i915)->graphics.ip);
 		step.media_step = gmd_to_intel_step(i915,
 						    &RUNTIME_INFO(i915)->media.ip);
-		step.display_step = gmd_to_intel_step(i915,
-						      &RUNTIME_INFO(i915)->display.ip);
+		step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step;
+		if (step.display_step >= STEP_FUTURE) {
+			drm_dbg(&i915->drm, "Using future display steppings\n");
+			step.display_step = STEP_FUTURE;
+		}
+
 		RUNTIME_INFO(i915)->step = step;
 
 		return;
-- 
2.40.0


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 3/5] drm/i915/display: Move display runtime info to display structure
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Move display runtime info to display structure Matt Roper
@ 2023-05-18  7:56   ` Andrzej Hajda
  2023-05-22 16:41     ` Matt Roper
  0 siblings, 1 reply; 21+ messages in thread
From: Andrzej Hajda @ 2023-05-18  7:56 UTC (permalink / raw)
  To: Matt Roper, intel-gfx; +Cc: intel-xe

On 18.05.2023 05:18, Matt Roper wrote:
> Move the runtime info specific to display into display-specific
> structures as has already been done with the constant display info.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_crtc.c     |   2 +-
>   drivers/gpu/drm/i915/display/intel_cursor.c   |   2 +-
>   drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
>   drivers/gpu/drm/i915/display/intel_display.h  |   8 +-
>   .../drm/i915/display/intel_display_device.h   |  23 ++
>   drivers/gpu/drm/i915/display/intel_fbc.c      |   6 +-
>   drivers/gpu/drm/i915/display/intel_hdcp.c     |   2 +-
>   .../drm/i915/display/skl_universal_plane.c    |   2 +-
>   drivers/gpu/drm/i915/i915_drv.h               |  17 +-
>   drivers/gpu/drm/i915/i915_pci.c               | 221 +++++++++++-------
>   drivers/gpu/drm/i915/intel_device_info.c      | 101 ++++----
>   drivers/gpu/drm/i915/intel_device_info.h      |  18 --
>   drivers/gpu/drm/i915/intel_step.c             |   8 +-
>   13 files changed, 245 insertions(+), 167 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 93c3226b98c9..182c6dd64f47 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -306,7 +306,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
>   		return PTR_ERR(crtc);
>   
>   	crtc->pipe = pipe;
> -	crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
> +	crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
>   
>   	if (DISPLAY_VER(dev_priv) >= 9)
>   		primary = skl_universal_plane_create(dev_priv, pipe,
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index dd2def27add9..093fc881ddc1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -814,7 +814,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>   						   DRM_MODE_ROTATE_0 |
>   						   DRM_MODE_ROTATE_180);
>   
> -	zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
> +	zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
>   	drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
>   
>   	if (DISPLAY_VER(dev_priv) >= 12)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 09320e14d75c..f1130e2c3542 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3366,7 +3366,7 @@ static u8 bigjoiner_pipes(struct drm_i915_private *i915)
>   	else
>   		pipes = 0;
>   
> -	return pipes & RUNTIME_INFO(i915)->pipe_mask;
> +	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
>   }
>   
>   static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index aa3a21ccd7fe..c744c021af23 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -105,7 +105,7 @@ enum i9xx_plane_id {
>   };
>   
>   #define plane_name(p) ((p) + 'A')
> -#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
> +#define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
>   
>   #define for_each_plane_id_on_crtc(__crtc, __p) \
>   	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
> @@ -221,7 +221,7 @@ enum phy_fia {
>   
>   #define for_each_pipe(__dev_priv, __p) \
>   	for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
> -		for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
> +		for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
>   
>   #define for_each_pipe_masked(__dev_priv, __p, __mask) \
>   	for_each_pipe(__dev_priv, __p) \
> @@ -229,7 +229,7 @@ enum phy_fia {
>   
>   #define for_each_cpu_transcoder(__dev_priv, __t) \
>   	for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)	\
> -		for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
> +		for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
>   
>   #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
>   	for_each_cpu_transcoder(__dev_priv, __t) \
> @@ -237,7 +237,7 @@ enum phy_fia {
>   
>   #define for_each_sprite(__dev_priv, __p, __s)				\
>   	for ((__s) = 0;							\
> -	     (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];	\
> +	     (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];	\
>   	     (__s)++)
>   
>   #define for_each_port(__port) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index c689d582dbf1..241f39b13f2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -29,7 +29,30 @@
>   	func(overlay_needs_physical); \
>   	func(supports_tv);
>   
> +struct intel_display_runtime_info {
> +	struct {
> +		u16 ver;
> +		u16 rel;
> +		u16 step;
> +	} ip;

Why not intel_ip_version? Maybe upgrdaded to 16bit.

> +
> +	u8 pipe_mask;
> +	u8 cpu_transcoder_mask;
> +
> +	u8 num_sprites[I915_MAX_PIPES];
> +	u8 num_scalers[I915_MAX_PIPES];
> +
> +	u8 fbc_mask;
> +
> +	bool has_hdcp;
> +	bool has_dmc;
> +	bool has_dsc;
> +};
> +
>   struct intel_display_device_info {
> +	/* Initial runtime info. */
> +	const struct intel_display_runtime_info __runtime;

Seems little bit confusing.
Why not sth like default_runtime/initial_runtime ?

> +
>   	u8 abox_mask;
>   
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 11bb8cf9c9d0..1966f9396201 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -56,7 +56,7 @@
>   
>   #define for_each_fbc_id(__dev_priv, __fbc_id) \
>   	for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
> -		for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
> +		for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
>   
>   #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
>   	for_each_fbc_id((__dev_priv), (__fbc_id)) \
> @@ -1708,10 +1708,10 @@ void intel_fbc_init(struct drm_i915_private *i915)
>   	enum intel_fbc_id fbc_id;
>   
>   	if (!drm_mm_initialized(&i915->mm.stolen))
> -		RUNTIME_INFO(i915)->fbc_mask = 0;
> +		DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
>   
>   	if (need_fbc_vtd_wa(i915))
> -		RUNTIME_INFO(i915)->fbc_mask = 0;
> +		DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
>   
>   	i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
>   	drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index dd539106ee5a..1f96d1fa68e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1103,7 +1103,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
>   
>   bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
>   {
> -	return RUNTIME_INFO(dev_priv)->has_hdcp &&
> +	return DISPLAY_RUNTIME_INFO(dev_priv)->has_hdcp &&
>   		(DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
>   }
>   
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 110401aab038..36070d86550f 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1944,7 +1944,7 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
>   static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
>   			      enum intel_fbc_id fbc_id, enum plane_id plane_id)
>   {
> -	if ((RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
> +	if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
>   		return false;
>   
>   	return plane_id == PLANE_PRIMARY;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 116fc4441f8b..d312314b212e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -205,6 +205,7 @@ struct drm_i915_private {
>   
>   	const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
>   	struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
> +	struct intel_display_runtime_info __display_runtime; /* Access with DISPLAY_RUNTIME_INFO() */
>   	struct intel_driver_caps caps;
>   
>   	struct i915_dsm dsm;
> @@ -408,7 +409,9 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>   	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
>   
>   #define INTEL_INFO(i915)	(&(i915)->__info)
> +#define DISPLAY_INFO(i915)	(INTEL_INFO(i915)->display)

If introduced in previous patch it could simplify multiple lines there.


>   #define RUNTIME_INFO(i915)	(&(i915)->__runtime)
> +#define DISPLAY_RUNTIME_INFO(i915)	(&(i915)->__display_runtime)
>   #define DRIVER_CAPS(i915)	(&(i915)->caps)
>   
>   #define INTEL_DEVID(i915)	(RUNTIME_INFO(i915)->device_id)
> @@ -427,7 +430,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>   #define IS_MEDIA_VER(i915, from, until) \
>   	(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
>   
> -#define DISPLAY_VER(i915)	(RUNTIME_INFO(i915)->display.ip.ver)
> +#define DISPLAY_VER(i915)	(DISPLAY_RUNTIME_INFO(i915)->ip.ver)
>   #define IS_DISPLAY_VER(i915, from, until) \
>   	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
>   
> @@ -810,7 +813,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display->has_hotplug)
>   
>   #define HAS_FW_BLC(i915)	(DISPLAY_VER(i915) > 2)
> -#define HAS_FBC(i915)	(RUNTIME_INFO(i915)->fbc_mask != 0)
> +#define HAS_FBC(i915)	(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
>   #define HAS_CUR_FBC(i915)	(!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
>   
>   #define HAS_DPT(i915)	(DISPLAY_VER(i915) >= 13)
> @@ -830,7 +833,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define HAS_PSR_HW_TRACKING(i915) \
>   	(INTEL_INFO(i915)->display->has_psr_hw_tracking)
>   #define HAS_PSR2_SEL_FETCH(i915)	 (DISPLAY_VER(i915) >= 12)
> -#define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
> +#define HAS_TRANSCODER(i915, trans)	 ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
>   
>   #define HAS_RC6(i915)		 (INTEL_INFO(i915)->has_rc6)
>   #define HAS_RC6p(i915)		 (INTEL_INFO(i915)->has_rc6p)
> @@ -838,9 +841,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   
>   #define HAS_RPS(i915)	(INTEL_INFO(i915)->has_rps)
>   
> -#define HAS_DMC(i915)	(RUNTIME_INFO(i915)->has_dmc)
> +#define HAS_DMC(i915)	(DISPLAY_RUNTIME_INFO(i915)->has_dmc)
>   #define HAS_DSB(i915)	(INTEL_INFO(i915)->display->has_dsb)
> -#define HAS_DSC(__i915)		(RUNTIME_INFO(__i915)->has_dsc)
> +#define HAS_DSC(__i915)		(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
>   #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
>   
>   #define HAS_HECI_PXP(i915) \
> @@ -902,9 +905,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
>   				 2 : HAS_L3_DPF(i915))
>   
> -#define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask))
> +#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
>   
> -#define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0)
> +#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
>   
>   #define HAS_VRR(i915)	(DISPLAY_VER(i915) >= 11)
>   
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index dd874a4db604..8b19df1294de 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -41,10 +41,11 @@
>   #define PLATFORM(x) .platform = (x)
>   #define GEN(x) \
>   	.__runtime.graphics.ip.ver = (x), \
> -	.__runtime.media.ip.ver = (x), \
> -	.__runtime.display.ip.ver = (x)
> +	.__runtime.media.ip.ver = (x) >
> -#define NO_DISPLAY .__runtime.pipe_mask = 0
> +static const struct intel_display_device_info no_display = { 0 };
> +
> +#define NO_DISPLAY .display = &no_display

We could get rid of the macro, ".display = &no_display" seems to be 
clear enough.

>   
>   #define I845_PIPE_OFFSETS \
>   	.pipe_offsets = { \
> @@ -212,7 +213,11 @@
>   	.has_gmch = 1, \
>   	I9XX_PIPE_OFFSETS, \
>   	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS
> +	I9XX_COLORS, \
> +	\
> +	.__runtime.ip.ver = 2, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>   
>   static const struct intel_display_device_info i830_display = {
>   	I830_DISPLAY,
> @@ -221,8 +226,6 @@ static const struct intel_display_device_info i830_display = {
>   #define I830_FEATURES \
>   	GEN(2), \
>   	.is_mobile = 1, \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>   	.gpu_reset_clobbers_display = true, \
>   	.has_3d_pipeline = 1, \
>   	.hws_needs_physical = 1, \
> @@ -242,7 +245,11 @@ static const struct intel_display_device_info i830_display = {
>   	.has_gmch = 1, \
>   	I845_PIPE_OFFSETS, \
>   	I845_CURSOR_OFFSETS, \
> -	I845_COLORS
> +	I845_COLORS, \
> +	\
> +	.__runtime.ip.ver = 2, \
> +	.__runtime.pipe_mask = BIT(PIPE_A), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A)
>   
>   static const struct intel_display_device_info i845_display = {
>   	I845_DISPLAY,
> @@ -250,8 +257,6 @@ static const struct intel_display_device_info i845_display = {
>   
>   #define I845_FEATURES \
>   	GEN(2), \
> -	.__runtime.pipe_mask = BIT(PIPE_A), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
>   	.has_3d_pipeline = 1, \
>   	.gpu_reset_clobbers_display = true, \
>   	.hws_needs_physical = 1, \
> @@ -279,24 +284,26 @@ static const struct intel_device_info i845g_info = {
>   
>   static const struct intel_display_device_info i85x_display = {
>   	I830_DISPLAY,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info i85x_info = {
>   	I830_FEATURES,
>   	PLATFORM(INTEL_I85X),
>   	.display = &i85x_display,
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_display_device_info i865g_display = {
>   	I845_DISPLAY,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info i865g_info = {
>   	I845_FEATURES,
>   	PLATFORM(INTEL_I865G),
>   	.display = &i865g_display,
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   #define GEN3_DISPLAY \
> @@ -304,7 +311,11 @@ static const struct intel_device_info i865g_info = {
>   	.has_overlay = 1, \
>   	I9XX_PIPE_OFFSETS, \
>   	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS
> +	I9XX_COLORS, \
> +	\
> +	.__runtime.ip.ver = 3, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>   
>   static const struct intel_display_device_info i915g_display = {
>   	GEN3_DISPLAY,
> @@ -317,6 +328,8 @@ static const struct intel_display_device_info i915gm_display = {
>   	.cursor_needs_physical = 1,
>   	.overlay_needs_physical = 1,
>   	.supports_tv = 1,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_display_device_info i945g_display = {
> @@ -332,6 +345,8 @@ static const struct intel_display_device_info i945gm_display = {
>   	.cursor_needs_physical = 1,
>   	.overlay_needs_physical = 1,
>   	.supports_tv = 1,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_display_device_info g33_display = {
> @@ -341,8 +356,6 @@ static const struct intel_display_device_info g33_display = {
>   
>   #define GEN3_FEATURES \
>   	GEN(3), \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>   	.gpu_reset_clobbers_display = true, \
>   	.__runtime.platform_engine_mask = BIT(RCS0), \
>   	.has_3d_pipeline = 1, \
> @@ -368,7 +381,6 @@ static const struct intel_device_info i915gm_info = {
>   	PLATFORM(INTEL_I915GM),
>   	.display = &i915gm_display,
>   	.is_mobile = 1,
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
>   };
> @@ -386,7 +398,6 @@ static const struct intel_device_info i945gm_info = {
>   	PLATFORM(INTEL_I945GM),
>   	.display = &i945gm_display,
>   	.is_mobile = 1,
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
>   };
> @@ -418,7 +429,11 @@ static const struct intel_device_info pnv_m_info = {
>   	.has_gmch = 1, \
>   	I9XX_PIPE_OFFSETS, \
>   	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS
> +	I9XX_COLORS, \
> +	\
> +	.__runtime.ip.ver = 4, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>   
>   static const struct intel_display_device_info i965g_display = {
>   	GEN4_DISPLAY,
> @@ -429,6 +444,8 @@ static const struct intel_display_device_info i965gm_display = {
>   	GEN4_DISPLAY,
>   	.has_overlay = 1,
>   	.supports_tv = 1,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_display_device_info g45_display = {
> @@ -438,12 +455,12 @@ static const struct intel_display_device_info g45_display = {
>   static const struct intel_display_device_info gm45_display = {
>   	GEN4_DISPLAY,
>   	.supports_tv = 1,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   #define GEN4_FEATURES \
>   	GEN(4), \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>   	.gpu_reset_clobbers_display = true, \
>   	.__runtime.platform_engine_mask = BIT(RCS0), \
>   	.has_3d_pipeline = 1, \
> @@ -468,7 +485,6 @@ static const struct intel_device_info i965gm_info = {
>   	PLATFORM(INTEL_I965GM),
>   	.display = &i965gm_display,
>   	.is_mobile = 1,
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   	.hws_needs_physical = 1,
>   	.has_snoop = false,
>   };
> @@ -485,7 +501,6 @@ static const struct intel_device_info gm45_info = {
>   	GEN4_FEATURES,
>   	PLATFORM(INTEL_GM45),
>   	.is_mobile = 1,
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
>   	.display = &gm45_display,
>   	.gpu_reset_clobbers_display = false,
> @@ -493,8 +508,6 @@ static const struct intel_device_info gm45_info = {
>   
>   #define GEN5_FEATURES \
>   	GEN(5), \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
>   	.has_3d_pipeline = 1, \
>   	.has_snoop = true, \
> @@ -511,7 +524,11 @@ static const struct intel_device_info gm45_info = {
>   	.has_hotplug = 1, \
>   	I9XX_PIPE_OFFSETS, \
>   	I9XX_CURSOR_OFFSETS, \
> -	ILK_COLORS
> +	ILK_COLORS, \
> +	\
> +	.__runtime.ip.ver = 5, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>   
>   static const struct intel_display_device_info ilk_d_display = {
>   	ILK_DISPLAY,
> @@ -525,6 +542,8 @@ static const struct intel_device_info ilk_d_info = {
>   
>   static const struct intel_display_device_info ilk_m_display = {
>   	ILK_DISPLAY,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info ilk_m_info = {
> @@ -533,14 +552,10 @@ static const struct intel_device_info ilk_m_info = {
>   	.display = &ilk_m_display,
>   	.is_mobile = 1,
>   	.has_rps = true,
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   #define GEN6_FEATURES \
>   	GEN(6), \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   	.has_3d_pipeline = 1, \
>   	.has_coherent_ggtt = true, \
> @@ -562,6 +577,11 @@ static const struct intel_display_device_info snb_display = {
>   	I9XX_PIPE_OFFSETS,
>   	I9XX_CURSOR_OFFSETS,
>   	ILK_COLORS,
> +
> +	.__runtime.ip.ver = 6,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   #define SNB_D_PLATFORM \
> @@ -600,9 +620,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>   
>   #define GEN7_FEATURES  \
>   	GEN(7), \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   	.has_3d_pipeline = 1, \
>   	.has_coherent_ggtt = true, \
> @@ -629,6 +646,12 @@ static const struct intel_display_device_info ivb_display = {
>   	IVB_PIPE_OFFSETS,
>   	IVB_CURSOR_OFFSETS,
>   	IVB_COLORS,
> +
> +	.__runtime.ip.ver = 7,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info ivb_d_gt1_info = {
> @@ -676,14 +699,16 @@ static const struct intel_display_device_info vlv_display = {
>   	I9XX_PIPE_OFFSETS,
>   	I9XX_CURSOR_OFFSETS,
>   	I9XX_COLORS,
> +
> +	.__runtime.ip.ver = 7,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
>   };
>   
>   static const struct intel_device_info vlv_info = {
>   	PLATFORM(INTEL_VALLEYVIEW),
>   	GEN(7),
>   	.is_lp = 1,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
>   	.display = &vlv_display,
>   	.has_runtime_pm = 1,
>   	.has_rc6 = 1,
> @@ -704,8 +729,6 @@ static const struct intel_device_info vlv_info = {
>   #define G75_FEATURES  \
>   	GEN7_FEATURES, \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
>   	.has_rc6p = 0 /* RC6p removed-by HSW */, \
>   	.has_runtime_pm = 1
>   
> @@ -722,6 +745,12 @@ static const struct intel_display_device_info hsw_display = {
>   	HSW_PIPE_OFFSETS,
>   	IVB_CURSOR_OFFSETS,
>   	IVB_COLORS,
> +
> +	.__runtime.ip.ver = 7,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info hsw_gt1_info = {
> @@ -759,6 +788,12 @@ static const struct intel_display_device_info bdw_display = {
>   	HSW_PIPE_OFFSETS,
>   	IVB_CURSOR_OFFSETS,
>   	IVB_COLORS,
> +
> +	.__runtime.ip.ver = 8,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   #define BDW_PLATFORM \
> @@ -801,13 +836,16 @@ static const struct intel_display_device_info chv_display = {
>   	CHV_PIPE_OFFSETS,
>   	CHV_CURSOR_OFFSETS,
>   	CHV_COLORS,
> +
> +	.__runtime.ip.ver = 8,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C),
>   };
>   
>   static const struct intel_device_info chv_info = {
>   	PLATFORM(INTEL_CHERRYVIEW),
>   	GEN(8),
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
>   	.display = &chv_display,
>   	.is_lp = 1,
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> @@ -836,9 +874,7 @@ static const struct intel_device_info chv_info = {
>   	GEN8_FEATURES, \
>   	GEN(9), \
>   	GEN9_DEFAULT_PAGE_SIZES, \
> -	.__runtime.has_dmc = 1, \
> -	.has_gt_uc = 1, \
> -	.__runtime.has_hdcp = 1
> +	.has_gt_uc = 1
>   
>   static const struct intel_display_device_info skl_display = {
>   	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> @@ -853,6 +889,14 @@ static const struct intel_display_device_info skl_display = {
>   	HSW_PIPE_OFFSETS,
>   	IVB_CURSOR_OFFSETS,
>   	IVB_COLORS,
> +
> +	.__runtime.ip.ver = 9,
> +	.__runtime.has_dmc = 1,
> +	.__runtime.has_hdcp = 1,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   #define SKL_PLATFORM \
> @@ -893,16 +937,9 @@ static const struct intel_device_info skl_gt4_info = {
>   	GEN(9), \
>   	.is_lp = 1, \
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> -		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
>   	.has_3d_pipeline = 1, \
>   	.has_64bit_reloc = 1, \
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> -	.__runtime.has_hdcp = 1, \
>   	.has_runtime_pm = 1, \
> -	.__runtime.has_dmc = 1, \
>   	.has_rc6 = 1, \
>   	.has_rps = true, \
>   	.has_logical_ring_contexts = 1, \
> @@ -929,11 +966,21 @@ static const struct intel_device_info skl_gt4_info = {
>   	.has_psr_hw_tracking = 1, \
>   	HSW_PIPE_OFFSETS, \
>   	IVB_CURSOR_OFFSETS, \
> -	IVB_COLORS
> +	IVB_COLORS, \
> +	\
> +	.__runtime.has_dmc = 1, \
> +	.__runtime.has_hdcp = 1, \
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> +		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
>   
>   static const struct intel_display_device_info bxt_display = {
>   	GEN9_LP_DISPLAY,
>   	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> +
> +	.__runtime.ip.ver = 9,
>   };
>   
>   static const struct intel_device_info bxt_info = {
> @@ -946,12 +993,13 @@ static const struct intel_display_device_info glk_display = {
>   	GEN9_LP_DISPLAY,
>   	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
>   	GLK_COLORS,
> +
> +	.__runtime.ip.ver = 10,
>   };
>   
>   static const struct intel_device_info glk_info = {
>   	GEN9_LP_FEATURES,
>   	PLATFORM(INTEL_GEMINILAKE),
> -	.__runtime.display.ip.ver = 10,
>   	.display = &glk_display,
>   };
>   
> @@ -1027,11 +1075,7 @@ static const struct intel_device_info cml_gt2_info = {
>   #define GEN11_FEATURES \
>   	GEN9_FEATURES, \
>   	GEN11_DEFAULT_PAGE_SIZES, \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> -		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
>   	GEN(11), \
> -	.__runtime.has_dsc = 1, \
>   	.has_coherent_ggtt = false, \
>   	.has_logical_ring_elsq = 1
>   
> @@ -1064,6 +1108,16 @@ static const struct intel_display_device_info gen11_display = {
>   	},
>   	IVB_CURSOR_OFFSETS,
>   	ICL_COLORS,
> +
> +	.__runtime.ip.ver = 11,
> +	.__runtime.has_dmc = 1,
> +	.__runtime.has_dsc = 1, \
> +	.__runtime.has_hdcp = 1,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
> +		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info icl_info = {
> @@ -1093,10 +1147,6 @@ static const struct intel_device_info jsl_info = {
>   #define GEN12_FEATURES \
>   	GEN11_FEATURES, \
>   	GEN(12), \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> -		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
>   	TGL_CACHELEVEL, \
>   	.has_global_mocs = 1, \
>   	.has_pxp = 1, \
> @@ -1131,7 +1181,17 @@ static const struct intel_device_info jsl_info = {
>   		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
>   	}, \
>   	TGL_CURSOR_OFFSETS, \
> -	ICL_COLORS
> +	ICL_COLORS, \
> +	\
> +	.__runtime.ip.ver = 12, \
> +	.__runtime.has_dmc = 1, \
> +	.__runtime.has_dsc = 1, \
> +	.__runtime.has_hdcp = 1, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> +		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A)
>   
>   static const struct intel_display_device_info tgl_display = {
>   	XE_D_DISPLAY,
> @@ -1150,14 +1210,15 @@ static const struct intel_display_device_info rkl_display = {
>   	.abox_mask = BIT(0),
>   	.has_hti = 1,
>   	.has_psr_hw_tracking = 0,
> +
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C),
>   };
>   
>   static const struct intel_device_info rkl_info = {
>   	GEN12_FEATURES,
>   	PLATFORM(INTEL_ROCKETLAKE),
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -		BIT(TRANSCODER_C),
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
>   	.display = &rkl_display,
> @@ -1176,7 +1237,6 @@ static const struct intel_device_info dg1_info = {
>   	DGFX_FEATURES,
>   	.__runtime.graphics.ip.rel = 10,
>   	PLATFORM(INTEL_DG1),
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>   	.require_force_probe = 1,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
> @@ -1195,7 +1255,6 @@ static const struct intel_display_device_info adl_s_display = {
>   static const struct intel_device_info adl_s_info = {
>   	GEN12_FEATURES,
>   	PLATFORM(INTEL_ALDERLAKE_S),
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>   	.dma_mask_size = 39,
> @@ -1235,29 +1294,28 @@ static const struct intel_device_info adl_s_info = {
>   		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
>   		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
>   	},									\
> -	TGL_CURSOR_OFFSETS
> -
> -#define XE_LPD_RUNTIME \
> +	TGL_CURSOR_OFFSETS,							\
> +										\
> +	.__runtime.ip.ver = 13,							\
>   	.__runtime.has_dmc = 1,							\
>   	.__runtime.has_dsc = 1,							\
>   	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
>   	.__runtime.has_hdcp = 1,						\
> -	.__runtime.display.ip.ver = 13,							\
>   	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
>   
>   static const struct intel_display_device_info xe_lpd_display = {
>   	XE_LPD_FEATURES,
>   	.has_cdclk_crawl = 1,
>   	.has_psr_hw_tracking = 0,
> -};
>   
> -static const struct intel_device_info adl_p_info = {
> -	GEN12_FEATURES,
> -	XE_LPD_RUNTIME,
> -	PLATFORM(INTEL_ALDERLAKE_P),
>   	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>   			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
>   			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> +};
> +
> +static const struct intel_device_info adl_p_info = {
> +	GEN12_FEATURES,
> +	PLATFORM(INTEL_ALDERLAKE_P),
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>   	.__runtime.ppgtt_size = 48,
> @@ -1341,13 +1399,13 @@ static const struct intel_device_info xehpsdv_info = {
>   static const struct intel_display_device_info xe_hpd_display = {
>   	XE_LPD_FEATURES,
>   	.has_cdclk_squash = 1,
> +
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>   };
>   
>   static const struct intel_device_info dg2_info = {
>   	DG2_FEATURES,
> -	XE_LPD_RUNTIME,
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>   	.display = &xe_hpd_display,
>   };
>   
> @@ -1386,11 +1444,6 @@ static const struct intel_device_info pvc_info = {
>   	PVC_CACHELEVEL,
>   };
>   
> -#define XE_LPDP_RUNTIME	\
> -	XE_LPD_RUNTIME,	\
> -	.__runtime.display.ip.ver = 14,	\
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
> -
>   static const struct intel_gt_definition xelpmp_extra_gt[] = {
>   	{
>   		.type = GT_MEDIA,
> @@ -1405,13 +1458,15 @@ static const struct intel_display_device_info xe_lpdp_display = {
>   	XE_LPD_FEATURES,
>   	.has_cdclk_crawl = 1,
>   	.has_cdclk_squash = 1,
> +
> +	.__runtime.ip.ver = 14,
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>   };
>   
>   static const struct intel_device_info mtl_info = {
>   	XE_HP_FEATURES,
> -	XE_LPDP_RUNTIME,
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>   	/*
>   	 * Real graphics IP version will be obtained from hardware GMD_ID
>   	 * register.  Value provided here is just for sanity checking.
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index d0bf626d0360..e10907ddbade 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -95,6 +95,9 @@ void intel_device_info_print(const struct intel_device_info *info,
>   			     const struct intel_runtime_info *runtime,
>   			     struct drm_printer *p)
>   {
> +	const struct intel_display_runtime_info *display_runtime =
> +		&info->display->__runtime;
> +
>   	if (runtime->graphics.ip.rel)
>   		drm_printf(p, "graphics version: %u.%02u\n",
>   			   runtime->graphics.ip.ver,
> @@ -111,13 +114,13 @@ void intel_device_info_print(const struct intel_device_info *info,
>   		drm_printf(p, "media version: %u\n",
>   			   runtime->media.ip.ver);
>   
> -	if (runtime->display.ip.rel)
> +	if (display_runtime->ip.rel)
>   		drm_printf(p, "display version: %u.%02u\n",
> -			   runtime->display.ip.ver,
> -			   runtime->display.ip.rel);
> +			   display_runtime->ip.ver,
> +			   display_runtime->ip.rel);
>   	else
>   		drm_printf(p, "display version: %u\n",
> -			   runtime->display.ip.ver);
> +			   display_runtime->ip.ver);
>   
>   	drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
>   	drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));
> @@ -142,9 +145,9 @@ void intel_device_info_print(const struct intel_device_info *info,
>   	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
>   #undef PRINT_FLAG
>   
> -	drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
> -	drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
> -	drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
> +	drm_printf(p, "has_hdcp: %s\n", str_yes_no(display_runtime->has_hdcp));
> +	drm_printf(p, "has_dmc: %s\n", str_yes_no(display_runtime->has_dmc));
> +	drm_printf(p, "has_dsc: %s\n", str_yes_no(display_runtime->has_dsc));
>   
>   	drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
>   }
> @@ -342,6 +345,7 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
>   static void intel_ipver_early_init(struct drm_i915_private *i915)
>   {
>   	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
> +	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
>   
>   	if (!HAS_GMD_ID(i915)) {
>   		drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
> @@ -363,7 +367,7 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
>   		RUNTIME_INFO(i915)->graphics.ip.rel = 70;
>   	}
>   	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> -		    &runtime->display.ip);
> +		    (struct intel_ip_version *)&display_runtime->ip);
>   	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
>   		    &runtime->media.ip);
>   }
> @@ -410,32 +414,34 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   {
>   	struct intel_device_info *info = mkwrite_device_info(dev_priv);
>   	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
> +	struct intel_display_runtime_info *display_runtime =
> +		DISPLAY_RUNTIME_INFO(dev_priv);
>   	enum pipe pipe;
>   
>   	/* Wa_14011765242: adl-s A0,A1 */
>   	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
>   		for_each_pipe(dev_priv, pipe)
> -			runtime->num_scalers[pipe] = 0;
> +			display_runtime->num_scalers[pipe] = 0;
>   	else if (DISPLAY_VER(dev_priv) >= 11) {
>   		for_each_pipe(dev_priv, pipe)
> -			runtime->num_scalers[pipe] = 2;
> +			display_runtime->num_scalers[pipe] = 2;
>   	} else if (DISPLAY_VER(dev_priv) >= 9) {
> -		runtime->num_scalers[PIPE_A] = 2;
> -		runtime->num_scalers[PIPE_B] = 2;
> -		runtime->num_scalers[PIPE_C] = 1;
> +		display_runtime->num_scalers[PIPE_A] = 2;
> +		display_runtime->num_scalers[PIPE_B] = 2;
> +		display_runtime->num_scalers[PIPE_C] = 1;
>   	}
>   
>   	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
>   
>   	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
>   		for_each_pipe(dev_priv, pipe)
> -			runtime->num_sprites[pipe] = 4;
> +			display_runtime->num_sprites[pipe] = 4;
>   	else if (DISPLAY_VER(dev_priv) >= 11)
>   		for_each_pipe(dev_priv, pipe)
> -			runtime->num_sprites[pipe] = 6;
> +			display_runtime->num_sprites[pipe] = 6;
>   	else if (DISPLAY_VER(dev_priv) == 10)
>   		for_each_pipe(dev_priv, pipe)
> -			runtime->num_sprites[pipe] = 3;
> +			display_runtime->num_sprites[pipe] = 3;
>   	else if (IS_BROXTON(dev_priv)) {
>   		/*
>   		 * Skylake and Broxton currently don't expose the topmost plane as its
> @@ -446,15 +452,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   		 * down the line.
>   		 */
>   
> -		runtime->num_sprites[PIPE_A] = 2;
> -		runtime->num_sprites[PIPE_B] = 2;
> -		runtime->num_sprites[PIPE_C] = 1;
> +		display_runtime->num_sprites[PIPE_A] = 2;
> +		display_runtime->num_sprites[PIPE_B] = 2;
> +		display_runtime->num_sprites[PIPE_C] = 1;
>   	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>   		for_each_pipe(dev_priv, pipe)
> -			runtime->num_sprites[pipe] = 2;
> +			display_runtime->num_sprites[pipe] = 2;
>   	} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
>   		for_each_pipe(dev_priv, pipe)
> -			runtime->num_sprites[pipe] = 1;
> +			display_runtime->num_sprites[pipe] = 1;
>   	}
>   
>   	if (HAS_DISPLAY(dev_priv) &&
> @@ -462,7 +468,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   	    !(intel_de_read(dev_priv, GU_CNTL_PROTECTED) & DEPRESENT)) {
>   		drm_info(&dev_priv->drm, "Display not present, disabling\n");
>   
> -		runtime->pipe_mask = 0;
> +		display_runtime->pipe_mask = 0;
>   	}
>   
>   	if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
> @@ -485,47 +491,47 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
>   			drm_info(&dev_priv->drm,
>   				 "Display fused off, disabling\n");
> -			runtime->pipe_mask = 0;
> +			display_runtime->pipe_mask = 0;
>   		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
>   			drm_info(&dev_priv->drm, "PipeC fused off\n");
> -			runtime->pipe_mask &= ~BIT(PIPE_C);
> -			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> +			display_runtime->pipe_mask &= ~BIT(PIPE_C);
> +			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
>   		}
>   	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
>   		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
>   
>   		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
> -			runtime->pipe_mask &= ~BIT(PIPE_A);
> -			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
> -			runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
> +			display_runtime->pipe_mask &= ~BIT(PIPE_A);
> +			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
> +			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
>   		}
>   		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
> -			runtime->pipe_mask &= ~BIT(PIPE_B);
> -			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
> +			display_runtime->pipe_mask &= ~BIT(PIPE_B);
> +			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
>   		}
>   		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
> -			runtime->pipe_mask &= ~BIT(PIPE_C);
> -			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> +			display_runtime->pipe_mask &= ~BIT(PIPE_C);
> +			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
>   		}
>   
>   		if (DISPLAY_VER(dev_priv) >= 12 &&
>   		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
> -			runtime->pipe_mask &= ~BIT(PIPE_D);
> -			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> +			display_runtime->pipe_mask &= ~BIT(PIPE_D);
> +			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
>   		}
>   
>   		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> -			runtime->has_hdcp = 0;
> +			display_runtime->has_hdcp = 0;
>   
>   		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> -			runtime->fbc_mask = 0;
> +			display_runtime->fbc_mask = 0;
>   
>   		if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
> -			runtime->has_dmc = 0;
> +			display_runtime->has_dmc = 0;
>   
>   		if (IS_DISPLAY_VER(dev_priv, 10, 12) &&
>   		    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
> -			runtime->has_dsc = 0;
> +			display_runtime->has_dsc = 0;
>   	}
>   
>   	if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
> @@ -542,13 +548,13 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   						   DRIVER_ATOMIC);
>   		info->display = &no_display;
>   
> -		runtime->cpu_transcoder_mask = 0;
> -		memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
> -		memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
> -		runtime->fbc_mask = 0;
> -		runtime->has_hdcp = false;
> -		runtime->has_dmc = false;
> -		runtime->has_dsc = false;
> +		display_runtime->cpu_transcoder_mask = 0;
> +		memset(display_runtime->num_sprites, 0, sizeof(display_runtime->num_sprites));
> +		memset(display_runtime->num_scalers, 0, sizeof(display_runtime->num_scalers));
> +		display_runtime->fbc_mask = 0;
> +		display_runtime->has_hdcp = false;
> +		display_runtime->has_dmc = false;
> +		display_runtime->has_dsc = false;
>   	}
>   
>   	/* Disable nuclear pageflip by default on pre-g4x */
> @@ -568,6 +574,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
>   {
>   	struct intel_device_info *info;
>   	struct intel_runtime_info *runtime;
> +	struct intel_display_runtime_info *display_runtime;
>   
>   	/* Setup the write-once "constant" device info */
>   	info = mkwrite_device_info(i915);
> @@ -576,6 +583,10 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
>   	/* Initialize initial runtime info from static const data and pdev. */
>   	runtime = RUNTIME_INFO(i915);
>   	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
> +	display_runtime = DISPLAY_RUNTIME_INFO(i915);
> +	memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
> +	       sizeof(*display_runtime));
> +
>   	runtime->device_id = device_id;
>   }
>   
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index f212e02e6582..069291b3bd37 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -199,9 +199,6 @@ struct intel_runtime_info {
>   	struct {
>   		struct intel_ip_version ip;
>   	} media;
> -	struct {
> -		struct intel_ip_version ip;
> -	} display;
>   
>   	/*
>   	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
> @@ -229,21 +226,6 @@ struct intel_runtime_info {
>   	u32 memory_regions; /* regions supported by the HW */
>   
>   	bool has_pooled_eu;
> -
> -	/* display */
> -	struct {
> -		u8 pipe_mask;
> -		u8 cpu_transcoder_mask;
> -
> -		u8 num_sprites[I915_MAX_PIPES];
> -		u8 num_scalers[I915_MAX_PIPES];
> -
> -		u8 fbc_mask;
> -
> -		bool has_hdcp;
> -		bool has_dmc;
> -		bool has_dsc;
> -	};
>   };
>   
>   struct intel_device_info {
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 84a6fe736a3b..8a9ff6227e53 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -166,8 +166,12 @@ void intel_step_init(struct drm_i915_private *i915)
>   						       &RUNTIME_INFO(i915)->graphics.ip);
>   		step.media_step = gmd_to_intel_step(i915,
>   						    &RUNTIME_INFO(i915)->media.ip);
> -		step.display_step = gmd_to_intel_step(i915,
> -						      &RUNTIME_INFO(i915)->display.ip);
> +		step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step;
> +		if (step.display_step >= STEP_FUTURE) {
> +			drm_dbg(&i915->drm, "Using future display steppings\n");
> +			step.display_step = STEP_FUTURE;
> +		}
> +

I wondered why unwinded but I've realized because of differnt type of 
display 'ip', maybe using common type is not a bad idea.

Regards
Andrzej


>   		RUNTIME_INFO(i915)->step = step;
>   
>   		return;


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 3/5] drm/i915/display: Move display runtime info to display structure
  2023-05-18  7:56   ` Andrzej Hajda
@ 2023-05-22 16:41     ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-05-22 16:41 UTC (permalink / raw)
  To: Andrzej Hajda; +Cc: intel-gfx, intel-xe

On Thu, May 18, 2023 at 09:56:07AM +0200, Andrzej Hajda wrote:
> On 18.05.2023 05:18, Matt Roper wrote:
> > Move the runtime info specific to display into display-specific
> > structures as has already been done with the constant display info.
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
...
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -29,7 +29,30 @@
> >   	func(overlay_needs_physical); \
> >   	func(supports_tv);
> > +struct intel_display_runtime_info {
> > +	struct {
> > +		u16 ver;
> > +		u16 rel;
> > +		u16 step;
> > +	} ip;
> 
> Why not intel_ip_version? Maybe upgrdaded to 16bit.

intel_ip_version is an i915-specific structure.  Part of the goal of
this series is to minimize the use of i915 types (aside from those that
are specific to display) so that the code can be more easily re-used in
Xe with a smaller compatibility layer.


Matt

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH 4/5] drm/i915/display: Make display responsible for probing its own IP
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
                   ` (2 preceding siblings ...)
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Move display runtime info to display structure Matt Roper
@ 2023-05-18  3:18 ` Matt Roper
  2023-05-18 10:01   ` Andrzej Hajda
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Matt Roper @ 2023-05-18  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Matt Roper, intel-xe

Rather than selecting the display IP and feature flags at the same time
the general PCI probing happens, move this step into the display code
itself so that it can be more easily re-used outside of i915 (i.e., by
the Xe driver).

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   2 +
 .../drm/i915/display/intel_display_device.c   | 692 ++++++++++++++++++
 .../drm/i915/display/intel_display_device.h   |   3 +
 drivers/gpu/drm/i915/i915_pci.c               | 650 ----------------
 drivers/gpu/drm/i915/i915_reg.h               |  33 -
 drivers/gpu/drm/i915/intel_device_info.c      |  13 +-
 6 files changed, 707 insertions(+), 686 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dd9ca69f4998..06374fc072d3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -25,6 +25,7 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
 
 # Fine grained warnings disable
 CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
+CFLAGS_display/intel_display_device.o = $(call cc-disable-warning, override-init)
 CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
 
 subdir-ccflags-y += -I$(srctree)/$(src)
@@ -308,6 +309,7 @@ i915-y += \
 	display/intel_cx0_phy.o \
 	display/intel_ddi.o \
 	display/intel_ddi_buf_trans.o \
+	display/intel_display_device.o \
 	display/intel_display_trace.o \
 	display/intel_dkl_phy.o \
 	display/intel_dp.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
new file mode 100644
index 000000000000..78fa522aaf0b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <drm/i915_pciids.h>
+#include <drm/drm_color_mgmt.h>
+#include <linux/mod_devicetable.h>
+
+#include "intel_display_device.h"
+#include "intel_display_power.h"
+#include "intel_display_reg_defs.h"
+#include "intel_fbc.h"
+
+#define PIPE_A_OFFSET		0x70000
+#define PIPE_B_OFFSET		0x71000
+#define PIPE_C_OFFSET		0x72000
+#define PIPE_D_OFFSET		0x73000
+#define CHV_PIPE_C_OFFSET	0x74000
+/*
+ * There's actually no pipe EDP. Some pipe registers have
+ * simply shifted from the pipe to the transcoder, while
+ * keeping their original offset. Thus we need PIPE_EDP_OFFSET
+ * to access such registers in transcoder EDP.
+ */
+#define PIPE_EDP_OFFSET	0x7f000
+
+/* ICL DSI 0 and 1 */
+#define PIPE_DSI0_OFFSET	0x7b000
+#define PIPE_DSI1_OFFSET	0x7b800
+
+#define TRANSCODER_A_OFFSET 0x60000
+#define TRANSCODER_B_OFFSET 0x61000
+#define TRANSCODER_C_OFFSET 0x62000
+#define CHV_TRANSCODER_C_OFFSET 0x63000
+#define TRANSCODER_D_OFFSET 0x63000
+#define TRANSCODER_EDP_OFFSET 0x6f000
+#define TRANSCODER_DSI0_OFFSET	0x6b000
+#define TRANSCODER_DSI1_OFFSET	0x6b800
+
+#define CURSOR_A_OFFSET 0x70080
+#define CURSOR_B_OFFSET 0x700c0
+#define CHV_CURSOR_C_OFFSET 0x700e0
+#define IVB_CURSOR_B_OFFSET 0x71080
+#define IVB_CURSOR_C_OFFSET 0x72080
+#define TGL_CURSOR_D_OFFSET 0x73080
+
+#define I845_PIPE_OFFSETS \
+	.pipe_offsets = { \
+		[TRANSCODER_A] = PIPE_A_OFFSET,	\
+	}, \
+	.trans_offsets = { \
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+	}
+
+#define I9XX_PIPE_OFFSETS \
+	.pipe_offsets = { \
+		[TRANSCODER_A] = PIPE_A_OFFSET,	\
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
+	}, \
+	.trans_offsets = { \
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+	}
+
+#define IVB_PIPE_OFFSETS \
+	.pipe_offsets = { \
+		[TRANSCODER_A] = PIPE_A_OFFSET,	\
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
+		[TRANSCODER_C] = PIPE_C_OFFSET, \
+	}, \
+	.trans_offsets = { \
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+	}
+
+#define HSW_PIPE_OFFSETS \
+	.pipe_offsets = { \
+		[TRANSCODER_A] = PIPE_A_OFFSET,	\
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
+		[TRANSCODER_C] = PIPE_C_OFFSET, \
+		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
+	}, \
+	.trans_offsets = { \
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
+	}
+
+#define CHV_PIPE_OFFSETS \
+	.pipe_offsets = { \
+		[TRANSCODER_A] = PIPE_A_OFFSET, \
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
+		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
+	}, \
+	.trans_offsets = { \
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
+	}
+
+#define I845_CURSOR_OFFSETS \
+	.cursor_offsets = { \
+		[PIPE_A] = CURSOR_A_OFFSET, \
+	}
+
+#define I9XX_CURSOR_OFFSETS \
+	.cursor_offsets = { \
+		[PIPE_A] = CURSOR_A_OFFSET, \
+		[PIPE_B] = CURSOR_B_OFFSET, \
+	}
+
+#define CHV_CURSOR_OFFSETS \
+	.cursor_offsets = { \
+		[PIPE_A] = CURSOR_A_OFFSET, \
+		[PIPE_B] = CURSOR_B_OFFSET, \
+		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
+	}
+
+#define IVB_CURSOR_OFFSETS \
+	.cursor_offsets = { \
+		[PIPE_A] = CURSOR_A_OFFSET, \
+		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
+		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
+	}
+
+#define TGL_CURSOR_OFFSETS \
+	.cursor_offsets = { \
+		[PIPE_A] = CURSOR_A_OFFSET, \
+		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
+		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
+		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
+	}
+
+#define I845_COLORS \
+	.color = { .gamma_lut_size = 256 }
+#define I9XX_COLORS \
+	.color = { .gamma_lut_size = 129, \
+		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+	}
+#define ILK_COLORS \
+	.color = { .gamma_lut_size = 1024 }
+#define IVB_COLORS \
+	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
+#define CHV_COLORS \
+	.color = { \
+		.degamma_lut_size = 65, .gamma_lut_size = 257, \
+		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+	}
+#define GLK_COLORS \
+	.color = { \
+		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
+		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
+	}
+#define ICL_COLORS \
+	.color = { \
+		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
+		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
+		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+	}
+
+#define I830_DISPLAY \
+	.has_overlay = 1, \
+	.cursor_needs_physical = 1, \
+	.overlay_needs_physical = 1, \
+	.has_gmch = 1, \
+	I9XX_PIPE_OFFSETS, \
+	I9XX_CURSOR_OFFSETS, \
+	I9XX_COLORS, \
+	\
+	.__runtime.ip.ver = 2, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
+
+static const struct intel_display_device_info i830_display = {
+	I830_DISPLAY,
+};
+
+#define I845_DISPLAY \
+	.has_overlay = 1, \
+	.overlay_needs_physical = 1, \
+	.has_gmch = 1, \
+	I845_PIPE_OFFSETS, \
+	I845_CURSOR_OFFSETS, \
+	I845_COLORS, \
+	\
+	.__runtime.ip.ver = 2, \
+	.__runtime.pipe_mask = BIT(PIPE_A), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A)
+
+static const struct intel_display_device_info i845_display = {
+	I845_DISPLAY,
+};
+
+static const struct intel_display_device_info i85x_display = {
+	I830_DISPLAY,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info i865g_display = {
+	I845_DISPLAY,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+#define GEN3_DISPLAY \
+	.has_gmch = 1, \
+	.has_overlay = 1, \
+	I9XX_PIPE_OFFSETS, \
+	I9XX_CURSOR_OFFSETS, \
+	I9XX_COLORS, \
+	\
+	.__runtime.ip.ver = 3, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
+
+static const struct intel_display_device_info i915g_display = {
+	GEN3_DISPLAY,
+	.cursor_needs_physical = 1,
+	.overlay_needs_physical = 1,
+};
+
+static const struct intel_display_device_info i915gm_display = {
+	GEN3_DISPLAY,
+	.cursor_needs_physical = 1,
+	.overlay_needs_physical = 1,
+	.supports_tv = 1,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info i945g_display = {
+	GEN3_DISPLAY,
+	.has_hotplug = 1,
+	.cursor_needs_physical = 1,
+	.overlay_needs_physical = 1,
+};
+
+static const struct intel_display_device_info i945gm_display = {
+	GEN3_DISPLAY,
+	.has_hotplug = 1,
+	.cursor_needs_physical = 1,
+	.overlay_needs_physical = 1,
+	.supports_tv = 1,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info g33_display = {
+	GEN3_DISPLAY,
+	.has_hotplug = 1,
+};
+
+#define GEN4_DISPLAY \
+	.has_hotplug = 1, \
+	.has_gmch = 1, \
+	I9XX_PIPE_OFFSETS, \
+	I9XX_CURSOR_OFFSETS, \
+	I9XX_COLORS, \
+	\
+	.__runtime.ip.ver = 4, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
+
+static const struct intel_display_device_info i965g_display = {
+	GEN4_DISPLAY,
+	.has_overlay = 1,
+};
+
+static const struct intel_display_device_info i965gm_display = {
+	GEN4_DISPLAY,
+	.has_overlay = 1,
+	.supports_tv = 1,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info g45_display = {
+	GEN4_DISPLAY,
+};
+
+static const struct intel_display_device_info gm45_display = {
+	GEN4_DISPLAY,
+	.supports_tv = 1,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+#define ILK_DISPLAY \
+	.has_hotplug = 1, \
+	I9XX_PIPE_OFFSETS, \
+	I9XX_CURSOR_OFFSETS, \
+	ILK_COLORS, \
+	\
+	.__runtime.ip.ver = 5, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
+
+static const struct intel_display_device_info ilk_d_display = {
+	ILK_DISPLAY,
+};
+
+static const struct intel_display_device_info ilk_m_display = {
+	ILK_DISPLAY,
+
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info snb_display = {
+	.has_hotplug = 1,
+	I9XX_PIPE_OFFSETS,
+	I9XX_CURSOR_OFFSETS,
+	ILK_COLORS,
+
+	.__runtime.ip.ver = 6,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info ivb_display = {
+	.has_hotplug = 1,
+	IVB_PIPE_OFFSETS,
+	IVB_CURSOR_OFFSETS,
+	IVB_COLORS,
+
+	.__runtime.ip.ver = 7,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info vlv_display = {
+	.has_gmch = 1,
+	.has_hotplug = 1,
+	.mmio_offset = VLV_DISPLAY_BASE,
+	I9XX_PIPE_OFFSETS,
+	I9XX_CURSOR_OFFSETS,
+	I9XX_COLORS,
+
+	.__runtime.ip.ver = 7,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+};
+
+static const struct intel_display_device_info hsw_display = {
+	.has_ddi = 1,
+	.has_dp_mst = 1,
+	.has_fpga_dbg = 1,
+	.has_hotplug = 1,
+	HSW_PIPE_OFFSETS,
+	IVB_CURSOR_OFFSETS,
+	IVB_COLORS,
+
+	.__runtime.ip.ver = 7,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info bdw_display = {
+	.has_ddi = 1,
+	.has_dp_mst = 1,
+	.has_fpga_dbg = 1,
+	.has_hotplug = 1,
+	HSW_PIPE_OFFSETS,
+	IVB_CURSOR_OFFSETS,
+	IVB_COLORS,
+
+	.__runtime.ip.ver = 8,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info chv_display = {
+	.has_hotplug = 1,
+	.has_gmch = 1,
+	.mmio_offset = VLV_DISPLAY_BASE,
+	CHV_PIPE_OFFSETS,
+	CHV_CURSOR_OFFSETS,
+	CHV_COLORS,
+
+	.__runtime.ip.ver = 8,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C),
+};
+
+static const struct intel_display_device_info skl_display = {
+	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
+	.dbuf.slice_mask = BIT(DBUF_S1),
+	.has_ddi = 1,
+	.has_dp_mst = 1,
+	.has_fpga_dbg = 1,
+	.has_hotplug = 1,
+	.has_ipc = 1,
+	.has_psr = 1,
+	.has_psr_hw_tracking = 1,
+	HSW_PIPE_OFFSETS,
+	IVB_CURSOR_OFFSETS,
+	IVB_COLORS,
+
+	.__runtime.ip.ver = 9,
+	.__runtime.has_dmc = 1,
+	.__runtime.has_hdcp = 1,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+#define GEN9_LP_DISPLAY \
+	.dbuf.slice_mask = BIT(DBUF_S1), \
+	.has_dp_mst = 1, \
+	.has_ddi = 1, \
+	.has_fpga_dbg = 1, \
+	.has_hotplug = 1, \
+	.has_ipc = 1, \
+	.has_psr = 1, \
+	.has_psr_hw_tracking = 1, \
+	HSW_PIPE_OFFSETS, \
+	IVB_CURSOR_OFFSETS, \
+	IVB_COLORS, \
+	\
+	.__runtime.has_dmc = 1, \
+	.__runtime.has_hdcp = 1, \
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
+		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
+
+static const struct intel_display_device_info bxt_display = {
+	GEN9_LP_DISPLAY,
+	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+
+	.__runtime.ip.ver = 9,
+};
+
+static const struct intel_display_device_info glk_display = {
+	GEN9_LP_DISPLAY,
+	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
+	GLK_COLORS,
+
+	.__runtime.ip.ver = 10,
+};
+
+static const struct intel_display_device_info gen11_display = {
+	.abox_mask = BIT(0),
+	.dbuf.size = 2048,
+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
+	.has_ddi = 1,
+	.has_dp_mst = 1,
+	.has_fpga_dbg = 1,
+	.has_hotplug = 1,
+	.has_ipc = 1,
+	.has_psr = 1,
+	.has_psr_hw_tracking = 1,
+	.pipe_offsets = {
+		[TRANSCODER_A] = PIPE_A_OFFSET,
+		[TRANSCODER_B] = PIPE_B_OFFSET,
+		[TRANSCODER_C] = PIPE_C_OFFSET,
+		[TRANSCODER_EDP] = PIPE_EDP_OFFSET,
+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
+	},
+	.trans_offsets = {
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
+		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
+	},
+	IVB_CURSOR_OFFSETS,
+	ICL_COLORS,
+
+	.__runtime.ip.ver = 11,
+	.__runtime.has_dmc = 1,
+	.__runtime.has_dsc = 1, \
+	.__runtime.has_hdcp = 1,
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
+		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+#define XE_D_DISPLAY \
+	.abox_mask = GENMASK(2, 1), \
+	.dbuf.size = 2048, \
+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
+	.has_ddi = 1, \
+	.has_dp_mst = 1, \
+	.has_dsb = 1, \
+	.has_fpga_dbg = 1, \
+	.has_hotplug = 1, \
+	.has_ipc = 1, \
+	.has_psr = 1, \
+	.has_psr_hw_tracking = 1, \
+	.pipe_offsets = { \
+		[TRANSCODER_A] = PIPE_A_OFFSET, \
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
+		[TRANSCODER_C] = PIPE_C_OFFSET, \
+		[TRANSCODER_D] = PIPE_D_OFFSET, \
+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+	}, \
+	.trans_offsets = { \
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+	}, \
+	TGL_CURSOR_OFFSETS, \
+	ICL_COLORS, \
+	\
+	.__runtime.ip.ver = 12, \
+	.__runtime.has_dmc = 1, \
+	.__runtime.has_dsc = 1, \
+	.__runtime.has_hdcp = 1, \
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
+		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A)
+
+static const struct intel_display_device_info tgl_display = {
+	XE_D_DISPLAY,
+};
+
+static const struct intel_display_device_info rkl_display = {
+	XE_D_DISPLAY,
+	.abox_mask = BIT(0),
+	.has_hti = 1,
+	.has_psr_hw_tracking = 0,
+
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C),
+};
+
+static const struct intel_display_device_info adl_s_display = {
+	XE_D_DISPLAY,
+	.has_hti = 1,
+	.has_psr_hw_tracking = 0,
+};
+
+#define XE_LPD_FEATURES \
+	.abox_mask = GENMASK(1, 0),						\
+	.color = {								\
+		.degamma_lut_size = 129, .gamma_lut_size = 1024,		\
+		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
+		DRM_COLOR_LUT_EQUAL_CHANNELS,					\
+	},									\
+	.dbuf.size = 4096,							\
+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
+		BIT(DBUF_S4),							\
+	.has_ddi = 1,								\
+	.has_dp_mst = 1,							\
+	.has_dsb = 1,								\
+	.has_fpga_dbg = 1,							\
+	.has_hotplug = 1,							\
+	.has_ipc = 1,								\
+	.has_psr = 1,								\
+	.pipe_offsets = {							\
+		[TRANSCODER_A] = PIPE_A_OFFSET,					\
+		[TRANSCODER_B] = PIPE_B_OFFSET,					\
+		[TRANSCODER_C] = PIPE_C_OFFSET,					\
+		[TRANSCODER_D] = PIPE_D_OFFSET,					\
+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
+	},									\
+	.trans_offsets = {						\
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
+		[TRANSCODER_D] = TRANSCODER_D_OFFSET,				\
+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
+	},									\
+	TGL_CURSOR_OFFSETS,							\
+										\
+	.__runtime.ip.ver = 13,							\
+	.__runtime.has_dmc = 1,							\
+	.__runtime.has_dsc = 1,							\
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
+	.__runtime.has_hdcp = 1,						\
+	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
+
+static const struct intel_display_device_info xe_lpd_display = {
+	XE_LPD_FEATURES,
+	.has_cdclk_crawl = 1,
+	.has_psr_hw_tracking = 0,
+
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
+			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
+};
+
+static const struct intel_display_device_info xe_hpd_display = {
+	XE_LPD_FEATURES,
+	.has_cdclk_squash = 1,
+
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+};
+
+static const struct intel_display_device_info xe_lpdp_display = {
+	XE_LPD_FEATURES,
+	.has_cdclk_crawl = 1,
+	.has_cdclk_squash = 1,
+
+	.__runtime.ip.ver = 14,
+	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
+	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+};
+
+static const struct pci_device_id intel_display_ids[] = {
+	INTEL_I830_IDS(&i830_display),
+	INTEL_I845G_IDS(&i845_display),
+	INTEL_I85X_IDS(&i85x_display),
+	INTEL_I865G_IDS(&i865g_display),
+	INTEL_I915G_IDS(&i915g_display),
+	INTEL_I915GM_IDS(&i915gm_display),
+	INTEL_I945G_IDS(&i945g_display),
+	INTEL_I945GM_IDS(&i945gm_display),
+	INTEL_I965G_IDS(&i965g_display),
+	INTEL_G33_IDS(&g33_display),
+	INTEL_I965GM_IDS(&i965gm_display),
+	INTEL_GM45_IDS(&gm45_display),
+	INTEL_G45_IDS(&g45_display),
+	INTEL_PINEVIEW_G_IDS(&g33_display),
+	INTEL_PINEVIEW_M_IDS(&g33_display),
+	INTEL_IRONLAKE_D_IDS(&ilk_d_display),
+	INTEL_IRONLAKE_M_IDS(&ilk_m_display),
+	INTEL_SNB_D_IDS(&snb_display),
+	INTEL_SNB_M_IDS(&snb_display),
+	INTEL_IVB_Q_IDS(NULL),		/* must be first IVB in list */
+	INTEL_IVB_M_IDS(&ivb_display),
+	INTEL_IVB_D_IDS(&ivb_display),
+	INTEL_HSW_IDS(&hsw_display),
+	INTEL_VLV_IDS(&vlv_display),
+	INTEL_BDW_IDS(&bdw_display),
+	INTEL_CHV_IDS(&chv_display),
+	INTEL_SKL_IDS(&skl_display),
+	INTEL_BXT_IDS(&bxt_display),
+	INTEL_GLK_IDS(&glk_display),
+	INTEL_KBL_IDS(&skl_display),
+	INTEL_CFL_IDS(&skl_display),
+	INTEL_ICL_11_IDS(&gen11_display),
+	INTEL_EHL_IDS(&gen11_display),
+	INTEL_JSL_IDS(&gen11_display),
+	INTEL_TGL_12_IDS(&tgl_display),
+	INTEL_DG1_IDS(&tgl_display),
+	INTEL_RKL_IDS(&rkl_display),
+	INTEL_ADLS_IDS(&adl_s_display),
+	INTEL_RPLS_IDS(&adl_s_display),
+	INTEL_ADLP_IDS(&xe_lpd_display),
+	INTEL_ADLN_IDS(&xe_lpd_display),
+	INTEL_RPLP_IDS(&xe_lpd_display),
+	INTEL_DG2_IDS(&xe_hpd_display),
+
+	/* FIXME: Replace this with a GMD_ID lookup */
+	INTEL_MTL_IDS(&xe_lpdp_display),
+};
+
+const struct intel_display_device_info *
+intel_display_device_probe(u16 pci_devid)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
+		if (intel_display_ids[i].device == pci_devid)
+			return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
+	}
+
+	return NULL;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 241f39b13f2f..0a60ebfaff80 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -80,4 +80,7 @@ struct intel_display_device_info {
 	} color;
 };
 
+const struct intel_display_device_info *
+intel_display_device_probe(u16 pci_devid);
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8b19df1294de..928975d5fe2f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -43,129 +43,6 @@
 	.__runtime.graphics.ip.ver = (x), \
 	.__runtime.media.ip.ver = (x)
 
-static const struct intel_display_device_info no_display = { 0 };
-
-#define NO_DISPLAY .display = &no_display
-
-#define I845_PIPE_OFFSETS \
-	.pipe_offsets = { \
-		[TRANSCODER_A] = PIPE_A_OFFSET,	\
-	}, \
-	.trans_offsets = { \
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
-	}
-
-#define I9XX_PIPE_OFFSETS \
-	.pipe_offsets = { \
-		[TRANSCODER_A] = PIPE_A_OFFSET,	\
-		[TRANSCODER_B] = PIPE_B_OFFSET, \
-	}, \
-	.trans_offsets = { \
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
-		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
-	}
-
-#define IVB_PIPE_OFFSETS \
-	.pipe_offsets = { \
-		[TRANSCODER_A] = PIPE_A_OFFSET,	\
-		[TRANSCODER_B] = PIPE_B_OFFSET, \
-		[TRANSCODER_C] = PIPE_C_OFFSET, \
-	}, \
-	.trans_offsets = { \
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
-		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
-		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
-	}
-
-#define HSW_PIPE_OFFSETS \
-	.pipe_offsets = { \
-		[TRANSCODER_A] = PIPE_A_OFFSET,	\
-		[TRANSCODER_B] = PIPE_B_OFFSET, \
-		[TRANSCODER_C] = PIPE_C_OFFSET, \
-		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
-	}, \
-	.trans_offsets = { \
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
-		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
-		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
-		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
-	}
-
-#define CHV_PIPE_OFFSETS \
-	.pipe_offsets = { \
-		[TRANSCODER_A] = PIPE_A_OFFSET, \
-		[TRANSCODER_B] = PIPE_B_OFFSET, \
-		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
-	}, \
-	.trans_offsets = { \
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
-		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
-		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
-	}
-
-#define I845_CURSOR_OFFSETS \
-	.cursor_offsets = { \
-		[PIPE_A] = CURSOR_A_OFFSET, \
-	}
-
-#define I9XX_CURSOR_OFFSETS \
-	.cursor_offsets = { \
-		[PIPE_A] = CURSOR_A_OFFSET, \
-		[PIPE_B] = CURSOR_B_OFFSET, \
-	}
-
-#define CHV_CURSOR_OFFSETS \
-	.cursor_offsets = { \
-		[PIPE_A] = CURSOR_A_OFFSET, \
-		[PIPE_B] = CURSOR_B_OFFSET, \
-		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
-	}
-
-#define IVB_CURSOR_OFFSETS \
-	.cursor_offsets = { \
-		[PIPE_A] = CURSOR_A_OFFSET, \
-		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
-		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
-	}
-
-#define TGL_CURSOR_OFFSETS \
-	.cursor_offsets = { \
-		[PIPE_A] = CURSOR_A_OFFSET, \
-		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
-		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
-		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
-	}
-
-#define I845_COLORS \
-	.color = { .gamma_lut_size = 256 }
-#define I9XX_COLORS \
-	.color = { .gamma_lut_size = 129, \
-		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
-	}
-#define ILK_COLORS \
-	.color = { .gamma_lut_size = 1024 }
-#define IVB_COLORS \
-	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
-#define CHV_COLORS \
-	.color = { \
-		.degamma_lut_size = 65, .gamma_lut_size = 257, \
-		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
-		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
-	}
-#define GLK_COLORS \
-	.color = { \
-		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
-		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
-				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
-	}
-#define ICL_COLORS \
-	.color = { \
-		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
-		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
-				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
-		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
-	}
-
 #define LEGACY_CACHELEVEL \
 	.cachelevel_to_pat = { \
 		[I915_CACHE_NONE]   = 0, \
@@ -206,23 +83,6 @@ static const struct intel_display_device_info no_display = { 0 };
 #define GEN_DEFAULT_REGIONS \
 	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
 
-#define I830_DISPLAY \
-	.has_overlay = 1, \
-	.cursor_needs_physical = 1, \
-	.overlay_needs_physical = 1, \
-	.has_gmch = 1, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS, \
-	\
-	.__runtime.ip.ver = 2, \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
-
-static const struct intel_display_device_info i830_display = {
-	I830_DISPLAY,
-};
-
 #define I830_FEATURES \
 	GEN(2), \
 	.is_mobile = 1, \
@@ -239,22 +99,6 @@ static const struct intel_display_device_info i830_display = {
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
 
-#define I845_DISPLAY \
-	.has_overlay = 1, \
-	.overlay_needs_physical = 1, \
-	.has_gmch = 1, \
-	I845_PIPE_OFFSETS, \
-	I845_CURSOR_OFFSETS, \
-	I845_COLORS, \
-	\
-	.__runtime.ip.ver = 2, \
-	.__runtime.pipe_mask = BIT(PIPE_A), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A)
-
-static const struct intel_display_device_info i845_display = {
-	I845_DISPLAY,
-};
-
 #define I845_FEATURES \
 	GEN(2), \
 	.has_3d_pipeline = 1, \
@@ -273,85 +117,21 @@ static const struct intel_display_device_info i845_display = {
 static const struct intel_device_info i830_info = {
 	I830_FEATURES,
 	PLATFORM(INTEL_I830),
-	.display = &i830_display,
 };
 
 static const struct intel_device_info i845g_info = {
 	I845_FEATURES,
 	PLATFORM(INTEL_I845G),
-	.display = &i845_display,
-};
-
-static const struct intel_display_device_info i85x_display = {
-	I830_DISPLAY,
-
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info i85x_info = {
 	I830_FEATURES,
 	PLATFORM(INTEL_I85X),
-	.display = &i85x_display,
-};
-
-static const struct intel_display_device_info i865g_display = {
-	I845_DISPLAY,
-
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info i865g_info = {
 	I845_FEATURES,
 	PLATFORM(INTEL_I865G),
-	.display = &i865g_display,
-};
-
-#define GEN3_DISPLAY \
-	.has_gmch = 1, \
-	.has_overlay = 1, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS, \
-	\
-	.__runtime.ip.ver = 3, \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
-
-static const struct intel_display_device_info i915g_display = {
-	GEN3_DISPLAY,
-	.cursor_needs_physical = 1,
-	.overlay_needs_physical = 1,
-};
-
-static const struct intel_display_device_info i915gm_display = {
-	GEN3_DISPLAY,
-	.cursor_needs_physical = 1,
-	.overlay_needs_physical = 1,
-	.supports_tv = 1,
-
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
-static const struct intel_display_device_info i945g_display = {
-	GEN3_DISPLAY,
-	.has_hotplug = 1,
-	.cursor_needs_physical = 1,
-	.overlay_needs_physical = 1,
-};
-
-static const struct intel_display_device_info i945gm_display = {
-	GEN3_DISPLAY,
-	.has_hotplug = 1,
-	.cursor_needs_physical = 1,
-	.overlay_needs_physical = 1,
-	.supports_tv = 1,
-
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
-static const struct intel_display_device_info g33_display = {
-	GEN3_DISPLAY,
-	.has_hotplug = 1,
 };
 
 #define GEN3_FEATURES \
@@ -370,7 +150,6 @@ static const struct intel_display_device_info g33_display = {
 static const struct intel_device_info i915g_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I915G),
-	.display = &i915g_display,
 	.has_coherent_ggtt = false,
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
@@ -379,7 +158,6 @@ static const struct intel_device_info i915g_info = {
 static const struct intel_device_info i915gm_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I915GM),
-	.display = &i915gm_display,
 	.is_mobile = 1,
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
@@ -388,7 +166,6 @@ static const struct intel_device_info i915gm_info = {
 static const struct intel_device_info i945g_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I945G),
-	.display = &i945g_display,
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
@@ -396,7 +173,6 @@ static const struct intel_device_info i945g_info = {
 static const struct intel_device_info i945gm_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I945GM),
-	.display = &i945gm_display,
 	.is_mobile = 1,
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
@@ -405,14 +181,12 @@ static const struct intel_device_info i945gm_info = {
 static const struct intel_device_info g33_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_G33),
-	.display = &g33_display,
 	.dma_mask_size = 36,
 };
 
 static const struct intel_device_info pnv_g_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_PINEVIEW),
-	.display = &g33_display,
 	.dma_mask_size = 36,
 };
 
@@ -420,45 +194,9 @@ static const struct intel_device_info pnv_m_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_PINEVIEW),
 	.is_mobile = 1,
-	.display = &g33_display,
 	.dma_mask_size = 36,
 };
 
-#define GEN4_DISPLAY \
-	.has_hotplug = 1, \
-	.has_gmch = 1, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	I9XX_COLORS, \
-	\
-	.__runtime.ip.ver = 4, \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
-
-static const struct intel_display_device_info i965g_display = {
-	GEN4_DISPLAY,
-	.has_overlay = 1,
-};
-
-static const struct intel_display_device_info i965gm_display = {
-	GEN4_DISPLAY,
-	.has_overlay = 1,
-	.supports_tv = 1,
-
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
-static const struct intel_display_device_info g45_display = {
-	GEN4_DISPLAY,
-};
-
-static const struct intel_display_device_info gm45_display = {
-	GEN4_DISPLAY,
-	.supports_tv = 1,
-
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
 #define GEN4_FEATURES \
 	GEN(4), \
 	.gpu_reset_clobbers_display = true, \
@@ -475,7 +213,6 @@ static const struct intel_display_device_info gm45_display = {
 static const struct intel_device_info i965g_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_I965G),
-	.display = &i965g_display,
 	.hws_needs_physical = 1,
 	.has_snoop = false,
 };
@@ -483,7 +220,6 @@ static const struct intel_device_info i965g_info = {
 static const struct intel_device_info i965gm_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_I965GM),
-	.display = &i965gm_display,
 	.is_mobile = 1,
 	.hws_needs_physical = 1,
 	.has_snoop = false,
@@ -493,7 +229,6 @@ static const struct intel_device_info g45_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_G45),
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
-	.display = &g45_display,
 	.gpu_reset_clobbers_display = false,
 };
 
@@ -502,7 +237,6 @@ static const struct intel_device_info gm45_info = {
 	PLATFORM(INTEL_GM45),
 	.is_mobile = 1,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
-	.display = &gm45_display,
 	.gpu_reset_clobbers_display = false,
 };
 
@@ -520,36 +254,14 @@ static const struct intel_device_info gm45_info = {
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
 
-#define ILK_DISPLAY \
-	.has_hotplug = 1, \
-	I9XX_PIPE_OFFSETS, \
-	I9XX_CURSOR_OFFSETS, \
-	ILK_COLORS, \
-	\
-	.__runtime.ip.ver = 5, \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
-
-static const struct intel_display_device_info ilk_d_display = {
-	ILK_DISPLAY,
-};
-
 static const struct intel_device_info ilk_d_info = {
 	GEN5_FEATURES,
 	PLATFORM(INTEL_IRONLAKE),
-	.display = &ilk_d_display,
-};
-
-static const struct intel_display_device_info ilk_m_display = {
-	ILK_DISPLAY,
-
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
 };
 
 static const struct intel_device_info ilk_m_info = {
 	GEN5_FEATURES,
 	PLATFORM(INTEL_IRONLAKE),
-	.display = &ilk_m_display,
 	.is_mobile = 1,
 	.has_rps = true,
 };
@@ -572,31 +284,17 @@ static const struct intel_device_info ilk_m_info = {
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
 
-static const struct intel_display_device_info snb_display = {
-	.has_hotplug = 1,
-	I9XX_PIPE_OFFSETS,
-	I9XX_CURSOR_OFFSETS,
-	ILK_COLORS,
-
-	.__runtime.ip.ver = 6,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
 #define SNB_D_PLATFORM \
 	GEN6_FEATURES, \
 	PLATFORM(INTEL_SANDYBRIDGE)
 
 static const struct intel_device_info snb_d_gt1_info = {
 	SNB_D_PLATFORM,
-	.display = &snb_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info snb_d_gt2_info = {
 	SNB_D_PLATFORM,
-	.display = &snb_display,
 	.gt = 2,
 };
 
@@ -608,13 +306,11 @@ static const struct intel_device_info snb_d_gt2_info = {
 
 static const struct intel_device_info snb_m_gt1_info = {
 	SNB_M_PLATFORM,
-	.display = &snb_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info snb_m_gt2_info = {
 	SNB_M_PLATFORM,
-	.display = &snb_display,
 	.gt = 2,
 };
 
@@ -641,28 +337,13 @@ static const struct intel_device_info snb_m_gt2_info = {
 	PLATFORM(INTEL_IVYBRIDGE), \
 	.has_l3_dpf = 1
 
-static const struct intel_display_device_info ivb_display = {
-	.has_hotplug = 1,
-	IVB_PIPE_OFFSETS,
-	IVB_CURSOR_OFFSETS,
-	IVB_COLORS,
-
-	.__runtime.ip.ver = 7,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-		BIT(TRANSCODER_C),
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
 static const struct intel_device_info ivb_d_gt1_info = {
 	IVB_D_PLATFORM,
-	.display = &ivb_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info ivb_d_gt2_info = {
 	IVB_D_PLATFORM,
-	.display = &ivb_display,
 	.gt = 2,
 };
 
@@ -674,42 +355,25 @@ static const struct intel_device_info ivb_d_gt2_info = {
 
 static const struct intel_device_info ivb_m_gt1_info = {
 	IVB_M_PLATFORM,
-	.display = &ivb_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info ivb_m_gt2_info = {
 	IVB_M_PLATFORM,
-	.display = &ivb_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info ivb_q_info = {
 	GEN7_FEATURES,
 	PLATFORM(INTEL_IVYBRIDGE),
-	NO_DISPLAY,
 	.gt = 2,
 	.has_l3_dpf = 1,
 };
 
-static const struct intel_display_device_info vlv_display = {
-	.has_gmch = 1,
-	.has_hotplug = 1,
-	.mmio_offset = VLV_DISPLAY_BASE,
-	I9XX_PIPE_OFFSETS,
-	I9XX_CURSOR_OFFSETS,
-	I9XX_COLORS,
-
-	.__runtime.ip.ver = 7,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
-};
-
 static const struct intel_device_info vlv_info = {
 	PLATFORM(INTEL_VALLEYVIEW),
 	GEN(7),
 	.is_lp = 1,
-	.display = &vlv_display,
 	.has_runtime_pm = 1,
 	.has_rc6 = 1,
 	.has_reset_engine = true,
@@ -737,37 +401,18 @@ static const struct intel_device_info vlv_info = {
 	PLATFORM(INTEL_HASWELL), \
 	.has_l3_dpf = 1
 
-static const struct intel_display_device_info hsw_display = {
-	.has_ddi = 1,
-	.has_dp_mst = 1,
-	.has_fpga_dbg = 1,
-	.has_hotplug = 1,
-	HSW_PIPE_OFFSETS,
-	IVB_CURSOR_OFFSETS,
-	IVB_COLORS,
-
-	.__runtime.ip.ver = 7,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
 static const struct intel_device_info hsw_gt1_info = {
 	HSW_PLATFORM,
-	.display = &hsw_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info hsw_gt2_info = {
 	HSW_PLATFORM,
-	.display = &hsw_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info hsw_gt3_info = {
 	HSW_PLATFORM,
-	.display = &hsw_display,
 	.gt = 3,
 };
 
@@ -780,41 +425,22 @@ static const struct intel_device_info hsw_gt3_info = {
 	.__runtime.ppgtt_size = 48, \
 	.has_64bit_reloc = 1
 
-static const struct intel_display_device_info bdw_display = {
-	.has_ddi = 1,
-	.has_dp_mst = 1,
-	.has_fpga_dbg = 1,
-	.has_hotplug = 1,
-	HSW_PIPE_OFFSETS,
-	IVB_CURSOR_OFFSETS,
-	IVB_COLORS,
-
-	.__runtime.ip.ver = 8,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
 #define BDW_PLATFORM \
 	GEN8_FEATURES, \
 	PLATFORM(INTEL_BROADWELL)
 
 static const struct intel_device_info bdw_gt1_info = {
 	BDW_PLATFORM,
-	.display = &bdw_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info bdw_gt2_info = {
 	BDW_PLATFORM,
-	.display = &bdw_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info bdw_rsvd_info = {
 	BDW_PLATFORM,
-	.display = &bdw_display,
 	.gt = 3,
 	/* According to the device ID those devices are GT3, they were
 	 * previously treated as not GT3, keep it like that.
@@ -823,30 +449,14 @@ static const struct intel_device_info bdw_rsvd_info = {
 
 static const struct intel_device_info bdw_gt3_info = {
 	BDW_PLATFORM,
-	.display = &bdw_display,
 	.gt = 3,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 };
 
-static const struct intel_display_device_info chv_display = {
-	.has_hotplug = 1,
-	.has_gmch = 1,
-	.mmio_offset = VLV_DISPLAY_BASE,
-	CHV_PIPE_OFFSETS,
-	CHV_CURSOR_OFFSETS,
-	CHV_COLORS,
-
-	.__runtime.ip.ver = 8,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-		BIT(TRANSCODER_C),
-};
-
 static const struct intel_device_info chv_info = {
 	PLATFORM(INTEL_CHERRYVIEW),
 	GEN(8),
-	.display = &chv_display,
 	.is_lp = 1,
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 	.has_64bit_reloc = 1,
@@ -876,42 +486,17 @@ static const struct intel_device_info chv_info = {
 	GEN9_DEFAULT_PAGE_SIZES, \
 	.has_gt_uc = 1
 
-static const struct intel_display_device_info skl_display = {
-	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
-	.dbuf.slice_mask = BIT(DBUF_S1),
-	.has_ddi = 1,
-	.has_dp_mst = 1,
-	.has_fpga_dbg = 1,
-	.has_hotplug = 1,
-	.has_ipc = 1,
-	.has_psr = 1,
-	.has_psr_hw_tracking = 1,
-	HSW_PIPE_OFFSETS,
-	IVB_CURSOR_OFFSETS,
-	IVB_COLORS,
-
-	.__runtime.ip.ver = 9,
-	.__runtime.has_dmc = 1,
-	.__runtime.has_hdcp = 1,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
 #define SKL_PLATFORM \
 	GEN9_FEATURES, \
 	PLATFORM(INTEL_SKYLAKE)
 
 static const struct intel_device_info skl_gt1_info = {
 	SKL_PLATFORM,
-	.display = &skl_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info skl_gt2_info = {
 	SKL_PLATFORM,
-	.display = &skl_display,
 	.gt = 2,
 };
 
@@ -923,13 +508,11 @@ static const struct intel_device_info skl_gt2_info = {
 
 static const struct intel_device_info skl_gt3_info = {
 	SKL_GT3_PLUS_PLATFORM,
-	.display = &skl_display,
 	.gt = 3,
 };
 
 static const struct intel_device_info skl_gt4_info = {
 	SKL_GT3_PLUS_PLATFORM,
-	.display = &skl_display,
 	.gt = 4,
 };
 
@@ -955,52 +538,14 @@ static const struct intel_device_info skl_gt4_info = {
 	GEN_DEFAULT_REGIONS, \
 	LEGACY_CACHELEVEL
 
-#define GEN9_LP_DISPLAY \
-	.dbuf.slice_mask = BIT(DBUF_S1), \
-	.has_dp_mst = 1, \
-	.has_ddi = 1, \
-	.has_fpga_dbg = 1, \
-	.has_hotplug = 1, \
-	.has_ipc = 1, \
-	.has_psr = 1, \
-	.has_psr_hw_tracking = 1, \
-	HSW_PIPE_OFFSETS, \
-	IVB_CURSOR_OFFSETS, \
-	IVB_COLORS, \
-	\
-	.__runtime.has_dmc = 1, \
-	.__runtime.has_hdcp = 1, \
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
-		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
-
-static const struct intel_display_device_info bxt_display = {
-	GEN9_LP_DISPLAY,
-	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
-
-	.__runtime.ip.ver = 9,
-};
-
 static const struct intel_device_info bxt_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
-	.display = &bxt_display,
-};
-
-static const struct intel_display_device_info glk_display = {
-	GEN9_LP_DISPLAY,
-	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
-	GLK_COLORS,
-
-	.__runtime.ip.ver = 10,
 };
 
 static const struct intel_device_info glk_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
-	.display = &glk_display,
 };
 
 #define KBL_PLATFORM \
@@ -1009,19 +554,16 @@ static const struct intel_device_info glk_info = {
 
 static const struct intel_device_info kbl_gt1_info = {
 	KBL_PLATFORM,
-	.display = &skl_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info kbl_gt2_info = {
 	KBL_PLATFORM,
-	.display = &skl_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info kbl_gt3_info = {
 	KBL_PLATFORM,
-	.display = &skl_display,
 	.gt = 3,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
@@ -1033,19 +575,16 @@ static const struct intel_device_info kbl_gt3_info = {
 
 static const struct intel_device_info cfl_gt1_info = {
 	CFL_PLATFORM,
-	.display = &skl_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info cfl_gt2_info = {
 	CFL_PLATFORM,
-	.display = &skl_display,
 	.gt = 2,
 };
 
 static const struct intel_device_info cfl_gt3_info = {
 	CFL_PLATFORM,
-	.display = &skl_display,
 	.gt = 3,
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
@@ -1057,13 +596,11 @@ static const struct intel_device_info cfl_gt3_info = {
 
 static const struct intel_device_info cml_gt1_info = {
 	CML_PLATFORM,
-	.display = &skl_display,
 	.gt = 1,
 };
 
 static const struct intel_device_info cml_gt2_info = {
 	CML_PLATFORM,
-	.display = &skl_display,
 	.gt = 2,
 };
 
@@ -1079,53 +616,11 @@ static const struct intel_device_info cml_gt2_info = {
 	.has_coherent_ggtt = false, \
 	.has_logical_ring_elsq = 1
 
-static const struct intel_display_device_info gen11_display = {
-	.abox_mask = BIT(0),
-	.dbuf.size = 2048,
-	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
-	.has_ddi = 1,
-	.has_dp_mst = 1,
-	.has_fpga_dbg = 1,
-	.has_hotplug = 1,
-	.has_ipc = 1,
-	.has_psr = 1,
-	.has_psr_hw_tracking = 1,
-	.pipe_offsets = {
-		[TRANSCODER_A] = PIPE_A_OFFSET,
-		[TRANSCODER_B] = PIPE_B_OFFSET,
-		[TRANSCODER_C] = PIPE_C_OFFSET,
-		[TRANSCODER_EDP] = PIPE_EDP_OFFSET,
-		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
-		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
-	},
-	.trans_offsets = {
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
-		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
-		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
-		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
-		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
-		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
-	},
-	IVB_CURSOR_OFFSETS,
-	ICL_COLORS,
-
-	.__runtime.ip.ver = 11,
-	.__runtime.has_dmc = 1,
-	.__runtime.has_dsc = 1, \
-	.__runtime.has_hdcp = 1,
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
-		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
-};
-
 static const struct intel_device_info icl_info = {
 	GEN11_FEATURES,
 	PLATFORM(INTEL_ICELAKE),
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
-	.display = &gen11_display,
 };
 
 static const struct intel_device_info ehl_info = {
@@ -1133,7 +628,6 @@ static const struct intel_device_info ehl_info = {
 	PLATFORM(INTEL_ELKHARTLAKE),
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 	.__runtime.ppgtt_size = 36,
-	.display = &gen11_display,
 };
 
 static const struct intel_device_info jsl_info = {
@@ -1141,7 +635,6 @@ static const struct intel_device_info jsl_info = {
 	PLATFORM(INTEL_JASPERLAKE),
 	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 	.__runtime.ppgtt_size = 36,
-	.display = &gen11_display,
 };
 
 #define GEN12_FEATURES \
@@ -1152,68 +645,11 @@ static const struct intel_device_info jsl_info = {
 	.has_pxp = 1, \
 	.max_pat_index = 3
 
-#define XE_D_DISPLAY \
-	.abox_mask = GENMASK(2, 1), \
-	.dbuf.size = 2048, \
-	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
-	.has_ddi = 1, \
-	.has_dp_mst = 1, \
-	.has_dsb = 1, \
-	.has_fpga_dbg = 1, \
-	.has_hotplug = 1, \
-	.has_ipc = 1, \
-	.has_psr = 1, \
-	.has_psr_hw_tracking = 1, \
-	.pipe_offsets = { \
-		[TRANSCODER_A] = PIPE_A_OFFSET, \
-		[TRANSCODER_B] = PIPE_B_OFFSET, \
-		[TRANSCODER_C] = PIPE_C_OFFSET, \
-		[TRANSCODER_D] = PIPE_D_OFFSET, \
-		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
-		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
-	}, \
-	.trans_offsets = { \
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
-		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
-		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
-		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
-		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
-		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
-	}, \
-	TGL_CURSOR_OFFSETS, \
-	ICL_COLORS, \
-	\
-	.__runtime.ip.ver = 12, \
-	.__runtime.has_dmc = 1, \
-	.__runtime.has_dsc = 1, \
-	.__runtime.has_hdcp = 1, \
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
-		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
-		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A)
-
-static const struct intel_display_device_info tgl_display = {
-	XE_D_DISPLAY,
-};
-
 static const struct intel_device_info tgl_info = {
 	GEN12_FEATURES,
 	PLATFORM(INTEL_TIGERLAKE),
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
-	.display = &tgl_display,
-};
-
-static const struct intel_display_device_info rkl_display = {
-	XE_D_DISPLAY,
-	.abox_mask = BIT(0),
-	.has_hti = 1,
-	.has_psr_hw_tracking = 0,
-
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-		BIT(TRANSCODER_C),
 };
 
 static const struct intel_device_info rkl_info = {
@@ -1221,7 +657,6 @@ static const struct intel_device_info rkl_info = {
 	PLATFORM(INTEL_ROCKETLAKE),
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
-	.display = &rkl_display,
 };
 
 #define DGFX_FEATURES \
@@ -1243,13 +678,6 @@ static const struct intel_device_info dg1_info = {
 		BIT(VCS0) | BIT(VCS2),
 	/* Wa_16011227922 */
 	.__runtime.ppgtt_size = 47,
-	.display = &tgl_display,
-};
-
-static const struct intel_display_device_info adl_s_display = {
-	XE_D_DISPLAY,
-	.has_hti = 1,
-	.has_psr_hw_tracking = 0,
 };
 
 static const struct intel_device_info adl_s_info = {
@@ -1258,59 +686,6 @@ static const struct intel_device_info adl_s_info = {
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.dma_mask_size = 39,
-	.display = &adl_s_display,
-};
-
-#define XE_LPD_FEATURES \
-	.abox_mask = GENMASK(1, 0),						\
-	.color = {								\
-		.degamma_lut_size = 129, .gamma_lut_size = 1024,		\
-		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
-		DRM_COLOR_LUT_EQUAL_CHANNELS,					\
-	},									\
-	.dbuf.size = 4096,							\
-	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
-		BIT(DBUF_S4),							\
-	.has_ddi = 1,								\
-	.has_dp_mst = 1,							\
-	.has_dsb = 1,								\
-	.has_fpga_dbg = 1,							\
-	.has_hotplug = 1,							\
-	.has_ipc = 1,								\
-	.has_psr = 1,								\
-	.pipe_offsets = {							\
-		[TRANSCODER_A] = PIPE_A_OFFSET,					\
-		[TRANSCODER_B] = PIPE_B_OFFSET,					\
-		[TRANSCODER_C] = PIPE_C_OFFSET,					\
-		[TRANSCODER_D] = PIPE_D_OFFSET,					\
-		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
-		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
-	},									\
-	.trans_offsets = {						\
-		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
-		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
-		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
-		[TRANSCODER_D] = TRANSCODER_D_OFFSET,				\
-		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
-		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
-	},									\
-	TGL_CURSOR_OFFSETS,							\
-										\
-	.__runtime.ip.ver = 13,							\
-	.__runtime.has_dmc = 1,							\
-	.__runtime.has_dsc = 1,							\
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
-	.__runtime.has_hdcp = 1,						\
-	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
-
-static const struct intel_display_device_info xe_lpd_display = {
-	XE_LPD_FEATURES,
-	.has_cdclk_crawl = 1,
-	.has_psr_hw_tracking = 0,
-
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
-			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
 };
 
 static const struct intel_device_info adl_p_info = {
@@ -1319,7 +694,6 @@ static const struct intel_device_info adl_p_info = {
 	.__runtime.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.__runtime.ppgtt_size = 48,
-	.display = &xe_lpd_display,
 	.dma_mask_size = 39,
 };
 
@@ -1367,7 +741,6 @@ static const struct intel_device_info xehpsdv_info = {
 	XE_HPM_FEATURES,
 	DGFX_FEATURES,
 	PLATFORM(INTEL_XEHPSDV),
-	NO_DISPLAY,
 	.has_64k_pages = 1,
 	.has_media_ratio_mode = 1,
 	.__runtime.platform_engine_mask =
@@ -1396,22 +769,12 @@ static const struct intel_device_info xehpsdv_info = {
 		BIT(VCS0) | BIT(VCS2) | \
 		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
 
-static const struct intel_display_device_info xe_hpd_display = {
-	XE_LPD_FEATURES,
-	.has_cdclk_squash = 1,
-
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
-};
-
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
-	.display = &xe_hpd_display,
 };
 
 static const struct intel_device_info ats_m_info = {
 	DG2_FEATURES,
-	NO_DISPLAY,
 	.require_force_probe = 1,
 	.tuning_thread_rr_after_dep = 1,
 };
@@ -1433,7 +796,6 @@ static const struct intel_device_info pvc_info = {
 	.__runtime.graphics.ip.rel = 60,
 	.__runtime.media.ip.rel = 60,
 	PLATFORM(INTEL_PONTEVECCHIO),
-	NO_DISPLAY,
 	.has_flat_ccs = 0,
 	.max_pat_index = 7,
 	.__runtime.platform_engine_mask =
@@ -1454,17 +816,6 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
 	{}
 };
 
-static const struct intel_display_device_info xe_lpdp_display = {
-	XE_LPD_FEATURES,
-	.has_cdclk_crawl = 1,
-	.has_cdclk_squash = 1,
-
-	.__runtime.ip.ver = 14,
-	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
-	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
-			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
-};
-
 static const struct intel_device_info mtl_info = {
 	XE_HP_FEATURES,
 	/*
@@ -1475,7 +826,6 @@ static const struct intel_device_info mtl_info = {
 	.__runtime.graphics.ip.rel = 70,
 	.__runtime.media.ip.ver = 13,
 	PLATFORM(INTEL_METEORLAKE),
-	.display = &xe_lpdp_display,
 	.extra_gt_list = xelpmp_extra_gt,
 	.has_flat_ccs = 0,
 	.has_gmd_id = 1,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a9ab8de8421..f1ba1eae26ca 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1966,15 +1966,6 @@
 #define _TRANS_VSYNC_DSI1	0x6b814
 #define _TRANS_VSYNCSHIFT_DSI1	0x6b828
 
-#define TRANSCODER_A_OFFSET 0x60000
-#define TRANSCODER_B_OFFSET 0x61000
-#define TRANSCODER_C_OFFSET 0x62000
-#define CHV_TRANSCODER_C_OFFSET 0x63000
-#define TRANSCODER_D_OFFSET 0x63000
-#define TRANSCODER_EDP_OFFSET 0x6f000
-#define TRANSCODER_DSI0_OFFSET	0x6b000
-#define TRANSCODER_DSI1_OFFSET	0x6b800
-
 #define TRANS_HTOTAL(trans)	_MMIO_TRANS2((trans), _TRANS_HTOTAL_A)
 #define TRANS_HBLANK(trans)	_MMIO_TRANS2((trans), _TRANS_HBLANK_A)
 #define TRANS_HSYNC(trans)	_MMIO_TRANS2((trans), _TRANS_HSYNC_A)
@@ -2622,23 +2613,6 @@
 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
 
-#define PIPE_A_OFFSET		0x70000
-#define PIPE_B_OFFSET		0x71000
-#define PIPE_C_OFFSET		0x72000
-#define PIPE_D_OFFSET		0x73000
-#define CHV_PIPE_C_OFFSET	0x74000
-/*
- * There's actually no pipe EDP. Some pipe registers have
- * simply shifted from the pipe to the transcoder, while
- * keeping their original offset. Thus we need PIPE_EDP_OFFSET
- * to access such registers in transcoder EDP.
- */
-#define PIPE_EDP_OFFSET	0x7f000
-
-/* ICL DSI 0 and 1 */
-#define PIPE_DSI0_OFFSET	0x7b000
-#define PIPE_DSI1_OFFSET	0x7b800
-
 #define TRANSCONF(trans)	_MMIO_PIPE2((trans), _TRANSACONF)
 #define PIPEDSL(pipe)		_MMIO_PIPE2(pipe, _PIPEADSL)
 #define PIPEFRAME(pipe)		_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
@@ -3099,13 +3073,6 @@
 #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A)
 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
 
-#define CURSOR_A_OFFSET 0x70080
-#define CURSOR_B_OFFSET 0x700c0
-#define CHV_CURSOR_C_OFFSET 0x700e0
-#define IVB_CURSOR_B_OFFSET 0x71080
-#define IVB_CURSOR_C_OFFSET 0x72080
-#define TGL_CURSOR_D_OFFSET 0x73080
-
 /* Display A control */
 #define _DSPAADDR_VLV				0x7017C /* vlv/chv */
 #define _DSPACNTR				0x70180
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e10907ddbade..9d0b54ba50c1 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -583,9 +583,16 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
 	/* Initialize initial runtime info from static const data and pdev. */
 	runtime = RUNTIME_INFO(i915);
 	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
-	display_runtime = DISPLAY_RUNTIME_INFO(i915);
-	memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
-	       sizeof(*display_runtime));
+
+	/* Probe display support */
+	info->display = intel_display_device_probe(device_id);
+	if (info->display) {
+		display_runtime = DISPLAY_RUNTIME_INFO(i915);
+		memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
+		       sizeof(*display_runtime));
+	} else {
+		info->display = &no_display;
+	}
 
 	runtime->device_id = device_id;
 }
-- 
2.40.0


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 4/5] drm/i915/display: Make display responsible for probing its own IP
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 4/5] drm/i915/display: Make display responsible for probing its own IP Matt Roper
@ 2023-05-18 10:01   ` Andrzej Hajda
  0 siblings, 0 replies; 21+ messages in thread
From: Andrzej Hajda @ 2023-05-18 10:01 UTC (permalink / raw)
  To: Matt Roper, intel-gfx; +Cc: intel-xe

On 18.05.2023 05:18, Matt Roper wrote:
> Rather than selecting the display IP and feature flags at the same time
> the general PCI probing happens, move this step into the display code
> itself so that it can be more easily re-used outside of i915 (i.e., by
> the Xe driver).
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile                 |   2 +
>   .../drm/i915/display/intel_display_device.c   | 692 ++++++++++++++++++
>   .../drm/i915/display/intel_display_device.h   |   3 +
>   drivers/gpu/drm/i915/i915_pci.c               | 650 ----------------
>   drivers/gpu/drm/i915/i915_reg.h               |  33 -
>   drivers/gpu/drm/i915/intel_device_info.c      |  13 +-
>   6 files changed, 707 insertions(+), 686 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.c
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index dd9ca69f4998..06374fc072d3 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -25,6 +25,7 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
>   
>   # Fine grained warnings disable
>   CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
> +CFLAGS_display/intel_display_device.o = $(call cc-disable-warning, override-init)
>   CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
>   
>   subdir-ccflags-y += -I$(srctree)/$(src)
> @@ -308,6 +309,7 @@ i915-y += \
>   	display/intel_cx0_phy.o \
>   	display/intel_ddi.o \
>   	display/intel_ddi_buf_trans.o \
> +	display/intel_display_device.o \
>   	display/intel_display_trace.o \
>   	display/intel_dkl_phy.o \
>   	display/intel_dp.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> new file mode 100644
> index 000000000000..78fa522aaf0b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -0,0 +1,692 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <drm/i915_pciids.h>
> +#include <drm/drm_color_mgmt.h>
> +#include <linux/mod_devicetable.h>
> +
> +#include "intel_display_device.h"
> +#include "intel_display_power.h"
> +#include "intel_display_reg_defs.h"
> +#include "intel_fbc.h"
> +
> +#define PIPE_A_OFFSET		0x70000
> +#define PIPE_B_OFFSET		0x71000
> +#define PIPE_C_OFFSET		0x72000
> +#define PIPE_D_OFFSET		0x73000
> +#define CHV_PIPE_C_OFFSET	0x74000
> +/*
> + * There's actually no pipe EDP. Some pipe registers have
> + * simply shifted from the pipe to the transcoder, while
> + * keeping their original offset. Thus we need PIPE_EDP_OFFSET
> + * to access such registers in transcoder EDP.
> + */
> +#define PIPE_EDP_OFFSET	0x7f000
> +
> +/* ICL DSI 0 and 1 */
> +#define PIPE_DSI0_OFFSET	0x7b000
> +#define PIPE_DSI1_OFFSET	0x7b800
> +
> +#define TRANSCODER_A_OFFSET 0x60000
> +#define TRANSCODER_B_OFFSET 0x61000
> +#define TRANSCODER_C_OFFSET 0x62000
> +#define CHV_TRANSCODER_C_OFFSET 0x63000
> +#define TRANSCODER_D_OFFSET 0x63000
> +#define TRANSCODER_EDP_OFFSET 0x6f000
> +#define TRANSCODER_DSI0_OFFSET	0x6b000
> +#define TRANSCODER_DSI1_OFFSET	0x6b800
> +
> +#define CURSOR_A_OFFSET 0x70080
> +#define CURSOR_B_OFFSET 0x700c0
> +#define CHV_CURSOR_C_OFFSET 0x700e0
> +#define IVB_CURSOR_B_OFFSET 0x71080
> +#define IVB_CURSOR_C_OFFSET 0x72080
> +#define TGL_CURSOR_D_OFFSET 0x73080
> +
> +#define I845_PIPE_OFFSETS \
> +	.pipe_offsets = { \
> +		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> +	}, \
> +	.trans_offsets = { \
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> +	}
> +
> +#define I9XX_PIPE_OFFSETS \
> +	.pipe_offsets = { \
> +		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> +		[TRANSCODER_B] = PIPE_B_OFFSET, \
> +	}, \
> +	.trans_offsets = { \
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> +	}
> +
> +#define IVB_PIPE_OFFSETS \
> +	.pipe_offsets = { \
> +		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> +		[TRANSCODER_B] = PIPE_B_OFFSET, \
> +		[TRANSCODER_C] = PIPE_C_OFFSET, \
> +	}, \
> +	.trans_offsets = { \
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> +		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> +	}
> +
> +#define HSW_PIPE_OFFSETS \
> +	.pipe_offsets = { \
> +		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> +		[TRANSCODER_B] = PIPE_B_OFFSET, \
> +		[TRANSCODER_C] = PIPE_C_OFFSET, \
> +		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> +	}, \
> +	.trans_offsets = { \
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> +		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> +		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> +	}
> +
> +#define CHV_PIPE_OFFSETS \
> +	.pipe_offsets = { \
> +		[TRANSCODER_A] = PIPE_A_OFFSET, \
> +		[TRANSCODER_B] = PIPE_B_OFFSET, \
> +		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> +	}, \
> +	.trans_offsets = { \
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> +		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> +	}
> +
> +#define I845_CURSOR_OFFSETS \
> +	.cursor_offsets = { \
> +		[PIPE_A] = CURSOR_A_OFFSET, \
> +	}
> +
> +#define I9XX_CURSOR_OFFSETS \
> +	.cursor_offsets = { \
> +		[PIPE_A] = CURSOR_A_OFFSET, \
> +		[PIPE_B] = CURSOR_B_OFFSET, \
> +	}
> +
> +#define CHV_CURSOR_OFFSETS \
> +	.cursor_offsets = { \
> +		[PIPE_A] = CURSOR_A_OFFSET, \
> +		[PIPE_B] = CURSOR_B_OFFSET, \
> +		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
> +	}
> +
> +#define IVB_CURSOR_OFFSETS \
> +	.cursor_offsets = { \
> +		[PIPE_A] = CURSOR_A_OFFSET, \
> +		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
> +		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
> +	}
> +
> +#define TGL_CURSOR_OFFSETS \
> +	.cursor_offsets = { \
> +		[PIPE_A] = CURSOR_A_OFFSET, \
> +		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
> +		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
> +		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
> +	}
> +
> +#define I845_COLORS \
> +	.color = { .gamma_lut_size = 256 }
> +#define I9XX_COLORS \
> +	.color = { .gamma_lut_size = 129, \
> +		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> +	}
> +#define ILK_COLORS \
> +	.color = { .gamma_lut_size = 1024 }
> +#define IVB_COLORS \
> +	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> +#define CHV_COLORS \
> +	.color = { \
> +		.degamma_lut_size = 65, .gamma_lut_size = 257, \
> +		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> +		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> +	}
> +#define GLK_COLORS \
> +	.color = { \
> +		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
> +		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> +				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
> +	}
> +#define ICL_COLORS \
> +	.color = { \
> +		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
> +		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> +				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
> +		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> +	}
> +
> +#define I830_DISPLAY \
> +	.has_overlay = 1, \
> +	.cursor_needs_physical = 1, \
> +	.overlay_needs_physical = 1, \
> +	.has_gmch = 1, \
> +	I9XX_PIPE_OFFSETS, \
> +	I9XX_CURSOR_OFFSETS, \
> +	I9XX_COLORS, \
> +	\
> +	.__runtime.ip.ver = 2, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> +
> +static const struct intel_display_device_info i830_display = {
> +	I830_DISPLAY,
> +};
> +
> +#define I845_DISPLAY \
> +	.has_overlay = 1, \
> +	.overlay_needs_physical = 1, \
> +	.has_gmch = 1, \
> +	I845_PIPE_OFFSETS, \
> +	I845_CURSOR_OFFSETS, \
> +	I845_COLORS, \
> +	\
> +	.__runtime.ip.ver = 2, \
> +	.__runtime.pipe_mask = BIT(PIPE_A), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A)
> +
> +static const struct intel_display_device_info i845_display = {
> +	I845_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info i85x_display = {
> +	I830_DISPLAY,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info i865g_display = {
> +	I845_DISPLAY,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +#define GEN3_DISPLAY \
> +	.has_gmch = 1, \
> +	.has_overlay = 1, \
> +	I9XX_PIPE_OFFSETS, \
> +	I9XX_CURSOR_OFFSETS, \
> +	I9XX_COLORS, \
> +	\
> +	.__runtime.ip.ver = 3, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> +
> +static const struct intel_display_device_info i915g_display = {
> +	GEN3_DISPLAY,
> +	.cursor_needs_physical = 1,
> +	.overlay_needs_physical = 1,
> +};
> +
> +static const struct intel_display_device_info i915gm_display = {
> +	GEN3_DISPLAY,
> +	.cursor_needs_physical = 1,
> +	.overlay_needs_physical = 1,
> +	.supports_tv = 1,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info i945g_display = {
> +	GEN3_DISPLAY,
> +	.has_hotplug = 1,
> +	.cursor_needs_physical = 1,
> +	.overlay_needs_physical = 1,
> +};
> +
> +static const struct intel_display_device_info i945gm_display = {
> +	GEN3_DISPLAY,
> +	.has_hotplug = 1,
> +	.cursor_needs_physical = 1,
> +	.overlay_needs_physical = 1,
> +	.supports_tv = 1,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info g33_display = {
> +	GEN3_DISPLAY,
> +	.has_hotplug = 1,
> +};
> +
> +#define GEN4_DISPLAY \
> +	.has_hotplug = 1, \
> +	.has_gmch = 1, \
> +	I9XX_PIPE_OFFSETS, \
> +	I9XX_CURSOR_OFFSETS, \
> +	I9XX_COLORS, \
> +	\
> +	.__runtime.ip.ver = 4, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> +
> +static const struct intel_display_device_info i965g_display = {
> +	GEN4_DISPLAY,
> +	.has_overlay = 1,
> +};
> +
> +static const struct intel_display_device_info i965gm_display = {
> +	GEN4_DISPLAY,
> +	.has_overlay = 1,
> +	.supports_tv = 1,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info g45_display = {
> +	GEN4_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info gm45_display = {
> +	GEN4_DISPLAY,
> +	.supports_tv = 1,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +#define ILK_DISPLAY \
> +	.has_hotplug = 1, \
> +	I9XX_PIPE_OFFSETS, \
> +	I9XX_CURSOR_OFFSETS, \
> +	ILK_COLORS, \
> +	\
> +	.__runtime.ip.ver = 5, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> +
> +static const struct intel_display_device_info ilk_d_display = {
> +	ILK_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info ilk_m_display = {
> +	ILK_DISPLAY,
> +
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info snb_display = {
> +	.has_hotplug = 1,
> +	I9XX_PIPE_OFFSETS,
> +	I9XX_CURSOR_OFFSETS,
> +	ILK_COLORS,
> +
> +	.__runtime.ip.ver = 6,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info ivb_display = {
> +	.has_hotplug = 1,
> +	IVB_PIPE_OFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +	IVB_COLORS,
> +
> +	.__runtime.ip.ver = 7,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info vlv_display = {
> +	.has_gmch = 1,
> +	.has_hotplug = 1,
> +	.mmio_offset = VLV_DISPLAY_BASE,
> +	I9XX_PIPE_OFFSETS,
> +	I9XX_CURSOR_OFFSETS,
> +	I9XX_COLORS,
> +
> +	.__runtime.ip.ver = 7,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> +};
> +
> +static const struct intel_display_device_info hsw_display = {
> +	.has_ddi = 1,
> +	.has_dp_mst = 1,
> +	.has_fpga_dbg = 1,
> +	.has_hotplug = 1,
> +	HSW_PIPE_OFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +	IVB_COLORS,
> +
> +	.__runtime.ip.ver = 7,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info bdw_display = {
> +	.has_ddi = 1,
> +	.has_dp_mst = 1,
> +	.has_fpga_dbg = 1,
> +	.has_hotplug = 1,
> +	HSW_PIPE_OFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +	IVB_COLORS,
> +
> +	.__runtime.ip.ver = 8,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info chv_display = {
> +	.has_hotplug = 1,
> +	.has_gmch = 1,
> +	.mmio_offset = VLV_DISPLAY_BASE,
> +	CHV_PIPE_OFFSETS,
> +	CHV_CURSOR_OFFSETS,
> +	CHV_COLORS,
> +
> +	.__runtime.ip.ver = 8,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C),
> +};
> +
> +static const struct intel_display_device_info skl_display = {
> +	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> +	.dbuf.slice_mask = BIT(DBUF_S1),
> +	.has_ddi = 1,
> +	.has_dp_mst = 1,
> +	.has_fpga_dbg = 1,
> +	.has_hotplug = 1,
> +	.has_ipc = 1,
> +	.has_psr = 1,
> +	.has_psr_hw_tracking = 1,
> +	HSW_PIPE_OFFSETS,
> +	IVB_CURSOR_OFFSETS,
> +	IVB_COLORS,
> +
> +	.__runtime.ip.ver = 9,
> +	.__runtime.has_dmc = 1,
> +	.__runtime.has_hdcp = 1,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +#define GEN9_LP_DISPLAY \
> +	.dbuf.slice_mask = BIT(DBUF_S1), \
> +	.has_dp_mst = 1, \
> +	.has_ddi = 1, \
> +	.has_fpga_dbg = 1, \
> +	.has_hotplug = 1, \
> +	.has_ipc = 1, \
> +	.has_psr = 1, \
> +	.has_psr_hw_tracking = 1, \
> +	HSW_PIPE_OFFSETS, \
> +	IVB_CURSOR_OFFSETS, \
> +	IVB_COLORS, \
> +	\
> +	.__runtime.has_dmc = 1, \
> +	.__runtime.has_hdcp = 1, \
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> +		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
> +
> +static const struct intel_display_device_info bxt_display = {
> +	GEN9_LP_DISPLAY,
> +	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> +
> +	.__runtime.ip.ver = 9,
> +};
> +
> +static const struct intel_display_device_info glk_display = {
> +	GEN9_LP_DISPLAY,
> +	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> +	GLK_COLORS,
> +
> +	.__runtime.ip.ver = 10,
> +};
> +
> +static const struct intel_display_device_info gen11_display = {
> +	.abox_mask = BIT(0),
> +	.dbuf.size = 2048,
> +	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
> +	.has_ddi = 1,
> +	.has_dp_mst = 1,
> +	.has_fpga_dbg = 1,
> +	.has_hotplug = 1,
> +	.has_ipc = 1,
> +	.has_psr = 1,
> +	.has_psr_hw_tracking = 1,
> +	.pipe_offsets = {
> +		[TRANSCODER_A] = PIPE_A_OFFSET,
> +		[TRANSCODER_B] = PIPE_B_OFFSET,
> +		[TRANSCODER_C] = PIPE_C_OFFSET,
> +		[TRANSCODER_EDP] = PIPE_EDP_OFFSET,
> +		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> +		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> +	},
> +	.trans_offsets = {
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
> +		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
> +		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
> +		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> +		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> +	},
> +	IVB_CURSOR_OFFSETS,
> +	ICL_COLORS,
> +
> +	.__runtime.ip.ver = 11,
> +	.__runtime.has_dmc = 1,
> +	.__runtime.has_dsc = 1, \
> +	.__runtime.has_hdcp = 1,
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
> +		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +#define XE_D_DISPLAY \
> +	.abox_mask = GENMASK(2, 1), \
> +	.dbuf.size = 2048, \
> +	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> +	.has_ddi = 1, \
> +	.has_dp_mst = 1, \
> +	.has_dsb = 1, \
> +	.has_fpga_dbg = 1, \
> +	.has_hotplug = 1, \
> +	.has_ipc = 1, \
> +	.has_psr = 1, \
> +	.has_psr_hw_tracking = 1, \
> +	.pipe_offsets = { \
> +		[TRANSCODER_A] = PIPE_A_OFFSET, \
> +		[TRANSCODER_B] = PIPE_B_OFFSET, \
> +		[TRANSCODER_C] = PIPE_C_OFFSET, \
> +		[TRANSCODER_D] = PIPE_D_OFFSET, \
> +		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> +		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> +	}, \
> +	.trans_offsets = { \
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> +		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> +		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> +		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> +		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> +	}, \
> +	TGL_CURSOR_OFFSETS, \
> +	ICL_COLORS, \
> +	\
> +	.__runtime.ip.ver = 12, \
> +	.__runtime.has_dmc = 1, \
> +	.__runtime.has_dsc = 1, \
> +	.__runtime.has_hdcp = 1, \
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> +		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A)
> +
> +static const struct intel_display_device_info tgl_display = {
> +	XE_D_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info rkl_display = {
> +	XE_D_DISPLAY,
> +	.abox_mask = BIT(0),
> +	.has_hti = 1,
> +	.has_psr_hw_tracking = 0,
> +
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +		BIT(TRANSCODER_C),
> +};
> +
> +static const struct intel_display_device_info adl_s_display = {
> +	XE_D_DISPLAY,
> +	.has_hti = 1,
> +	.has_psr_hw_tracking = 0,
> +};
> +
> +#define XE_LPD_FEATURES \
> +	.abox_mask = GENMASK(1, 0),						\
> +	.color = {								\
> +		.degamma_lut_size = 129, .gamma_lut_size = 1024,		\
> +		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
> +		DRM_COLOR_LUT_EQUAL_CHANNELS,					\
> +	},									\
> +	.dbuf.size = 4096,							\
> +	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
> +		BIT(DBUF_S4),							\
> +	.has_ddi = 1,								\
> +	.has_dp_mst = 1,							\
> +	.has_dsb = 1,								\
> +	.has_fpga_dbg = 1,							\
> +	.has_hotplug = 1,							\
> +	.has_ipc = 1,								\
> +	.has_psr = 1,								\
> +	.pipe_offsets = {							\
> +		[TRANSCODER_A] = PIPE_A_OFFSET,					\
> +		[TRANSCODER_B] = PIPE_B_OFFSET,					\
> +		[TRANSCODER_C] = PIPE_C_OFFSET,					\
> +		[TRANSCODER_D] = PIPE_D_OFFSET,					\
> +		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
> +		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
> +	},									\
> +	.trans_offsets = {						\
> +		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
> +		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
> +		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
> +		[TRANSCODER_D] = TRANSCODER_D_OFFSET,				\
> +		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
> +		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
> +	},									\
> +	TGL_CURSOR_OFFSETS,							\
> +										\
> +	.__runtime.ip.ver = 13,							\
> +	.__runtime.has_dmc = 1,							\
> +	.__runtime.has_dsc = 1,							\
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
> +	.__runtime.has_hdcp = 1,						\
> +	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
> +
> +static const struct intel_display_device_info xe_lpd_display = {
> +	XE_LPD_FEATURES,
> +	.has_cdclk_crawl = 1,
> +	.has_psr_hw_tracking = 0,
> +
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> +			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> +};
> +
> +static const struct intel_display_device_info xe_hpd_display = {
> +	XE_LPD_FEATURES,
> +	.has_cdclk_squash = 1,
> +
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +};
> +
> +static const struct intel_display_device_info xe_lpdp_display = {
> +	XE_LPD_FEATURES,
> +	.has_cdclk_crawl = 1,
> +	.has_cdclk_squash = 1,
> +
> +	.__runtime.ip.ver = 14,
> +	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> +	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +};
> +
> +static const struct pci_device_id intel_display_ids[] = {
> +	INTEL_I830_IDS(&i830_display),
> +	INTEL_I845G_IDS(&i845_display),
> +	INTEL_I85X_IDS(&i85x_display),
> +	INTEL_I865G_IDS(&i865g_display),
> +	INTEL_I915G_IDS(&i915g_display),
> +	INTEL_I915GM_IDS(&i915gm_display),
> +	INTEL_I945G_IDS(&i945g_display),
> +	INTEL_I945GM_IDS(&i945gm_display),
> +	INTEL_I965G_IDS(&i965g_display),
> +	INTEL_G33_IDS(&g33_display),
> +	INTEL_I965GM_IDS(&i965gm_display),
> +	INTEL_GM45_IDS(&gm45_display),
> +	INTEL_G45_IDS(&g45_display),
> +	INTEL_PINEVIEW_G_IDS(&g33_display),
> +	INTEL_PINEVIEW_M_IDS(&g33_display),
> +	INTEL_IRONLAKE_D_IDS(&ilk_d_display),
> +	INTEL_IRONLAKE_M_IDS(&ilk_m_display),
> +	INTEL_SNB_D_IDS(&snb_display),
> +	INTEL_SNB_M_IDS(&snb_display),
> +	INTEL_IVB_Q_IDS(NULL),		/* must be first IVB in list */
> +	INTEL_IVB_M_IDS(&ivb_display),
> +	INTEL_IVB_D_IDS(&ivb_display),
> +	INTEL_HSW_IDS(&hsw_display),
> +	INTEL_VLV_IDS(&vlv_display),
> +	INTEL_BDW_IDS(&bdw_display),
> +	INTEL_CHV_IDS(&chv_display),
> +	INTEL_SKL_IDS(&skl_display),
> +	INTEL_BXT_IDS(&bxt_display),
> +	INTEL_GLK_IDS(&glk_display),
> +	INTEL_KBL_IDS(&skl_display),
> +	INTEL_CFL_IDS(&skl_display),
> +	INTEL_ICL_11_IDS(&gen11_display),
> +	INTEL_EHL_IDS(&gen11_display),
> +	INTEL_JSL_IDS(&gen11_display),
> +	INTEL_TGL_12_IDS(&tgl_display),
> +	INTEL_DG1_IDS(&tgl_display),
> +	INTEL_RKL_IDS(&rkl_display),
> +	INTEL_ADLS_IDS(&adl_s_display),
> +	INTEL_RPLS_IDS(&adl_s_display),
> +	INTEL_ADLP_IDS(&xe_lpd_display),
> +	INTEL_ADLN_IDS(&xe_lpd_display),
> +	INTEL_RPLP_IDS(&xe_lpd_display),
> +	INTEL_DG2_IDS(&xe_hpd_display),
> +
> +	/* FIXME: Replace this with a GMD_ID lookup */
> +	INTEL_MTL_IDS(&xe_lpdp_display),
> +};
> +
> +const struct intel_display_device_info *
> +intel_display_device_probe(u16 pci_devid)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> +		if (intel_display_ids[i].device == pci_devid)
> +			return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
> +	}
> +
> +	return NULL;

Why not "return &no_display" ?

> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 241f39b13f2f..0a60ebfaff80 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -80,4 +80,7 @@ struct intel_display_device_info {
>   	} color;
>   };
>   
> +const struct intel_display_device_info *
> +intel_display_device_probe(u16 pci_devid);
> +
>   #endif
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 8b19df1294de..928975d5fe2f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -43,129 +43,6 @@
>   	.__runtime.graphics.ip.ver = (x), \
>   	.__runtime.media.ip.ver = (x)
>   
> -static const struct intel_display_device_info no_display = { 0 };
> -
> -#define NO_DISPLAY .display = &no_display
> -
> -#define I845_PIPE_OFFSETS \
> -	.pipe_offsets = { \
> -		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> -	}, \
> -	.trans_offsets = { \
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> -	}
> -
> -#define I9XX_PIPE_OFFSETS \
> -	.pipe_offsets = { \
> -		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> -		[TRANSCODER_B] = PIPE_B_OFFSET, \
> -	}, \
> -	.trans_offsets = { \
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> -		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> -	}
> -
> -#define IVB_PIPE_OFFSETS \
> -	.pipe_offsets = { \
> -		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> -		[TRANSCODER_B] = PIPE_B_OFFSET, \
> -		[TRANSCODER_C] = PIPE_C_OFFSET, \
> -	}, \
> -	.trans_offsets = { \
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> -		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> -		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> -	}
> -
> -#define HSW_PIPE_OFFSETS \
> -	.pipe_offsets = { \
> -		[TRANSCODER_A] = PIPE_A_OFFSET,	\
> -		[TRANSCODER_B] = PIPE_B_OFFSET, \
> -		[TRANSCODER_C] = PIPE_C_OFFSET, \
> -		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> -	}, \
> -	.trans_offsets = { \
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> -		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> -		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> -		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> -	}
> -
> -#define CHV_PIPE_OFFSETS \
> -	.pipe_offsets = { \
> -		[TRANSCODER_A] = PIPE_A_OFFSET, \
> -		[TRANSCODER_B] = PIPE_B_OFFSET, \
> -		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> -	}, \
> -	.trans_offsets = { \
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> -		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> -		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> -	}
> -
> -#define I845_CURSOR_OFFSETS \
> -	.cursor_offsets = { \
> -		[PIPE_A] = CURSOR_A_OFFSET, \
> -	}
> -
> -#define I9XX_CURSOR_OFFSETS \
> -	.cursor_offsets = { \
> -		[PIPE_A] = CURSOR_A_OFFSET, \
> -		[PIPE_B] = CURSOR_B_OFFSET, \
> -	}
> -
> -#define CHV_CURSOR_OFFSETS \
> -	.cursor_offsets = { \
> -		[PIPE_A] = CURSOR_A_OFFSET, \
> -		[PIPE_B] = CURSOR_B_OFFSET, \
> -		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
> -	}
> -
> -#define IVB_CURSOR_OFFSETS \
> -	.cursor_offsets = { \
> -		[PIPE_A] = CURSOR_A_OFFSET, \
> -		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
> -		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
> -	}
> -
> -#define TGL_CURSOR_OFFSETS \
> -	.cursor_offsets = { \
> -		[PIPE_A] = CURSOR_A_OFFSET, \
> -		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
> -		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
> -		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
> -	}
> -
> -#define I845_COLORS \
> -	.color = { .gamma_lut_size = 256 }
> -#define I9XX_COLORS \
> -	.color = { .gamma_lut_size = 129, \
> -		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> -	}
> -#define ILK_COLORS \
> -	.color = { .gamma_lut_size = 1024 }
> -#define IVB_COLORS \
> -	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> -#define CHV_COLORS \
> -	.color = { \
> -		.degamma_lut_size = 65, .gamma_lut_size = 257, \
> -		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> -		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> -	}
> -#define GLK_COLORS \
> -	.color = { \
> -		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
> -		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> -				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
> -	}
> -#define ICL_COLORS \
> -	.color = { \
> -		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
> -		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> -				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
> -		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> -	}
> -
>   #define LEGACY_CACHELEVEL \
>   	.cachelevel_to_pat = { \
>   		[I915_CACHE_NONE]   = 0, \
> @@ -206,23 +83,6 @@ static const struct intel_display_device_info no_display = { 0 };
>   #define GEN_DEFAULT_REGIONS \
>   	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
>   
> -#define I830_DISPLAY \
> -	.has_overlay = 1, \
> -	.cursor_needs_physical = 1, \
> -	.overlay_needs_physical = 1, \
> -	.has_gmch = 1, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS, \
> -	\
> -	.__runtime.ip.ver = 2, \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> -
> -static const struct intel_display_device_info i830_display = {
> -	I830_DISPLAY,
> -};
> -
>   #define I830_FEATURES \
>   	GEN(2), \
>   	.is_mobile = 1, \
> @@ -239,22 +99,6 @@ static const struct intel_display_device_info i830_display = {
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
>   
> -#define I845_DISPLAY \
> -	.has_overlay = 1, \
> -	.overlay_needs_physical = 1, \
> -	.has_gmch = 1, \
> -	I845_PIPE_OFFSETS, \
> -	I845_CURSOR_OFFSETS, \
> -	I845_COLORS, \
> -	\
> -	.__runtime.ip.ver = 2, \
> -	.__runtime.pipe_mask = BIT(PIPE_A), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A)
> -
> -static const struct intel_display_device_info i845_display = {
> -	I845_DISPLAY,
> -};
> -
>   #define I845_FEATURES \
>   	GEN(2), \
>   	.has_3d_pipeline = 1, \
> @@ -273,85 +117,21 @@ static const struct intel_display_device_info i845_display = {
>   static const struct intel_device_info i830_info = {
>   	I830_FEATURES,
>   	PLATFORM(INTEL_I830),
> -	.display = &i830_display,
>   };
>   
>   static const struct intel_device_info i845g_info = {
>   	I845_FEATURES,
>   	PLATFORM(INTEL_I845G),
> -	.display = &i845_display,
> -};
> -
> -static const struct intel_display_device_info i85x_display = {
> -	I830_DISPLAY,
> -
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info i85x_info = {
>   	I830_FEATURES,
>   	PLATFORM(INTEL_I85X),
> -	.display = &i85x_display,
> -};
> -
> -static const struct intel_display_device_info i865g_display = {
> -	I845_DISPLAY,
> -
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info i865g_info = {
>   	I845_FEATURES,
>   	PLATFORM(INTEL_I865G),
> -	.display = &i865g_display,
> -};
> -
> -#define GEN3_DISPLAY \
> -	.has_gmch = 1, \
> -	.has_overlay = 1, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS, \
> -	\
> -	.__runtime.ip.ver = 3, \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> -
> -static const struct intel_display_device_info i915g_display = {
> -	GEN3_DISPLAY,
> -	.cursor_needs_physical = 1,
> -	.overlay_needs_physical = 1,
> -};
> -
> -static const struct intel_display_device_info i915gm_display = {
> -	GEN3_DISPLAY,
> -	.cursor_needs_physical = 1,
> -	.overlay_needs_physical = 1,
> -	.supports_tv = 1,
> -
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> -static const struct intel_display_device_info i945g_display = {
> -	GEN3_DISPLAY,
> -	.has_hotplug = 1,
> -	.cursor_needs_physical = 1,
> -	.overlay_needs_physical = 1,
> -};
> -
> -static const struct intel_display_device_info i945gm_display = {
> -	GEN3_DISPLAY,
> -	.has_hotplug = 1,
> -	.cursor_needs_physical = 1,
> -	.overlay_needs_physical = 1,
> -	.supports_tv = 1,
> -
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> -static const struct intel_display_device_info g33_display = {
> -	GEN3_DISPLAY,
> -	.has_hotplug = 1,
>   };
>   
>   #define GEN3_FEATURES \
> @@ -370,7 +150,6 @@ static const struct intel_display_device_info g33_display = {
>   static const struct intel_device_info i915g_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_I915G),
> -	.display = &i915g_display,
>   	.has_coherent_ggtt = false,
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
> @@ -379,7 +158,6 @@ static const struct intel_device_info i915g_info = {
>   static const struct intel_device_info i915gm_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_I915GM),
> -	.display = &i915gm_display,
>   	.is_mobile = 1,
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
> @@ -388,7 +166,6 @@ static const struct intel_device_info i915gm_info = {
>   static const struct intel_device_info i945g_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_I945G),
> -	.display = &i945g_display,
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
>   };
> @@ -396,7 +173,6 @@ static const struct intel_device_info i945g_info = {
>   static const struct intel_device_info i945gm_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_I945GM),
> -	.display = &i945gm_display,
>   	.is_mobile = 1,
>   	.hws_needs_physical = 1,
>   	.unfenced_needs_alignment = 1,
> @@ -405,14 +181,12 @@ static const struct intel_device_info i945gm_info = {
>   static const struct intel_device_info g33_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_G33),
> -	.display = &g33_display,
>   	.dma_mask_size = 36,
>   };
>   
>   static const struct intel_device_info pnv_g_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_PINEVIEW),
> -	.display = &g33_display,
>   	.dma_mask_size = 36,
>   };
>   
> @@ -420,45 +194,9 @@ static const struct intel_device_info pnv_m_info = {
>   	GEN3_FEATURES,
>   	PLATFORM(INTEL_PINEVIEW),
>   	.is_mobile = 1,
> -	.display = &g33_display,
>   	.dma_mask_size = 36,
>   };
>   
> -#define GEN4_DISPLAY \
> -	.has_hotplug = 1, \
> -	.has_gmch = 1, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	I9XX_COLORS, \
> -	\
> -	.__runtime.ip.ver = 4, \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> -
> -static const struct intel_display_device_info i965g_display = {
> -	GEN4_DISPLAY,
> -	.has_overlay = 1,
> -};
> -
> -static const struct intel_display_device_info i965gm_display = {
> -	GEN4_DISPLAY,
> -	.has_overlay = 1,
> -	.supports_tv = 1,
> -
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> -static const struct intel_display_device_info g45_display = {
> -	GEN4_DISPLAY,
> -};
> -
> -static const struct intel_display_device_info gm45_display = {
> -	GEN4_DISPLAY,
> -	.supports_tv = 1,
> -
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
>   #define GEN4_FEATURES \
>   	GEN(4), \
>   	.gpu_reset_clobbers_display = true, \
> @@ -475,7 +213,6 @@ static const struct intel_display_device_info gm45_display = {
>   static const struct intel_device_info i965g_info = {
>   	GEN4_FEATURES,
>   	PLATFORM(INTEL_I965G),
> -	.display = &i965g_display,
>   	.hws_needs_physical = 1,
>   	.has_snoop = false,
>   };
> @@ -483,7 +220,6 @@ static const struct intel_device_info i965g_info = {
>   static const struct intel_device_info i965gm_info = {
>   	GEN4_FEATURES,
>   	PLATFORM(INTEL_I965GM),
> -	.display = &i965gm_display,
>   	.is_mobile = 1,
>   	.hws_needs_physical = 1,
>   	.has_snoop = false,
> @@ -493,7 +229,6 @@ static const struct intel_device_info g45_info = {
>   	GEN4_FEATURES,
>   	PLATFORM(INTEL_G45),
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> -	.display = &g45_display,
>   	.gpu_reset_clobbers_display = false,
>   };
>   
> @@ -502,7 +237,6 @@ static const struct intel_device_info gm45_info = {
>   	PLATFORM(INTEL_GM45),
>   	.is_mobile = 1,
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> -	.display = &gm45_display,
>   	.gpu_reset_clobbers_display = false,
>   };
>   
> @@ -520,36 +254,14 @@ static const struct intel_device_info gm45_info = {
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
>   
> -#define ILK_DISPLAY \
> -	.has_hotplug = 1, \
> -	I9XX_PIPE_OFFSETS, \
> -	I9XX_CURSOR_OFFSETS, \
> -	ILK_COLORS, \
> -	\
> -	.__runtime.ip.ver = 5, \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> -
> -static const struct intel_display_device_info ilk_d_display = {
> -	ILK_DISPLAY,
> -};
> -
>   static const struct intel_device_info ilk_d_info = {
>   	GEN5_FEATURES,
>   	PLATFORM(INTEL_IRONLAKE),
> -	.display = &ilk_d_display,
> -};
> -
> -static const struct intel_display_device_info ilk_m_display = {
> -	ILK_DISPLAY,
> -
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
>   };
>   
>   static const struct intel_device_info ilk_m_info = {
>   	GEN5_FEATURES,
>   	PLATFORM(INTEL_IRONLAKE),
> -	.display = &ilk_m_display,
>   	.is_mobile = 1,
>   	.has_rps = true,
>   };
> @@ -572,31 +284,17 @@ static const struct intel_device_info ilk_m_info = {
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
>   
> -static const struct intel_display_device_info snb_display = {
> -	.has_hotplug = 1,
> -	I9XX_PIPE_OFFSETS,
> -	I9XX_CURSOR_OFFSETS,
> -	ILK_COLORS,
> -
> -	.__runtime.ip.ver = 6,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
>   #define SNB_D_PLATFORM \
>   	GEN6_FEATURES, \
>   	PLATFORM(INTEL_SANDYBRIDGE)
>   
>   static const struct intel_device_info snb_d_gt1_info = {
>   	SNB_D_PLATFORM,
> -	.display = &snb_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info snb_d_gt2_info = {
>   	SNB_D_PLATFORM,
> -	.display = &snb_display,
>   	.gt = 2,
>   };
>   
> @@ -608,13 +306,11 @@ static const struct intel_device_info snb_d_gt2_info = {
>   
>   static const struct intel_device_info snb_m_gt1_info = {
>   	SNB_M_PLATFORM,
> -	.display = &snb_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info snb_m_gt2_info = {
>   	SNB_M_PLATFORM,
> -	.display = &snb_display,
>   	.gt = 2,
>   };
>   
> @@ -641,28 +337,13 @@ static const struct intel_device_info snb_m_gt2_info = {
>   	PLATFORM(INTEL_IVYBRIDGE), \
>   	.has_l3_dpf = 1
>   
> -static const struct intel_display_device_info ivb_display = {
> -	.has_hotplug = 1,
> -	IVB_PIPE_OFFSETS,
> -	IVB_CURSOR_OFFSETS,
> -	IVB_COLORS,
> -
> -	.__runtime.ip.ver = 7,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -		BIT(TRANSCODER_C),
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
>   static const struct intel_device_info ivb_d_gt1_info = {
>   	IVB_D_PLATFORM,
> -	.display = &ivb_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info ivb_d_gt2_info = {
>   	IVB_D_PLATFORM,
> -	.display = &ivb_display,
>   	.gt = 2,
>   };
>   
> @@ -674,42 +355,25 @@ static const struct intel_device_info ivb_d_gt2_info = {
>   
>   static const struct intel_device_info ivb_m_gt1_info = {
>   	IVB_M_PLATFORM,
> -	.display = &ivb_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info ivb_m_gt2_info = {
>   	IVB_M_PLATFORM,
> -	.display = &ivb_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info ivb_q_info = {
>   	GEN7_FEATURES,
>   	PLATFORM(INTEL_IVYBRIDGE),
> -	NO_DISPLAY,
>   	.gt = 2,
>   	.has_l3_dpf = 1,
>   };
>   
> -static const struct intel_display_device_info vlv_display = {
> -	.has_gmch = 1,
> -	.has_hotplug = 1,
> -	.mmio_offset = VLV_DISPLAY_BASE,
> -	I9XX_PIPE_OFFSETS,
> -	I9XX_CURSOR_OFFSETS,
> -	I9XX_COLORS,
> -
> -	.__runtime.ip.ver = 7,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> -};
> -
>   static const struct intel_device_info vlv_info = {
>   	PLATFORM(INTEL_VALLEYVIEW),
>   	GEN(7),
>   	.is_lp = 1,
> -	.display = &vlv_display,
>   	.has_runtime_pm = 1,
>   	.has_rc6 = 1,
>   	.has_reset_engine = true,
> @@ -737,37 +401,18 @@ static const struct intel_device_info vlv_info = {
>   	PLATFORM(INTEL_HASWELL), \
>   	.has_l3_dpf = 1
>   
> -static const struct intel_display_device_info hsw_display = {
> -	.has_ddi = 1,
> -	.has_dp_mst = 1,
> -	.has_fpga_dbg = 1,
> -	.has_hotplug = 1,
> -	HSW_PIPE_OFFSETS,
> -	IVB_CURSOR_OFFSETS,
> -	IVB_COLORS,
> -
> -	.__runtime.ip.ver = 7,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
>   static const struct intel_device_info hsw_gt1_info = {
>   	HSW_PLATFORM,
> -	.display = &hsw_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info hsw_gt2_info = {
>   	HSW_PLATFORM,
> -	.display = &hsw_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info hsw_gt3_info = {
>   	HSW_PLATFORM,
> -	.display = &hsw_display,
>   	.gt = 3,
>   };
>   
> @@ -780,41 +425,22 @@ static const struct intel_device_info hsw_gt3_info = {
>   	.__runtime.ppgtt_size = 48, \
>   	.has_64bit_reloc = 1
>   
> -static const struct intel_display_device_info bdw_display = {
> -	.has_ddi = 1,
> -	.has_dp_mst = 1,
> -	.has_fpga_dbg = 1,
> -	.has_hotplug = 1,
> -	HSW_PIPE_OFFSETS,
> -	IVB_CURSOR_OFFSETS,
> -	IVB_COLORS,
> -
> -	.__runtime.ip.ver = 8,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
>   #define BDW_PLATFORM \
>   	GEN8_FEATURES, \
>   	PLATFORM(INTEL_BROADWELL)
>   
>   static const struct intel_device_info bdw_gt1_info = {
>   	BDW_PLATFORM,
> -	.display = &bdw_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info bdw_gt2_info = {
>   	BDW_PLATFORM,
> -	.display = &bdw_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info bdw_rsvd_info = {
>   	BDW_PLATFORM,
> -	.display = &bdw_display,
>   	.gt = 3,
>   	/* According to the device ID those devices are GT3, they were
>   	 * previously treated as not GT3, keep it like that.
> @@ -823,30 +449,14 @@ static const struct intel_device_info bdw_rsvd_info = {
>   
>   static const struct intel_device_info bdw_gt3_info = {
>   	BDW_PLATFORM,
> -	.display = &bdw_display,
>   	.gt = 3,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
>   };
>   
> -static const struct intel_display_device_info chv_display = {
> -	.has_hotplug = 1,
> -	.has_gmch = 1,
> -	.mmio_offset = VLV_DISPLAY_BASE,
> -	CHV_PIPE_OFFSETS,
> -	CHV_CURSOR_OFFSETS,
> -	CHV_COLORS,
> -
> -	.__runtime.ip.ver = 8,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -		BIT(TRANSCODER_C),
> -};
> -
>   static const struct intel_device_info chv_info = {
>   	PLATFORM(INTEL_CHERRYVIEW),
>   	GEN(8),
> -	.display = &chv_display,
>   	.is_lp = 1,
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
>   	.has_64bit_reloc = 1,
> @@ -876,42 +486,17 @@ static const struct intel_device_info chv_info = {
>   	GEN9_DEFAULT_PAGE_SIZES, \
>   	.has_gt_uc = 1
>   
> -static const struct intel_display_device_info skl_display = {
> -	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> -	.dbuf.slice_mask = BIT(DBUF_S1),
> -	.has_ddi = 1,
> -	.has_dp_mst = 1,
> -	.has_fpga_dbg = 1,
> -	.has_hotplug = 1,
> -	.has_ipc = 1,
> -	.has_psr = 1,
> -	.has_psr_hw_tracking = 1,
> -	HSW_PIPE_OFFSETS,
> -	IVB_CURSOR_OFFSETS,
> -	IVB_COLORS,
> -
> -	.__runtime.ip.ver = 9,
> -	.__runtime.has_dmc = 1,
> -	.__runtime.has_hdcp = 1,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
>   #define SKL_PLATFORM \
>   	GEN9_FEATURES, \
>   	PLATFORM(INTEL_SKYLAKE)
>   
>   static const struct intel_device_info skl_gt1_info = {
>   	SKL_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info skl_gt2_info = {
>   	SKL_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 2,
>   };
>   
> @@ -923,13 +508,11 @@ static const struct intel_device_info skl_gt2_info = {
>   
>   static const struct intel_device_info skl_gt3_info = {
>   	SKL_GT3_PLUS_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 3,
>   };
>   
>   static const struct intel_device_info skl_gt4_info = {
>   	SKL_GT3_PLUS_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 4,
>   };
>   
> @@ -955,52 +538,14 @@ static const struct intel_device_info skl_gt4_info = {
>   	GEN_DEFAULT_REGIONS, \
>   	LEGACY_CACHELEVEL
>   
> -#define GEN9_LP_DISPLAY \
> -	.dbuf.slice_mask = BIT(DBUF_S1), \
> -	.has_dp_mst = 1, \
> -	.has_ddi = 1, \
> -	.has_fpga_dbg = 1, \
> -	.has_hotplug = 1, \
> -	.has_ipc = 1, \
> -	.has_psr = 1, \
> -	.has_psr_hw_tracking = 1, \
> -	HSW_PIPE_OFFSETS, \
> -	IVB_CURSOR_OFFSETS, \
> -	IVB_COLORS, \
> -	\
> -	.__runtime.has_dmc = 1, \
> -	.__runtime.has_hdcp = 1, \
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> -		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
> -
> -static const struct intel_display_device_info bxt_display = {
> -	GEN9_LP_DISPLAY,
> -	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> -
> -	.__runtime.ip.ver = 9,
> -};
> -
>   static const struct intel_device_info bxt_info = {
>   	GEN9_LP_FEATURES,
>   	PLATFORM(INTEL_BROXTON),
> -	.display = &bxt_display,
> -};
> -
> -static const struct intel_display_device_info glk_display = {
> -	GEN9_LP_DISPLAY,
> -	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> -	GLK_COLORS,
> -
> -	.__runtime.ip.ver = 10,
>   };
>   
>   static const struct intel_device_info glk_info = {
>   	GEN9_LP_FEATURES,
>   	PLATFORM(INTEL_GEMINILAKE),
> -	.display = &glk_display,
>   };
>   
>   #define KBL_PLATFORM \
> @@ -1009,19 +554,16 @@ static const struct intel_device_info glk_info = {
>   
>   static const struct intel_device_info kbl_gt1_info = {
>   	KBL_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info kbl_gt2_info = {
>   	KBL_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info kbl_gt3_info = {
>   	KBL_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 3,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> @@ -1033,19 +575,16 @@ static const struct intel_device_info kbl_gt3_info = {
>   
>   static const struct intel_device_info cfl_gt1_info = {
>   	CFL_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info cfl_gt2_info = {
>   	CFL_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 2,
>   };
>   
>   static const struct intel_device_info cfl_gt3_info = {
>   	CFL_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 3,
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> @@ -1057,13 +596,11 @@ static const struct intel_device_info cfl_gt3_info = {
>   
>   static const struct intel_device_info cml_gt1_info = {
>   	CML_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 1,
>   };
>   
>   static const struct intel_device_info cml_gt2_info = {
>   	CML_PLATFORM,
> -	.display = &skl_display,
>   	.gt = 2,
>   };
>   
> @@ -1079,53 +616,11 @@ static const struct intel_device_info cml_gt2_info = {
>   	.has_coherent_ggtt = false, \
>   	.has_logical_ring_elsq = 1
>   
> -static const struct intel_display_device_info gen11_display = {
> -	.abox_mask = BIT(0),
> -	.dbuf.size = 2048,
> -	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
> -	.has_ddi = 1,
> -	.has_dp_mst = 1,
> -	.has_fpga_dbg = 1,
> -	.has_hotplug = 1,
> -	.has_ipc = 1,
> -	.has_psr = 1,
> -	.has_psr_hw_tracking = 1,
> -	.pipe_offsets = {
> -		[TRANSCODER_A] = PIPE_A_OFFSET,
> -		[TRANSCODER_B] = PIPE_B_OFFSET,
> -		[TRANSCODER_C] = PIPE_C_OFFSET,
> -		[TRANSCODER_EDP] = PIPE_EDP_OFFSET,
> -		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> -		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> -	},
> -	.trans_offsets = {
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
> -		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
> -		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
> -		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
> -		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> -		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> -	},
> -	IVB_CURSOR_OFFSETS,
> -	ICL_COLORS,
> -
> -	.__runtime.ip.ver = 11,
> -	.__runtime.has_dmc = 1,
> -	.__runtime.has_dsc = 1, \
> -	.__runtime.has_hdcp = 1,
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
> -		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
>   static const struct intel_device_info icl_info = {
>   	GEN11_FEATURES,
>   	PLATFORM(INTEL_ICELAKE),
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> -	.display = &gen11_display,
>   };
>   
>   static const struct intel_device_info ehl_info = {
> @@ -1133,7 +628,6 @@ static const struct intel_device_info ehl_info = {
>   	PLATFORM(INTEL_ELKHARTLAKE),
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>   	.__runtime.ppgtt_size = 36,
> -	.display = &gen11_display,
>   };
>   
>   static const struct intel_device_info jsl_info = {
> @@ -1141,7 +635,6 @@ static const struct intel_device_info jsl_info = {
>   	PLATFORM(INTEL_JASPERLAKE),
>   	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>   	.__runtime.ppgtt_size = 36,
> -	.display = &gen11_display,
>   };
>   
>   #define GEN12_FEATURES \
> @@ -1152,68 +645,11 @@ static const struct intel_device_info jsl_info = {
>   	.has_pxp = 1, \
>   	.max_pat_index = 3
>   
> -#define XE_D_DISPLAY \
> -	.abox_mask = GENMASK(2, 1), \
> -	.dbuf.size = 2048, \
> -	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> -	.has_ddi = 1, \
> -	.has_dp_mst = 1, \
> -	.has_dsb = 1, \
> -	.has_fpga_dbg = 1, \
> -	.has_hotplug = 1, \
> -	.has_ipc = 1, \
> -	.has_psr = 1, \
> -	.has_psr_hw_tracking = 1, \
> -	.pipe_offsets = { \
> -		[TRANSCODER_A] = PIPE_A_OFFSET, \
> -		[TRANSCODER_B] = PIPE_B_OFFSET, \
> -		[TRANSCODER_C] = PIPE_C_OFFSET, \
> -		[TRANSCODER_D] = PIPE_D_OFFSET, \
> -		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> -		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> -	}, \
> -	.trans_offsets = { \
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> -		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> -		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> -		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> -		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> -		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> -	}, \
> -	TGL_CURSOR_OFFSETS, \
> -	ICL_COLORS, \
> -	\
> -	.__runtime.ip.ver = 12, \
> -	.__runtime.has_dmc = 1, \
> -	.__runtime.has_dsc = 1, \
> -	.__runtime.has_hdcp = 1, \
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> -		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> -		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A)
> -
> -static const struct intel_display_device_info tgl_display = {
> -	XE_D_DISPLAY,
> -};
> -
>   static const struct intel_device_info tgl_info = {
>   	GEN12_FEATURES,
>   	PLATFORM(INTEL_TIGERLAKE),
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> -	.display = &tgl_display,
> -};
> -
> -static const struct intel_display_device_info rkl_display = {
> -	XE_D_DISPLAY,
> -	.abox_mask = BIT(0),
> -	.has_hti = 1,
> -	.has_psr_hw_tracking = 0,
> -
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -		BIT(TRANSCODER_C),
>   };
>   
>   static const struct intel_device_info rkl_info = {
> @@ -1221,7 +657,6 @@ static const struct intel_device_info rkl_info = {
>   	PLATFORM(INTEL_ROCKETLAKE),
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
> -	.display = &rkl_display,
>   };
>   
>   #define DGFX_FEATURES \
> @@ -1243,13 +678,6 @@ static const struct intel_device_info dg1_info = {
>   		BIT(VCS0) | BIT(VCS2),
>   	/* Wa_16011227922 */
>   	.__runtime.ppgtt_size = 47,
> -	.display = &tgl_display,
> -};
> -
> -static const struct intel_display_device_info adl_s_display = {
> -	XE_D_DISPLAY,
> -	.has_hti = 1,
> -	.has_psr_hw_tracking = 0,
>   };
>   
>   static const struct intel_device_info adl_s_info = {
> @@ -1258,59 +686,6 @@ static const struct intel_device_info adl_s_info = {
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>   	.dma_mask_size = 39,
> -	.display = &adl_s_display,
> -};
> -
> -#define XE_LPD_FEATURES \
> -	.abox_mask = GENMASK(1, 0),						\
> -	.color = {								\
> -		.degamma_lut_size = 129, .gamma_lut_size = 1024,		\
> -		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
> -		DRM_COLOR_LUT_EQUAL_CHANNELS,					\
> -	},									\
> -	.dbuf.size = 4096,							\
> -	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
> -		BIT(DBUF_S4),							\
> -	.has_ddi = 1,								\
> -	.has_dp_mst = 1,							\
> -	.has_dsb = 1,								\
> -	.has_fpga_dbg = 1,							\
> -	.has_hotplug = 1,							\
> -	.has_ipc = 1,								\
> -	.has_psr = 1,								\
> -	.pipe_offsets = {							\
> -		[TRANSCODER_A] = PIPE_A_OFFSET,					\
> -		[TRANSCODER_B] = PIPE_B_OFFSET,					\
> -		[TRANSCODER_C] = PIPE_C_OFFSET,					\
> -		[TRANSCODER_D] = PIPE_D_OFFSET,					\
> -		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
> -		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
> -	},									\
> -	.trans_offsets = {						\
> -		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
> -		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
> -		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
> -		[TRANSCODER_D] = TRANSCODER_D_OFFSET,				\
> -		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
> -		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
> -	},									\
> -	TGL_CURSOR_OFFSETS,							\
> -										\
> -	.__runtime.ip.ver = 13,							\
> -	.__runtime.has_dmc = 1,							\
> -	.__runtime.has_dsc = 1,							\
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\
> -	.__runtime.has_hdcp = 1,						\
> -	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
> -
> -static const struct intel_display_device_info xe_lpd_display = {
> -	XE_LPD_FEATURES,
> -	.has_cdclk_crawl = 1,
> -	.has_psr_hw_tracking = 0,
> -
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> -			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
>   };
>   
>   static const struct intel_device_info adl_p_info = {
> @@ -1319,7 +694,6 @@ static const struct intel_device_info adl_p_info = {
>   	.__runtime.platform_engine_mask =
>   		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>   	.__runtime.ppgtt_size = 48,
> -	.display = &xe_lpd_display,
>   	.dma_mask_size = 39,
>   };
>   
> @@ -1367,7 +741,6 @@ static const struct intel_device_info xehpsdv_info = {
>   	XE_HPM_FEATURES,
>   	DGFX_FEATURES,
>   	PLATFORM(INTEL_XEHPSDV),
> -	NO_DISPLAY,
>   	.has_64k_pages = 1,
>   	.has_media_ratio_mode = 1,
>   	.__runtime.platform_engine_mask =
> @@ -1396,22 +769,12 @@ static const struct intel_device_info xehpsdv_info = {
>   		BIT(VCS0) | BIT(VCS2) | \
>   		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
>   
> -static const struct intel_display_device_info xe_hpd_display = {
> -	XE_LPD_FEATURES,
> -	.has_cdclk_squash = 1,
> -
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> -};
> -
>   static const struct intel_device_info dg2_info = {
>   	DG2_FEATURES,
> -	.display = &xe_hpd_display,
>   };
>   
>   static const struct intel_device_info ats_m_info = {
>   	DG2_FEATURES,
> -	NO_DISPLAY,
>   	.require_force_probe = 1,
>   	.tuning_thread_rr_after_dep = 1,
>   };
> @@ -1433,7 +796,6 @@ static const struct intel_device_info pvc_info = {
>   	.__runtime.graphics.ip.rel = 60,
>   	.__runtime.media.ip.rel = 60,
>   	PLATFORM(INTEL_PONTEVECCHIO),
> -	NO_DISPLAY,
>   	.has_flat_ccs = 0,
>   	.max_pat_index = 7,
>   	.__runtime.platform_engine_mask =
> @@ -1454,17 +816,6 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
>   	{}
>   };
>   
> -static const struct intel_display_device_info xe_lpdp_display = {
> -	XE_LPD_FEATURES,
> -	.has_cdclk_crawl = 1,
> -	.has_cdclk_squash = 1,
> -
> -	.__runtime.ip.ver = 14,
> -	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> -	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> -			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> -};
> -
>   static const struct intel_device_info mtl_info = {
>   	XE_HP_FEATURES,
>   	/*
> @@ -1475,7 +826,6 @@ static const struct intel_device_info mtl_info = {
>   	.__runtime.graphics.ip.rel = 70,
>   	.__runtime.media.ip.ver = 13,
>   	PLATFORM(INTEL_METEORLAKE),
> -	.display = &xe_lpdp_display,
>   	.extra_gt_list = xelpmp_extra_gt,
>   	.has_flat_ccs = 0,
>   	.has_gmd_id = 1,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a9ab8de8421..f1ba1eae26ca 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1966,15 +1966,6 @@
>   #define _TRANS_VSYNC_DSI1	0x6b814
>   #define _TRANS_VSYNCSHIFT_DSI1	0x6b828
>   
> -#define TRANSCODER_A_OFFSET 0x60000
> -#define TRANSCODER_B_OFFSET 0x61000
> -#define TRANSCODER_C_OFFSET 0x62000
> -#define CHV_TRANSCODER_C_OFFSET 0x63000
> -#define TRANSCODER_D_OFFSET 0x63000
> -#define TRANSCODER_EDP_OFFSET 0x6f000
> -#define TRANSCODER_DSI0_OFFSET	0x6b000
> -#define TRANSCODER_DSI1_OFFSET	0x6b800
> -
>   #define TRANS_HTOTAL(trans)	_MMIO_TRANS2((trans), _TRANS_HTOTAL_A)
>   #define TRANS_HBLANK(trans)	_MMIO_TRANS2((trans), _TRANS_HBLANK_A)
>   #define TRANS_HSYNC(trans)	_MMIO_TRANS2((trans), _TRANS_HSYNC_A)
> @@ -2622,23 +2613,6 @@
>   #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
>   #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
>   
> -#define PIPE_A_OFFSET		0x70000
> -#define PIPE_B_OFFSET		0x71000
> -#define PIPE_C_OFFSET		0x72000
> -#define PIPE_D_OFFSET		0x73000
> -#define CHV_PIPE_C_OFFSET	0x74000
> -/*
> - * There's actually no pipe EDP. Some pipe registers have
> - * simply shifted from the pipe to the transcoder, while
> - * keeping their original offset. Thus we need PIPE_EDP_OFFSET
> - * to access such registers in transcoder EDP.
> - */
> -#define PIPE_EDP_OFFSET	0x7f000
> -
> -/* ICL DSI 0 and 1 */
> -#define PIPE_DSI0_OFFSET	0x7b000
> -#define PIPE_DSI1_OFFSET	0x7b800
> -
>   #define TRANSCONF(trans)	_MMIO_PIPE2((trans), _TRANSACONF)
>   #define PIPEDSL(pipe)		_MMIO_PIPE2(pipe, _PIPEADSL)
>   #define PIPEFRAME(pipe)		_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
> @@ -3099,13 +3073,6 @@
>   #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A)
>   #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
>   
> -#define CURSOR_A_OFFSET 0x70080
> -#define CURSOR_B_OFFSET 0x700c0
> -#define CHV_CURSOR_C_OFFSET 0x700e0
> -#define IVB_CURSOR_B_OFFSET 0x71080
> -#define IVB_CURSOR_C_OFFSET 0x72080
> -#define TGL_CURSOR_D_OFFSET 0x73080
> -
>   /* Display A control */
>   #define _DSPAADDR_VLV				0x7017C /* vlv/chv */
>   #define _DSPACNTR				0x70180
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index e10907ddbade..9d0b54ba50c1 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -583,9 +583,16 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
>   	/* Initialize initial runtime info from static const data and pdev. */
>   	runtime = RUNTIME_INFO(i915);
>   	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
> -	display_runtime = DISPLAY_RUNTIME_INFO(i915);
> -	memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
> -	       sizeof(*display_runtime));
> +
> +	/* Probe display support */
> +	info->display = intel_display_device_probe(device_id);
> +	if (info->display) {
> +		display_runtime = DISPLAY_RUNTIME_INFO(i915);
> +		memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
> +		       sizeof(*display_runtime));
> +	} else {
> +		info->display = &no_display;
> +	}

Assuming intel_display_device_probe always returns pointer (sometimes to 
no_display). You can try to simplify it:
	info->display = intel_display_device_probe(device_id);
	*DISPLAY_RUNTIME_INFO(i915) = DISPLAY_INFO(i915)->__runtime;

Regards
Andrzej

>   
>   	runtime->device_id = device_id;
>   }


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
                   ` (3 preceding siblings ...)
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 4/5] drm/i915/display: Make display responsible for probing its own IP Matt Roper
@ 2023-05-18  3:18 ` Matt Roper
  2023-05-18  7:53   ` kernel test robot
                     ` (2 more replies)
  2023-05-18  4:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Move display identification/probing under display/ Patchwork
                   ` (3 subsequent siblings)
  8 siblings, 3 replies; 21+ messages in thread
From: Matt Roper @ 2023-05-18  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Matt Roper, intel-xe

For platforms with GMD_ID support (i.e., everything MTL and beyond),
identification of the display IP present should be based on the contents
of the GMD_ID register rather than a PCI devid match.

Note that since GMD_ID readout requires access to the PCI BAR, a slight
change to the driver init sequence is needed --- pci_enable_device() is
now called before i915_driver_create().

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/intel_display_device.c   | 64 +++++++++++++++++--
 .../drm/i915/display/intel_display_device.h   |  5 +-
 drivers/gpu/drm/i915/i915_driver.c            | 10 +--
 drivers/gpu/drm/i915/intel_device_info.c      | 13 ++--
 4 files changed, 78 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 78fa522aaf0b..813a2a494082 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -6,7 +6,10 @@
 #include <drm/i915_pciids.h>
 #include <drm/drm_color_mgmt.h>
 #include <linux/mod_devicetable.h>
+#include <linux/pci.h>
 
+#include "i915_drv.h"
+#include "i915_reg.h"
 #include "intel_display_device.h"
 #include "intel_display_power.h"
 #include "intel_display_reg_defs.h"
@@ -674,18 +677,69 @@ static const struct pci_device_id intel_display_ids[] = {
 	INTEL_RPLP_IDS(&xe_lpd_display),
 	INTEL_DG2_IDS(&xe_hpd_display),
 
-	/* FIXME: Replace this with a GMD_ID lookup */
-	INTEL_MTL_IDS(&xe_lpdp_display),
+	/*
+	 * Do not add any GMD_ID-based platforms to this list.  They will
+	 * be probed automatically based on the IP version reported by
+	 * the hardware.
+	 */
 };
 
+struct {
+	u16 ver;
+	u16 rel;
+	const struct intel_display_device_info *display;
+} gmdid_display_map[] = {
+	{ 14,  0, &xe_lpdp_display },
+};
+
+static const struct intel_display_device_info *
+probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	void __iomem *addr;
+	u32 val;
+	int i;
+
+	addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
+	if (!addr) {
+		drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
+		return NULL;
+	}
+
+	val = ioread32(addr);
+	pci_iounmap(pdev, addr);
+
+	if (val == 0)
+		/* Platform doesn't have display */
+		return NULL;
+
+	*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
+	*rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
+	*step = REG_FIELD_GET(GMD_ID_STEP, val);
+
+	for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
+		if (*ver == gmdid_display_map[i].ver &&
+		    *rel == gmdid_display_map[i].rel)
+			return gmdid_display_map[i].display;
+
+	drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
+		*ver, *rel);
+	return NULL;
+}
+
 const struct intel_display_device_info *
-intel_display_device_probe(u16 pci_devid)
+intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
+			   u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
 {
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 	int i;
 
+	if (has_gmdid)
+		return probe_gmdid_display(i915, gmdid_ver, gmdid_rel, gmdid_step);
+
 	for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
-		if (intel_display_ids[i].device == pci_devid)
-			return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
+		if (intel_display_ids[i].device == pdev->device)
+			return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;
 	}
 
 	return NULL;
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 0a60ebfaff80..9a344ee36d8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -80,7 +80,10 @@ struct intel_display_device_info {
 	} color;
 };
 
+struct drm_i915_private;
+
 const struct intel_display_device_info *
-intel_display_device_probe(u16 pci_devid);
+intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
+			   u16 *ver, u16 *rel, u16 *step);
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 522733a89946..d02c602e9a0b 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -754,14 +754,16 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	struct drm_i915_private *i915;
 	int ret;
 
-	i915 = i915_driver_create(pdev, ent);
-	if (IS_ERR(i915))
-		return PTR_ERR(i915);
-
 	ret = pci_enable_device(pdev);
 	if (ret)
 		goto out_fini;
 
+	i915 = i915_driver_create(pdev, ent);
+	if (IS_ERR(i915)) {
+		ret = PTR_ERR(i915);
+		goto out_pci_disable;
+	}
+
 	ret = i915_driver_early_probe(i915);
 	if (ret < 0)
 		goto out_pci_disable;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9d0b54ba50c1..5f38ff8caac0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -345,7 +345,6 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
 static void intel_ipver_early_init(struct drm_i915_private *i915)
 {
 	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
-	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
 
 	if (!HAS_GMD_ID(i915)) {
 		drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
@@ -366,8 +365,6 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
 		RUNTIME_INFO(i915)->graphics.ip.ver = 12;
 		RUNTIME_INFO(i915)->graphics.ip.rel = 70;
 	}
-	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
-		    (struct intel_ip_version *)&display_runtime->ip);
 	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
 		    &runtime->media.ip);
 }
@@ -575,6 +572,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
 	struct intel_device_info *info;
 	struct intel_runtime_info *runtime;
 	struct intel_display_runtime_info *display_runtime;
+	u16 ver, rel, step;
 
 	/* Setup the write-once "constant" device info */
 	info = mkwrite_device_info(i915);
@@ -585,11 +583,18 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
 	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
 
 	/* Probe display support */
-	info->display = intel_display_device_probe(device_id);
+	info->display = intel_display_device_probe(i915, info->has_gmd_id,
+						   &ver, &rel, &step);
 	if (info->display) {
 		display_runtime = DISPLAY_RUNTIME_INFO(i915);
 		memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
 		       sizeof(*display_runtime));
+
+		if (info->has_gmd_id) {
+			display_runtime->ip.ver = ver;
+			display_runtime->ip.rel = rel;
+			display_runtime->ip.step = step;
+		}
 	} else {
 		info->display = &no_display;
 	}
-- 
2.40.0


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
@ 2023-05-18  7:53   ` kernel test robot
  2023-05-18  9:28   ` kernel test robot
  2023-05-18 10:44   ` Andrzej Hajda
  2 siblings, 0 replies; 21+ messages in thread
From: kernel test robot @ 2023-05-18  7:53 UTC (permalink / raw)
  To: Matt Roper, intel-gfx; +Cc: llvm, Matt Roper, intel-xe, oe-kbuild-all

[-- Attachment #1: Type: text/plain, Size: 15588 bytes --]

Hi Matt,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Matt-Roper/drm-i915-display-Move-display-device-info-to-header-under-display/20230518-112007
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230518031804.3133486-6-matthew.d.roper%40intel.com
patch subject: [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code
config: i386-randconfig-a004
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/fc14367208dfb37157d27e941b61827dc058c60b
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Matt-Roper/drm-i915-display-Move-display-device-info-to-header-under-display/20230518-112007
        git checkout fc14367208dfb37157d27e941b61827dc058c60b
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202305181522.Rsq94cMp-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/i915_driver.c:758:6: warning: variable 'i915' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
           if (ret)
               ^~~
   drivers/gpu/drm/i915/i915_driver.c:849:19: note: uninitialized use occurs here
           i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
                            ^~~~
   drivers/gpu/drm/i915/i915_utils.h:73:16: note: expanded from macro 'i915_probe_error'
           __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
                         ^~~~
   drivers/gpu/drm/i915/i915_driver.c:758:2: note: remove the 'if' if its condition is always false
           if (ret)
           ^~~~~~~~
   drivers/gpu/drm/i915/i915_driver.c:754:31: note: initialize the variable 'i915' to silence this warning
           struct drm_i915_private *i915;
                                        ^
                                         = NULL
   1 warning generated.


vim +758 drivers/gpu/drm/i915/i915_driver.c

55ac5a1614f998 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2018-09-05  740  
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  741  /**
b01558e56f8486 drivers/gpu/drm/i915/i915_drv.c    Janusz Krzysztofik     2019-07-12  742   * i915_driver_probe - setup chip and create an initial config
d2ad3ae4ecf582 drivers/gpu/drm/i915/i915_drv.c    Joonas Lahtinen        2016-11-10  743   * @pdev: PCI device
d2ad3ae4ecf582 drivers/gpu/drm/i915/i915_drv.c    Joonas Lahtinen        2016-11-10  744   * @ent: matching PCI ID entry
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  745   *
b01558e56f8486 drivers/gpu/drm/i915/i915_drv.c    Janusz Krzysztofik     2019-07-12  746   * The driver probe routine has to do several things:
86a1758d751de0 drivers/gpu/drm/i915/i915_driver.c Jani Nikula            2023-04-14  747   *   - drive output discovery via intel_display_driver_probe()
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  748   *   - initialize the memory manager
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  749   *   - allocate initial config memory
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  750   *   - setup the DRM framebuffer with the allocated memory
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  751   */
b01558e56f8486 drivers/gpu/drm/i915/i915_drv.c    Janusz Krzysztofik     2019-07-12  752  int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  753  {
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  754  	struct drm_i915_private *i915;
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  755  	int ret;
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  756  
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  757  	ret = pci_enable_device(pdev);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24 @758  	if (ret)
cad3688ff00656 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2017-02-10  759  		goto out_fini;
7d87a7f709650b drivers/gpu/drm/i915/i915_drv.c    Ville Syrjälä          2014-04-09  760  
fc14367208dfb3 drivers/gpu/drm/i915/i915_driver.c Matt Roper             2023-05-17  761  	i915 = i915_driver_create(pdev, ent);
fc14367208dfb3 drivers/gpu/drm/i915/i915_driver.c Matt Roper             2023-05-17  762  	if (IS_ERR(i915)) {
fc14367208dfb3 drivers/gpu/drm/i915/i915_driver.c Matt Roper             2023-05-17  763  		ret = PTR_ERR(i915);
fc14367208dfb3 drivers/gpu/drm/i915/i915_driver.c Matt Roper             2023-05-17  764  		goto out_pci_disable;
fc14367208dfb3 drivers/gpu/drm/i915/i915_driver.c Matt Roper             2023-05-17  765  	}
fc14367208dfb3 drivers/gpu/drm/i915/i915_driver.c Matt Roper             2023-05-17  766  
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  767  	ret = i915_driver_early_probe(i915);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  768  	if (ret < 0)
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  769  		goto out_pci_disable;
719388e146c34f drivers/gpu/drm/i915/i915_drv.c    Damien Lespiau         2015-02-04  770  
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  771  	disable_rpm_wakeref_asserts(&i915->runtime_pm);
1347f5b46a270d drivers/gpu/drm/i915/i915_drv.c    Damien Lespiau         2015-03-17  772  
9e859eb9d0f5e3 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-27  773  	intel_vgpu_detect(i915);
9e138ea1bdb1d1 drivers/gpu/drm/i915/i915_drv.c    Daniele Ceraolo Spurio 2019-06-19  774  
bec68cc9ea42d8 drivers/gpu/drm/i915/i915_driver.c Tvrtko Ursulin         2022-03-19  775  	ret = intel_gt_probe_all(i915);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  776  	if (ret < 0)
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  777  		goto out_runtime_pm_put;
ef11bdb3e00a3f drivers/gpu/drm/i915/i915_drv.c    Rodrigo Vivi           2015-10-28  778  
bec68cc9ea42d8 drivers/gpu/drm/i915/i915_driver.c Tvrtko Ursulin         2022-03-19  779  	ret = i915_driver_mmio_probe(i915);
bec68cc9ea42d8 drivers/gpu/drm/i915/i915_driver.c Tvrtko Ursulin         2022-03-19  780  	if (ret < 0)
bec68cc9ea42d8 drivers/gpu/drm/i915/i915_driver.c Tvrtko Ursulin         2022-03-19  781  		goto out_tiles_cleanup;
bec68cc9ea42d8 drivers/gpu/drm/i915/i915_driver.c Tvrtko Ursulin         2022-03-19  782  
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  783  	ret = i915_driver_hw_probe(i915);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  784  	if (ret < 0)
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  785  		goto out_cleanup_mmio;
ef11bdb3e00a3f drivers/gpu/drm/i915/i915_drv.c    Rodrigo Vivi           2015-10-28  786  
86a1758d751de0 drivers/gpu/drm/i915/i915_driver.c Jani Nikula            2023-04-14  787  	ret = intel_display_driver_probe_noirq(i915);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  788  	if (ret < 0)
baf54385af7856 drivers/gpu/drm/i915/i915_drv.c    Daniel Vetter          2017-06-21  789  		goto out_cleanup_hw;
79e539453b34e3 drivers/gpu/drm/i915/i915_drv.c    Jesse Barnes           2008-11-07  790  
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  791  	ret = intel_irq_install(i915);
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  792  	if (ret)
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  793  		goto out_cleanup_modeset;
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  794  
86a1758d751de0 drivers/gpu/drm/i915/i915_driver.c Jani Nikula            2023-04-14  795  	ret = intel_display_driver_probe_nogem(i915);
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  796  	if (ret)
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  797  		goto out_cleanup_irq;
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  798  
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  799  	ret = i915_gem_init(i915);
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  800  	if (ret)
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  801  		goto out_cleanup_modeset2;
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  802  
f67986b0119c04 drivers/gpu/drm/i915/i915_driver.c Alan Previn            2022-12-08  803  	intel_pxp_init(i915);
f67986b0119c04 drivers/gpu/drm/i915/i915_driver.c Alan Previn            2022-12-08  804  
86a1758d751de0 drivers/gpu/drm/i915/i915_driver.c Jani Nikula            2023-04-14  805  	ret = intel_display_driver_probe(i915);
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  806  	if (ret)
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  807  		goto out_cleanup_gem;
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  808  
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  809  	i915_driver_register(i915);
30c964a6cb7bba drivers/gpu/drm/i915/i915_drv.c    Robert Beckett         2015-08-28  810  
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  811  	enable_rpm_wakeref_asserts(&i915->runtime_pm);
30c964a6cb7bba drivers/gpu/drm/i915/i915_drv.c    Robert Beckett         2015-08-28  812  
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  813  	i915_welcome_messages(i915);
27d558a1a0ab07 drivers/gpu/drm/i915/i915_drv.c    Michal Wajdeczko       2017-12-21  814  
7fb81e9d80738e drivers/gpu/drm/i915/i915_drv.c    Daniel Vetter          2020-03-23  815  	i915->do_release = true;
7fb81e9d80738e drivers/gpu/drm/i915/i915_drv.c    Daniel Vetter          2020-03-23  816  
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  817  	return 0;
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  818  
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  819  out_cleanup_gem:
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  820  	i915_gem_suspend(i915);
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  821  	i915_gem_driver_remove(i915);
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  822  	i915_gem_driver_release(i915);
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  823  out_cleanup_modeset2:
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  824  	/* FIXME clean up the error path */
86a1758d751de0 drivers/gpu/drm/i915/i915_driver.c Jani Nikula            2023-04-14  825  	intel_display_driver_remove(i915);
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  826  	intel_irq_uninstall(i915);
86a1758d751de0 drivers/gpu/drm/i915/i915_driver.c Jani Nikula            2023-04-14  827  	intel_display_driver_remove_noirq(i915);
d6843dda38dfa6 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-09-02  828  	goto out_cleanup_modeset;
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  829  out_cleanup_irq:
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  830  	intel_irq_uninstall(i915);
b664259f3fe2c7 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-19  831  out_cleanup_modeset:
86a1758d751de0 drivers/gpu/drm/i915/i915_driver.c Jani Nikula            2023-04-14  832  	intel_display_driver_remove_nogem(i915);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  833  out_cleanup_hw:
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  834  	i915_driver_hw_remove(i915);
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  835  	intel_memory_regions_driver_release(i915);
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  836  	i915_ggtt_driver_release(i915);
4d8151ae5329cf drivers/gpu/drm/i915/i915_drv.c    Thomas Hellström       2021-06-01  837  	i915_gem_drain_freed_objects(i915);
4d8151ae5329cf drivers/gpu/drm/i915/i915_drv.c    Thomas Hellström       2021-06-01  838  	i915_ggtt_driver_late_release(i915);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  839  out_cleanup_mmio:
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  840  	i915_driver_mmio_release(i915);
bec68cc9ea42d8 drivers/gpu/drm/i915/i915_driver.c Tvrtko Ursulin         2022-03-19  841  out_tiles_cleanup:
bec68cc9ea42d8 drivers/gpu/drm/i915/i915_driver.c Tvrtko Ursulin         2022-03-19  842  	intel_gt_release_all(i915);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  843  out_runtime_pm_put:
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  844  	enable_rpm_wakeref_asserts(&i915->runtime_pm);
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  845  	i915_driver_late_release(i915);
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  846  out_pci_disable:
0673ad472b9849 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2016-06-24  847  	pci_disable_device(pdev);
cad3688ff00656 drivers/gpu/drm/i915/i915_drv.c    Chris Wilson           2017-02-10  848  out_fini:
8eecfb3985e8c8 drivers/gpu/drm/i915/i915_drv.c    Jani Nikula            2020-02-11  849  	i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
30c964a6cb7bba drivers/gpu/drm/i915/i915_drv.c    Robert Beckett         2015-08-28  850  	return ret;
30c964a6cb7bba drivers/gpu/drm/i915/i915_drv.c    Robert Beckett         2015-08-28  851  }
30c964a6cb7bba drivers/gpu/drm/i915/i915_drv.c    Robert Beckett         2015-08-28  852  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[-- Attachment #2: config --]
[-- Type: text/plain, Size: 133102 bytes --]

#
# Automatically generated file; DO NOT EDIT.
# Linux/i386 6.4.0-rc2 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="clang version 14.0.6 (git://gitmirror/llvm_project f28c006a5895fc0e329fe15fead81e37457cb1d1)"
CONFIG_GCC_VERSION=0
CONFIG_CC_IS_CLANG=y
CONFIG_CLANG_VERSION=140006
CONFIG_AS_IS_LLVM=y
CONFIG_AS_VERSION=140006
CONFIG_LD_VERSION=0
CONFIG_LD_IS_LLD=y
CONFIG_LLD_VERSION=140006
CONFIG_RUST_IS_AVAILABLE=y
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=125
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
CONFIG_UAPI_HEADER_TEST=y
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_HAVE_KERNEL_ZSTD=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
# CONFIG_KERNEL_ZSTD is not set
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
CONFIG_WATCH_QUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_USELIB=y
# CONFIG_AUDIT is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_PENDING_IRQ=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_GENERIC_IRQ_DEBUGFS=y
# end of IRQ subsystem

CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_ARCH_CLOCKSOURCE_INIT=y
CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
CONFIG_NO_HZ=y
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=125
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
# CONFIG_BPF_JIT is not set
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_DYNAMIC is not set
CONFIG_SCHED_CORE=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
CONFIG_PSI=y
CONFIG_PSI_DEFAULT_DISABLED=y
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_RCU_EXPERT=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_FORCE_TASKS_RCU=y
CONFIG_TASKS_RCU=y
CONFIG_FORCE_TASKS_RUDE_RCU=y
CONFIG_TASKS_RUDE_RCU=y
CONFIG_FORCE_TASKS_TRACE_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_FANOUT=32
CONFIG_RCU_FANOUT_LEAF=16
# CONFIG_RCU_NOCB_CPU is not set
# CONFIG_TASKS_TRACE_RCU_READ_MB is not set
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_IKHEADERS=y
CONFIG_LOG_BUF_SHIFT=20
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_INDEX=y
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y

#
# Scheduler features
#
# end of Scheduler features

CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough"
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_CGROUPS=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
# CONFIG_MEMCG is not set
# CONFIG_BLK_CGROUP is not set
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_CFS_BANDWIDTH is not set
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_SCHED_MM_CID=y
CONFIG_CGROUP_PIDS=y
# CONFIG_CGROUP_RDMA is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CGROUP_HUGETLB is not set
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
# CONFIG_CGROUP_PERF is not set
# CONFIG_CGROUP_BPF is not set
# CONFIG_CGROUP_MISC is not set
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_TIME_NS is not set
CONFIG_USER_NS=y
# CONFIG_PID_NS is not set
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_FORCE is not set
# CONFIG_BOOT_CONFIG_EMBED is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
# CONFIG_EXPERT is not set
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

# CONFIG_PROFILING is not set
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_X86_32=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf32-i386"
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_BUG=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_X86_32_SMP=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=2

#
# Processor type and features
#
CONFIG_SMP=y
CONFIG_X86_FEATURE_NAMES=y
CONFIG_X86_MPPARSE=y
# CONFIG_GOLDFISH is not set
# CONFIG_X86_CPU_RESCTRL is not set
# CONFIG_X86_BIGSMP is not set
# CONFIG_X86_EXTENDED_PLATFORM is not set
# CONFIG_X86_INTEL_LPSS is not set
# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
CONFIG_IOSF_MBI=y
CONFIG_IOSF_MBI_DEBUG=y
CONFIG_X86_32_IRIS=y
# CONFIG_SCHED_OMIT_FRAME_POINTER is not set
CONFIG_HYPERVISOR_GUEST=y
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_DEBUG is not set
CONFIG_PARAVIRT_SPINLOCKS=y
CONFIG_X86_HV_CALLBACK_VECTOR=y
CONFIG_KVM_GUEST=y
CONFIG_ARCH_CPUIDLE_HALTPOLL=y
# CONFIG_PVH is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_PARAVIRT_CLOCK=y
CONFIG_M486SX=y
# CONFIG_M486 is not set
# CONFIG_M586 is not set
# CONFIG_M586TSC is not set
# CONFIG_M586MMX is not set
# CONFIG_M686 is not set
# CONFIG_MPENTIUMII is not set
# CONFIG_MPENTIUMIII is not set
# CONFIG_MPENTIUMM is not set
# CONFIG_MPENTIUM4 is not set
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
# CONFIG_MCRUSOE is not set
# CONFIG_MEFFICEON is not set
# CONFIG_MWINCHIPC6 is not set
# CONFIG_MWINCHIP3D is not set
# CONFIG_MELAN is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
# CONFIG_MCYRIXIII is not set
# CONFIG_MVIAC3_2 is not set
# CONFIG_MVIAC7 is not set
# CONFIG_MCORE2 is not set
# CONFIG_MATOM is not set
CONFIG_X86_GENERIC=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_F00F_BUG=y
CONFIG_X86_INVD_BUG=y
CONFIG_X86_ALIGNMENT_16=y
CONFIG_X86_INTEL_USERCOPY=y
CONFIG_X86_MINIMUM_CPU_FAMILY=4
CONFIG_IA32_FEAT_CTL=y
CONFIG_X86_VMX_FEATURE_NAMES=y
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_CYRIX_32=y
CONFIG_CPU_SUP_AMD=y
CONFIG_CPU_SUP_HYGON=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_CPU_SUP_TRANSMETA_32=y
CONFIG_CPU_SUP_UMC_32=y
CONFIG_CPU_SUP_ZHAOXIN=y
CONFIG_CPU_SUP_VORTEX_32=y
CONFIG_HPET_TIMER=y
CONFIG_DMI=y
CONFIG_BOOT_VESA_SUPPORT=y
CONFIG_NR_CPUS_RANGE_BEGIN=2
CONFIG_NR_CPUS_RANGE_END=8
CONFIG_NR_CPUS_DEFAULT=8
CONFIG_NR_CPUS=8
CONFIG_SCHED_CLUSTER=y
CONFIG_SCHED_SMT=y
# CONFIG_SCHED_MC is not set
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set
# CONFIG_X86_MCE is not set

#
# Performance monitoring
#
CONFIG_PERF_EVENTS_INTEL_UNCORE=y
CONFIG_PERF_EVENTS_INTEL_RAPL=y
# CONFIG_PERF_EVENTS_INTEL_CSTATE is not set
# CONFIG_PERF_EVENTS_AMD_POWER is not set
# CONFIG_PERF_EVENTS_AMD_UNCORE is not set
# CONFIG_PERF_EVENTS_AMD_BRS is not set
# end of Performance monitoring

CONFIG_X86_LEGACY_VM86=y
CONFIG_VM86=y
CONFIG_X86_16BIT=y
CONFIG_X86_ESPFIX32=y
CONFIG_X86_IOPL_IOPERM=y
CONFIG_TOSHIBA=y
CONFIG_X86_REBOOTFIXUPS=y
CONFIG_MICROCODE=y
CONFIG_MICROCODE_INTEL=y
# CONFIG_MICROCODE_AMD is not set
# CONFIG_MICROCODE_LATE_LOADING is not set
CONFIG_X86_MSR=y
CONFIG_X86_CPUID=y
# CONFIG_NOHIGHMEM is not set
CONFIG_HIGHMEM4G=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_HIGHMEM=y
CONFIG_X86_CPA_STATISTICS=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ILLEGAL_POINTER_VALUE=0
CONFIG_HIGHPTE=y
CONFIG_X86_CHECK_BIOS_CORRUPTION=y
# CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK is not set
# CONFIG_MATH_EMULATION is not set
CONFIG_MTRR=y
CONFIG_MTRR_SANITIZER=y
CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
CONFIG_X86_PAT=y
CONFIG_ARCH_USES_PG_UNCACHED=y
CONFIG_X86_UMIP=y
CONFIG_CC_HAS_IBT=y
# CONFIG_X86_INTEL_TSX_MODE_OFF is not set
# CONFIG_X86_INTEL_TSX_MODE_ON is not set
CONFIG_X86_INTEL_TSX_MODE_AUTO=y
# CONFIG_EFI is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
CONFIG_HZ_1000=y
CONFIG_HZ=1000
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_PHYSICAL_START=0x1000000
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_X86_NEED_RELOCS=y
CONFIG_PHYSICAL_ALIGN=0x200000
CONFIG_HOTPLUG_CPU=y
# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
# CONFIG_COMPAT_VDSO is not set
# CONFIG_CMDLINE_BOOL is not set
CONFIG_MODIFY_LDT_SYSCALL=y
# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
# end of Processor type and features

CONFIG_CC_HAS_ENTRY_PADDING=y
CONFIG_FUNCTION_PADDING_CFI=11
CONFIG_FUNCTION_PADDING_BYTES=16
CONFIG_SPECULATION_MITIGATIONS=y
# CONFIG_RETPOLINE is not set
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y

#
# Power management and ACPI options
#
CONFIG_ARCH_HIBERNATION_HEADER=y
# CONFIG_SUSPEND is not set
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
# CONFIG_HIBERNATION_SNAPSHOT_DEV is not set
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=100
# CONFIG_PM_WAKELOCKS_GC is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_PM_TRACE=y
CONFIG_PM_TRACE_RTC=y
CONFIG_PM_CLK=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
CONFIG_ACPI_TABLE_LIB=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_SLEEP=y
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=y
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_TAD is not set
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_CPU_FREQ_PSS=y
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_PROCESSOR=y
# CONFIG_ACPI_IPMI is not set
CONFIG_ACPI_HOTPLUG_CPU=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_CUSTOM_DSDT_FILE=""
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_SBS is not set
# CONFIG_ACPI_HED is not set
# CONFIG_ACPI_CUSTOM_METHOD is not set
CONFIG_HAVE_ACPI_APEI=y
CONFIG_HAVE_ACPI_APEI_NMI=y
# CONFIG_ACPI_APEI is not set
# CONFIG_ACPI_DPTF is not set
# CONFIG_ACPI_CONFIGFS is not set
# CONFIG_ACPI_FFH is not set
# CONFIG_PMIC_OPREGION is not set
CONFIG_ACPI_VIOT=y
CONFIG_X86_PM_TIMER=y
CONFIG_X86_APM_BOOT=y
CONFIG_APM=y
# CONFIG_APM_IGNORE_USER_SUSPEND is not set
CONFIG_APM_DO_ENABLE=y
# CONFIG_APM_CPU_IDLE is not set
# CONFIG_APM_DISPLAY_BLANK is not set
# CONFIG_APM_ALLOW_INTS is not set

#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
# end of CPU Frequency scaling

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
# CONFIG_CPU_IDLE_GOV_MENU is not set
CONFIG_CPU_IDLE_GOV_TEO=y
CONFIG_CPU_IDLE_GOV_HALTPOLL=y
CONFIG_HALTPOLL_CPUIDLE=y
# end of CPU Idle

CONFIG_INTEL_IDLE=y
# end of Power management and ACPI options

#
# Bus options (PCI etc.)
#
# CONFIG_PCI_GOBIOS is not set
# CONFIG_PCI_GOMMCONFIG is not set
# CONFIG_PCI_GODIRECT is not set
CONFIG_PCI_GOANY=y
CONFIG_PCI_BIOS=y
CONFIG_PCI_DIRECT=y
CONFIG_PCI_MMCONFIG=y
CONFIG_ISA_DMA_API=y
# CONFIG_ISA is not set
CONFIG_SCx200=y
# CONFIG_SCx200HR_TIMER is not set
# CONFIG_OLPC is not set
CONFIG_ALIX=y
# CONFIG_NET5501 is not set
CONFIG_GEOS=y
CONFIG_AMD_NB=y
# end of Bus options (PCI etc.)

#
# Binary Emulations
#
CONFIG_COMPAT_32=y
# end of Binary Emulations

CONFIG_HAVE_ATOMIC_IOMAP=y
CONFIG_HAVE_KVM=y
CONFIG_VIRTUALIZATION=y
CONFIG_AS_AVX512=y
CONFIG_AS_SHA1_NI=y
CONFIG_AS_SHA256_NI=y
CONFIG_AS_TPAUSE=y
CONFIG_AS_GFNI=y

#
# General architecture-dependent options
#
CONFIG_CRASH_CORE=y
CONFIG_HOTPLUG_SMT=y
CONFIG_GENERIC_ENTRY=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
# CONFIG_STATIC_CALL_SELFTEST is not set
CONFIG_OPTPROBES=y
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_KRETPROBES=y
CONFIG_KRETPROBE_ON_RETHOOK=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_GATHER_MERGE_VMAS=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_HAS_LTO_CLANG=y
CONFIG_LTO_NONE=y
# CONFIG_LTO_CLANG_FULL is not set
# CONFIG_LTO_CLANG_THIN is not set
CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=8
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ISA_BUS_API=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_LOCK_EVENT_COUNTS=y
CONFIG_ARCH_HAS_MEM_ENCRYPT=y
CONFIG_HAVE_STATIC_CALL=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SPLIT_ARG64=y
CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
CONFIG_DYNAMIC_SIGFRAME=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT_16B=y
CONFIG_FUNCTION_ALIGNMENT=16
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_WBT=y
# CONFIG_BLK_WBT_MQ is not set
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
# CONFIG_BLK_SED_OPAL is not set
CONFIG_BLK_INLINE_ENCRYPTION=y
# CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
CONFIG_ACORN_PARTITION=y
# CONFIG_ACORN_PARTITION_CUMANA is not set
CONFIG_ACORN_PARTITION_EESOX=y
CONFIG_ACORN_PARTITION_ICS=y
CONFIG_ACORN_PARTITION_ADFS=y
CONFIG_ACORN_PARTITION_POWERTEC=y
# CONFIG_ACORN_PARTITION_RISCIX is not set
CONFIG_AIX_PARTITION=y
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
CONFIG_ATARI_PARTITION=y
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
CONFIG_KARMA_PARTITION=y
# CONFIG_EFI_PARTITION is not set
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
# CONFIG_IOSCHED_BFQ is not set
# end of IO Schedulers

CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SWAP=y
# CONFIG_ZSWAP is not set

#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# end of SLAB allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MEMORY_BALLOON=y
# CONFIG_BALLOON_COMPACTION is not set
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
# CONFIG_BOUNCE is not set
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
# CONFIG_TRANSPARENT_HUGEPAGE is not set
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
# CONFIG_CMA is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ZONE_DMA=y
CONFIG_VMAP_PFN=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_MAPPING_DIRTY_HELPERS=y
CONFIG_KMAP_LOCAL=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
CONFIG_USERFAULTFD=y
# CONFIG_LRU_GEN is not set

#
# Data Access Monitoring
#
CONFIG_DAMON=y
CONFIG_DAMON_VADDR=y
CONFIG_DAMON_PADDR=y
# CONFIG_DAMON_SYSFS is not set
# CONFIG_DAMON_DBGFS is not set
# CONFIG_DAMON_RECLAIM is not set
# CONFIG_DAMON_LRU_SORT is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y

#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_TLS is not set
# CONFIG_XFRM_USER is not set
# CONFIG_NET_KEY is not set
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_NET_HANDSHAKE=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_NET_IP_TUNNEL=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_NET_IPVTI is not set
# CONFIG_NET_FOU is not set
# CONFIG_NET_FOU_IP_TUNNELS is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_INET_UDP_DIAG is not set
# CONFIG_INET_RAW_DIAG is not set
# CONFIG_INET_DIAG_DESTROY is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_IPV6_VTI is not set
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
# CONFIG_IPV6_TUNNEL is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_IPV6_MROUTE is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
# CONFIG_NETLABEL is not set
# CONFIG_MPTCP is not set
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_BPFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
CONFIG_ATM=y
# CONFIG_ATM_CLIP is not set
# CONFIG_ATM_LANE is not set
# CONFIG_ATM_BR2684 is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
CONFIG_LLC=y
# CONFIG_LLC2 is not set
CONFIG_ATALK=y
CONFIG_DEV_APPLETALK=y
CONFIG_IPDDP=y
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
CONFIG_LAPB=y
CONFIG_PHONET=y
# CONFIG_6LOWPAN is not set
CONFIG_IEEE802154=y
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=y
CONFIG_MAC802154=y
# CONFIG_NET_SCHED is not set
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=y
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
# CONFIG_BATMAN_ADV_NC is not set
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_TRACING is not set
# CONFIG_OPENVSWITCH is not set
CONFIG_VSOCKETS=y
CONFIG_VSOCKETS_DIAG=y
CONFIG_VSOCKETS_LOOPBACK=y
# CONFIG_VIRTIO_VSOCKETS is not set
CONFIG_VIRTIO_VSOCKETS_COMMON=y
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
CONFIG_NET_NSH=y
CONFIG_HSR=y
# CONFIG_NET_SWITCHDEV is not set
# CONFIG_NET_L3_MASTER_DEV is not set
CONFIG_QRTR=y
CONFIG_QRTR_SMD=y
CONFIG_QRTR_TUN=y
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_MAX_SKB_FRAGS=17
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
# CONFIG_CGROUP_NET_PRIO is not set
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
CONFIG_CAN=y
# CONFIG_CAN_RAW is not set
CONFIG_CAN_BCM=y
# CONFIG_CAN_GW is not set
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
CONFIG_MCTP=y
# CONFIG_WIRELESS is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
# CONFIG_RFKILL_GPIO is not set
CONFIG_NET_9P=y
CONFIG_NET_9P_FD=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_NET_9P_DEBUG=y
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
CONFIG_NFC=y
# CONFIG_NFC_DIGITAL is not set
CONFIG_NFC_NCI=y
# CONFIG_NFC_NCI_UART is not set
CONFIG_NFC_HCI=y
# CONFIG_NFC_SHDLC is not set

#
# Near Field Communication (NFC) devices
#
CONFIG_NFC_MEI_PHY=y
CONFIG_NFC_VIRTUAL_NCI=y
CONFIG_NFC_FDP=y
# CONFIG_NFC_FDP_I2C is not set
CONFIG_NFC_PN544=y
CONFIG_NFC_PN544_MEI=y
CONFIG_NFC_PN533=y
CONFIG_NFC_PN533_I2C=y
CONFIG_NFC_PN532_UART=y
CONFIG_NFC_MICROREAD=y
CONFIG_NFC_MICROREAD_MEI=y
CONFIG_NFC_ST_NCI=y
CONFIG_NFC_ST_NCI_I2C=y
CONFIG_NFC_NXP_NCI=y
CONFIG_NFC_NXP_NCI_I2C=y
CONFIG_NFC_S3FWRN5=y
# CONFIG_NFC_S3FWRN5_I2C is not set
CONFIG_NFC_S3FWRN82_UART=y
# end of Near Field Communication (NFC) devices

CONFIG_PSAMPLE=y
CONFIG_NET_IFE=y
# CONFIG_LWTUNNEL is not set
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_FAILOVER=y
# CONFIG_ETHTOOL_NETLINK is not set

#
# Device Drivers
#
CONFIG_HAVE_EISA=y
CONFIG_EISA=y
# CONFIG_EISA_VLB_PRIMING is not set
# CONFIG_EISA_PCI_EISA is not set
# CONFIG_EISA_VIRTUAL_ROOT is not set
# CONFIG_EISA_NAMES is not set
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
CONFIG_PCIEASPM_POWER_SUPERSAVE=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
CONFIG_PCI_STUB=y
CONFIG_PCI_ATS=y
CONFIG_PCI_DOE=y
CONFIG_PCI_LOCKLESS_CONFIG=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#

#
# Cadence-based PCIe controllers
#
# end of Cadence-based PCIe controllers

#
# DesignWare-based PCIe controllers
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
CONFIG_PCI_MESON=y
CONFIG_PCIE_DW_PLAT=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_DW_PLAT_EP=y
# end of DesignWare-based PCIe controllers

#
# Mobiveil-based PCIe controllers
#
# end of Mobiveil-based PCIe controllers
# end of PCI controller drivers

#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
# CONFIG_PCI_EPF_TEST is not set
CONFIG_PCI_EPF_NTB=y
# CONFIG_PCI_EPF_VNTB is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=y
# end of PCI switch controller drivers

CONFIG_CXL_BUS=y
CONFIG_CXL_PCI=y
CONFIG_CXL_MEM_RAW_COMMANDS=y
CONFIG_CXL_ACPI=y
CONFIG_CXL_MEM=y
CONFIG_CXL_PORT=y
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
# CONFIG_STANDALONE is not set
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
# CONFIG_FW_LOADER_COMPRESS_ZSTD is not set
# CONFIG_FW_CACHE is not set
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
# end of Generic Driver Options

#
# Bus devices
#
# CONFIG_MHI_BUS is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
# end of ARM System Control and Management Interface Protocol

CONFIG_EDD=y
CONFIG_EDD_OFF=y
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_DMIID=y
# CONFIG_DMI_SYSFS is not set
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
# CONFIG_FW_CFG_SYSFS is not set
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
# CONFIG_GOOGLE_FIRMWARE is not set

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=y
CONFIG_GNSS_SERIAL=y
# CONFIG_GNSS_MTK_SERIAL is not set
CONFIG_GNSS_SIRF_SERIAL=y
CONFIG_GNSS_UBX_SERIAL=y
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
CONFIG_MTD_AR7_PARTS=y
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
CONFIG_FTL=y
CONFIG_NFTL=y
# CONFIG_NFTL_RW is not set
CONFIG_INFTL=y
CONFIG_RFD_FTL=y
CONFIG_SSFDC=y
# CONFIG_SM_FTL is not set
CONFIG_MTD_OOPS=y
CONFIG_MTD_SWAP=y
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_MTD_ABSENT=y
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_SCx200_DOCFLASH is not set
# CONFIG_MTD_PCI is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
CONFIG_MTD_PLATRAM=y
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
CONFIG_MTD_PMC551=y
# CONFIG_MTD_PMC551_BUGFIX is not set
# CONFIG_MTD_PMC551_DEBUG is not set
# CONFIG_MTD_SLRAM is not set
CONFIG_MTD_PHRAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=4096
CONFIG_MTDRAM_ERASE_SIZE=128
CONFIG_MTD_BLOCK2MTD=y

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=y
# CONFIG_MTD_ONENAND_OTP is not set
CONFIG_MTD_ONENAND_2X_PROGRAM=y
CONFIG_MTD_RAW_NAND=y

#
# Raw/parallel NAND flash controllers
#
# CONFIG_MTD_NAND_DENALI_PCI is not set
CONFIG_MTD_NAND_CAFE=y
CONFIG_MTD_NAND_CS553X=y
CONFIG_MTD_NAND_MXIC=y
# CONFIG_MTD_NAND_GPIO is not set
# CONFIG_MTD_NAND_PLATFORM is not set
CONFIG_MTD_NAND_ARASAN=y

#
# Misc
#
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_RICOH is not set
CONFIG_MTD_NAND_DISKONCHIP=y
# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
CONFIG_MTD_NAND_ECC_SW_BCH=y
# CONFIG_MTD_NAND_ECC_MXIC is not set
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_FASTMAP=y
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
CONFIG_MTD_HYPERBUS=y
# CONFIG_OF is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_PARPORT=y
CONFIG_PARPORT_PC=y
# CONFIG_PARPORT_SERIAL is not set
CONFIG_PARPORT_PC_FIFO=y
# CONFIG_PARPORT_PC_SUPERIO is not set
# CONFIG_PARPORT_1284 is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
# CONFIG_ZRAM is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_VIRTIO_BLK is not set
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_VERBOSE_ERRORS is not set
# CONFIG_NVME_HWMON is not set
CONFIG_NVME_FABRICS=y
CONFIG_NVME_FC=y
# CONFIG_NVME_TCP is not set
# CONFIG_NVME_AUTH is not set
CONFIG_NVME_TARGET=y
# CONFIG_NVME_TARGET_PASSTHRU is not set
# CONFIG_NVME_TARGET_LOOP is not set
CONFIG_NVME_TARGET_FC=y
CONFIG_NVME_TARGET_FCLOOP=y
# CONFIG_NVME_TARGET_TCP is not set
# CONFIG_NVME_TARGET_AUTH is not set
# end of NVME Support

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=y
CONFIG_AD525X_DPOT=y
# CONFIG_AD525X_DPOT_I2C is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_IBM_ASM is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=y
# CONFIG_TIFM_7XX1 is not set
CONFIG_ICS932S401=y
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_CS5535_MFGPT is not set
CONFIG_HP_ILO=y
# CONFIG_APDS9802ALS is not set
CONFIG_ISL29003=y
CONFIG_ISL29020=y
CONFIG_SENSORS_TSL2550=y
CONFIG_SENSORS_BH1770=y
CONFIG_SENSORS_APDS990X=y
CONFIG_HMC6352=y
CONFIG_DS1682=y
CONFIG_PCH_PHUB=y
# CONFIG_SRAM is not set
CONFIG_DW_XDATA_PCIE=y
# CONFIG_PCI_ENDPOINT_TEST is not set
CONFIG_XILINX_SDFEC=y
CONFIG_C2PORT=y
CONFIG_C2PORT_DURAMAR_2150=y

#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_LEGACY=y
CONFIG_EEPROM_MAX6875=y
CONFIG_EEPROM_93CX6=y
CONFIG_EEPROM_IDT_89HPESX=y
CONFIG_EEPROM_EE1004=y
# end of EEPROM support

CONFIG_CB710_CORE=y
CONFIG_CB710_DEBUG=y
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
CONFIG_TI_ST=y
# end of Texas Instruments shared transport line discipline

CONFIG_SENSORS_LIS3_I2C=y
CONFIG_ALTERA_STAPL=y
CONFIG_INTEL_MEI=y
CONFIG_INTEL_MEI_ME=y
# CONFIG_INTEL_MEI_TXE is not set
# CONFIG_INTEL_MEI_GSC is not set
CONFIG_INTEL_MEI_HDCP=y
CONFIG_INTEL_MEI_PXP=y
# CONFIG_INTEL_MEI_GSC_PROXY is not set
# CONFIG_VMWARE_VMCI is not set
# CONFIG_ECHO is not set
CONFIG_BCM_VK=y
CONFIG_BCM_VK_TTY=y
CONFIG_MISC_ALCOR_PCI=y
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_UACCE=y
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=y
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_PROC_FS is not set

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_BLK_DEV_SR is not set
CONFIG_CHR_DEV_SG=y
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=y
CONFIG_SCSI_SAS_ATTRS=y
# CONFIG_SCSI_SAS_LIBSAS is not set
CONFIG_SCSI_SRP_ATTRS=y
# end of SCSI Transports

# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
# CONFIG_SATA_PMP is not set

#
# Controllers with non-SFF native interface
#
# CONFIG_SATA_AHCI is not set
# CONFIG_SATA_AHCI_PLATFORM is not set
# CONFIG_AHCI_DWC is not set
# CONFIG_SATA_INIC162X is not set
CONFIG_SATA_ACARD_AHCI=y
# CONFIG_SATA_SIL24 is not set
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
CONFIG_PDC_ADMA=y
CONFIG_SATA_QSTOR=y
CONFIG_SATA_SX4=y
# CONFIG_ATA_BMDMA is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
CONFIG_PATA_MPIIX=y
CONFIG_PATA_NS87410=y
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_RZ1000 is not set
# CONFIG_PATA_PARPORT is not set

#
# Generic fallback / legacy drivers
#
CONFIG_PATA_LEGACY=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
# CONFIG_MD_AUTODETECT is not set
CONFIG_MD_LINEAR=y
CONFIG_MD_RAID0=y
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID10 is not set
# CONFIG_MD_RAID456 is not set
# CONFIG_MD_MULTIPATH is not set
# CONFIG_MD_FAULTY is not set
CONFIG_BCACHE=y
# CONFIG_BCACHE_DEBUG is not set
CONFIG_BCACHE_CLOSURES_DEBUG=y
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=y
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=y
CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y
CONFIG_DM_DEBUG_BLOCK_STACK_TRACING=y
CONFIG_DM_BIO_PRISON=y
CONFIG_DM_PERSISTENT_DATA=y
CONFIG_DM_UNSTRIPED=y
CONFIG_DM_CRYPT=y
CONFIG_DM_SNAPSHOT=y
# CONFIG_DM_THIN_PROVISIONING is not set
CONFIG_DM_CACHE=y
CONFIG_DM_CACHE_SMQ=y
# CONFIG_DM_WRITECACHE is not set
# CONFIG_DM_ERA is not set
CONFIG_DM_CLONE=y
CONFIG_DM_MIRROR=y
# CONFIG_DM_LOG_USERSPACE is not set
# CONFIG_DM_RAID is not set
CONFIG_DM_ZERO=y
CONFIG_DM_MULTIPATH=y
CONFIG_DM_MULTIPATH_QL=y
CONFIG_DM_MULTIPATH_ST=y
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
# CONFIG_DM_DELAY is not set
CONFIG_DM_DUST=y
CONFIG_DM_INIT=y
CONFIG_DM_UEVENT=y
# CONFIG_DM_FLAKEY is not set
CONFIG_DM_VERITY=y
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_SWITCH=y
CONFIG_DM_LOG_WRITES=y
CONFIG_DM_INTEGRITY=y
# CONFIG_DM_ZONED is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
CONFIG_FIREWIRE=y
CONFIG_FIREWIRE_OHCI=y
CONFIG_FIREWIRE_SBP2=y
# CONFIG_FIREWIRE_NET is not set
CONFIG_FIREWIRE_NOSY=y
# end of IEEE 1394 (FireWire) support

# CONFIG_MACINTOSH_DRIVERS is not set
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
CONFIG_DUMMY=y
# CONFIG_WIREGUARD is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_FC is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_IPVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_GENEVE is not set
# CONFIG_BAREUDP is not set
# CONFIG_GTP is not set
CONFIG_MACSEC=y
CONFIG_NETCONSOLE=y
# CONFIG_NETCONSOLE_DYNAMIC is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_NTB_NETDEV=y
# CONFIG_TUN is not set
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=y
CONFIG_VIRTIO_NET=y
CONFIG_NLMON=y
CONFIG_VSOCKMON=y
CONFIG_ARCNET=y
# CONFIG_ARCNET_1201 is not set
CONFIG_ARCNET_1051=y
CONFIG_ARCNET_RAW=y
CONFIG_ARCNET_CAP=y
CONFIG_ARCNET_COM90xx=y
# CONFIG_ARCNET_COM90xxIO is not set
# CONFIG_ARCNET_RIM_I is not set
CONFIG_ARCNET_COM20020=y
CONFIG_ARCNET_COM20020_PCI=y
CONFIG_ATM_DRIVERS=y
# CONFIG_ATM_DUMMY is not set
# CONFIG_ATM_TCP is not set
# CONFIG_ATM_LANAI is not set
CONFIG_ATM_ENI=y
# CONFIG_ATM_ENI_DEBUG is not set
# CONFIG_ATM_ENI_TUNE_BURST is not set
# CONFIG_ATM_NICSTAR is not set
CONFIG_ATM_IDT77252=y
# CONFIG_ATM_IDT77252_DEBUG is not set
CONFIG_ATM_IDT77252_RCV_ALL=y
CONFIG_ATM_IDT77252_USE_SUNI=y
# CONFIG_ATM_IA is not set
CONFIG_ATM_FORE200E=y
# CONFIG_ATM_FORE200E_USE_TASKLET is not set
CONFIG_ATM_FORE200E_TX_RETRY=16
CONFIG_ATM_FORE200E_DEBUG=0
CONFIG_ATM_HE=y
CONFIG_ATM_HE_USE_SUNI=y
CONFIG_ATM_SOLOS=y
CONFIG_ETHERNET=y
CONFIG_MDIO=y
CONFIG_NET_VENDOR_3COM=y
# CONFIG_EL3 is not set
# CONFIG_VORTEX is not set
CONFIG_TYPHOON=y
CONFIG_NET_VENDOR_ADAPTEC=y
CONFIG_ADAPTEC_STARFIRE=y
# CONFIG_NET_VENDOR_AGERE is not set
CONFIG_NET_VENDOR_ALACRITECH=y
CONFIG_SLICOSS=y
# CONFIG_NET_VENDOR_ALTEON is not set
CONFIG_ALTERA_TSE=y
CONFIG_NET_VENDOR_AMAZON=y
CONFIG_ENA_ETHERNET=y
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ASIX is not set
CONFIG_NET_VENDOR_ATHEROS=y
CONFIG_ATL2=y
# CONFIG_ATL1 is not set
CONFIG_ATL1E=y
CONFIG_ATL1C=y
CONFIG_ALX=y
CONFIG_CX_ECAT=y
CONFIG_NET_VENDOR_BROADCOM=y
CONFIG_B44=y
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI=y
# CONFIG_BCMGENET is not set
CONFIG_BNX2=y
CONFIG_CNIC=y
CONFIG_TIGON3=y
CONFIG_TIGON3_HWMON=y
CONFIG_BNX2X=y
CONFIG_SYSTEMPORT=y
CONFIG_BNXT=y
CONFIG_BNXT_FLOWER_OFFLOAD=y
# CONFIG_BNXT_DCB is not set
CONFIG_BNXT_HWMON=y
# CONFIG_NET_VENDOR_CADENCE is not set
CONFIG_NET_VENDOR_CAVIUM=y
CONFIG_NET_VENDOR_CHELSIO=y
CONFIG_CHELSIO_T1=y
# CONFIG_CHELSIO_T1_1G is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_CHELSIO_T4 is not set
CONFIG_CHELSIO_T4VF=y
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
CONFIG_NET_VENDOR_DAVICOM=y
CONFIG_DNET=y
CONFIG_NET_VENDOR_DEC=y
CONFIG_NET_TULIP=y
CONFIG_DE2104X=y
CONFIG_DE2104X_DSL=0
CONFIG_TULIP=y
CONFIG_TULIP_MWI=y
# CONFIG_TULIP_MMIO is not set
# CONFIG_TULIP_NAPI is not set
CONFIG_WINBOND_840=y
CONFIG_DM9102=y
CONFIG_ULI526X=y
CONFIG_NET_VENDOR_DLINK=y
CONFIG_DL2K=y
CONFIG_SUNDANCE=y
CONFIG_SUNDANCE_MMIO=y
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_ENGLEDER is not set
CONFIG_NET_VENDOR_EZCHIP=y
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
CONFIG_NET_VENDOR_GOOGLE=y
CONFIG_GVE=y
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=y
# CONFIG_E1000E is not set
# CONFIG_IGB is not set
# CONFIG_IGBVF is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
# CONFIG_IGC is not set
CONFIG_JME=y
# CONFIG_NET_VENDOR_LITEX is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
CONFIG_NET_VENDOR_MICREL=y
CONFIG_KS8851_MLL=y
CONFIG_KSZ884X_PCI=y
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_MYRI=y
# CONFIG_MYRI10GE is not set
CONFIG_FEALNX=y
CONFIG_NET_VENDOR_NI=y
CONFIG_NI_XGE_MANAGEMENT_ENET=y
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NATSEMI=y
CONFIG_NS83820=y
# CONFIG_NET_VENDOR_NETERION is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_8390=y
# CONFIG_NE2K_PCI is not set
CONFIG_NET_VENDOR_NVIDIA=y
# CONFIG_FORCEDETH is not set
CONFIG_NET_VENDOR_OKI=y
# CONFIG_PCH_GBE is not set
CONFIG_ETHOC=y
CONFIG_NET_VENDOR_PACKET_ENGINES=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
CONFIG_NET_VENDOR_BROCADE=y
# CONFIG_BNA is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
CONFIG_ATP=y
CONFIG_8139CP=y
CONFIG_8139TOO=y
# CONFIG_8139TOO_PIO is not set
CONFIG_8139TOO_TUNE_TWISTER=y
# CONFIG_8139TOO_8129 is not set
# CONFIG_8139_OLD_RX_RESET is not set
CONFIG_R8169=y
CONFIG_NET_VENDOR_RENESAS=y
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_NET_VENDOR_SILAN=y
CONFIG_SC92031=y
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_NET_VENDOR_SOCIONEXT=y
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SUN is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
CONFIG_FDDI=y
CONFIG_DEFXX=y
# CONFIG_SKFP is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_SFP=y

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
CONFIG_ADIN_PHY=y
# CONFIG_ADIN1100_PHY is not set
CONFIG_AQUANTIA_PHY=y
CONFIG_AX88796B_PHY=y
# CONFIG_BROADCOM_PHY is not set
CONFIG_BCM54140_PHY=y
CONFIG_BCM7XXX_PHY=y
CONFIG_BCM84881_PHY=y
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=y
CONFIG_CICADA_PHY=y
# CONFIG_CORTINA_PHY is not set
CONFIG_DAVICOM_PHY=y
# CONFIG_ICPLUS_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
CONFIG_LSI_ET1011C_PHY=y
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
CONFIG_MARVELL_88X2222_PHY=y
CONFIG_MAXLINEAR_GPHY=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MICREL_PHY=y
# CONFIG_MICROCHIP_T1S_PHY is not set
CONFIG_MICROCHIP_PHY=y
CONFIG_MICROCHIP_T1_PHY=y
CONFIG_MICROSEMI_PHY=y
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_CBTX_PHY is not set
CONFIG_NXP_C45_TJA11XX_PHY=y
CONFIG_NXP_TJA11XX_PHY=y
# CONFIG_NCN26000_PHY is not set
CONFIG_AT803X_PHY=y
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
# CONFIG_ROCKCHIP_PHY is not set
CONFIG_SMSC_PHY=y
# CONFIG_STE10XP is not set
CONFIG_TERANETICS_PHY=y
# CONFIG_DP83822_PHY is not set
CONFIG_DP83TC811_PHY=y
CONFIG_DP83848_PHY=y
# CONFIG_DP83867_PHY is not set
CONFIG_DP83869_PHY=y
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=y
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_PSE_CONTROLLER is not set
# CONFIG_CAN_DEV is not set

#
# MCTP Device Drivers
#
CONFIG_MCTP_SERIAL=y
# CONFIG_MCTP_TRANSPORT_I2C is not set
# end of MCTP Device Drivers

CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BCM_UNIMAC=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_I2C=y
# CONFIG_MDIO_MSCC_MIIM is not set

#
# MDIO Multiplexers
#

#
# PCS device drivers
#
CONFIG_PCS_ALTERA_TSE=y
# end of PCS device drivers

CONFIG_PLIP=y
# CONFIG_PPP is not set
CONFIG_SLIP=y
# CONFIG_SLIP_COMPRESSED is not set
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y

#
# Host-side USB support is needed for USB Network Adapter support
#
# CONFIG_WLAN is not set
CONFIG_WAN=y
# CONFIG_HDLC is not set
# CONFIG_IEEE802154_DRIVERS is not set

#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN

# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_USB4_NET is not set
# CONFIG_NETDEVSIM is not set
CONFIG_NET_FAILOVER=y
CONFIG_ISDN=y
CONFIG_MISDN=y
# CONFIG_MISDN_DSP is not set
CONFIG_MISDN_L1OIP=y

#
# mISDN hardware drivers
#
CONFIG_MISDN_HFCPCI=y
CONFIG_MISDN_HFCMULTI=y
CONFIG_MISDN_AVMFRITZ=y
CONFIG_MISDN_SPEEDFAX=y
# CONFIG_MISDN_INFINEON is not set
# CONFIG_MISDN_W6692 is not set
# CONFIG_MISDN_NETJET is not set
CONFIG_MISDN_IPAC=y
CONFIG_MISDN_ISAR=y

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_VIVALDIFMAP=y

#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADP5588=y
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
CONFIG_KEYBOARD_QT1050=y
CONFIG_KEYBOARD_QT1070=y
CONFIG_KEYBOARD_QT2160=y
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_KEYBOARD_TCA6416=y
CONFIG_KEYBOARD_TCA8418=y
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
CONFIG_KEYBOARD_LM8333=y
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
CONFIG_KEYBOARD_MPR121=y
CONFIG_KEYBOARD_NEWTON=y
CONFIG_KEYBOARD_OPENCORES=y
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
CONFIG_KEYBOARD_STOWAWAY=y
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_TM2_TOUCHKEY=y
CONFIG_KEYBOARD_XTKBD=y
# CONFIG_KEYBOARD_CROS_EC is not set
CONFIG_KEYBOARD_MTK_PMIC=y
CONFIG_KEYBOARD_CYPRESS_SF=y
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_VMMOUSE=y
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
CONFIG_MOUSE_ELAN_I2C=y
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=y
CONFIG_MOUSE_GPIO=y
CONFIG_MOUSE_SYNAPTICS_I2C=y
# CONFIG_MOUSE_SYNAPTICS_USB is not set
# CONFIG_INPUT_JOYSTICK is not set
CONFIG_INPUT_TABLET=y
# CONFIG_TABLET_USB_ACECAD is not set
# CONFIG_TABLET_USB_AIPTEK is not set
# CONFIG_TABLET_USB_HANWANG is not set
# CONFIG_TABLET_USB_KBTAB is not set
# CONFIG_TABLET_USB_PEGASUS is not set
# CONFIG_TABLET_SERIAL_WACOM4 is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_BMA150 is not set
CONFIG_INPUT_E3X0_BUTTON=y
CONFIG_INPUT_PCSPKR=y
# CONFIG_INPUT_MAX77693_HAPTIC is not set
CONFIG_INPUT_MAX8925_ONKEY=y
# CONFIG_INPUT_MMA8450 is not set
CONFIG_INPUT_APANEL=y
# CONFIG_INPUT_GPIO_BEEPER is not set
CONFIG_INPUT_GPIO_DECODER=y
CONFIG_INPUT_GPIO_VIBRA=y
CONFIG_INPUT_WISTRON_BTNS=y
# CONFIG_INPUT_ATLAS_BTNS is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
CONFIG_INPUT_KXTJ9=y
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=y
# CONFIG_INPUT_UINPUT is not set
CONFIG_INPUT_PCF50633_PMU=y
CONFIG_INPUT_PCF8574=y
CONFIG_INPUT_PWM_BEEPER=y
CONFIG_INPUT_PWM_VIBRA=y
CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_DA9063_ONKEY is not set
CONFIG_INPUT_ADXL34X=y
CONFIG_INPUT_ADXL34X_I2C=y
# CONFIG_INPUT_IBM_PANEL is not set
CONFIG_INPUT_IQS269A=y
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
# CONFIG_INPUT_CMA3000 is not set
CONFIG_INPUT_IDEAPAD_SLIDEBAR=y
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
CONFIG_INPUT_DRV260X_HAPTICS=y
CONFIG_INPUT_DRV2665_HAPTICS=y
CONFIG_INPUT_DRV2667_HAPTICS=y
# CONFIG_INPUT_RAVE_SP_PWRBUTTON is not set
CONFIG_RMI4_CORE=y
# CONFIG_RMI4_I2C is not set
# CONFIG_RMI4_SMB is not set
# CONFIG_RMI4_F03 is not set
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
# CONFIG_RMI4_F30 is not set
# CONFIG_RMI4_F34 is not set
# CONFIG_RMI4_F3A is not set
# CONFIG_RMI4_F54 is not set
# CONFIG_RMI4_F55 is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PARKBD is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=y
CONFIG_SERIO_ALTERA_PS2=y
CONFIG_SERIO_PS2MULT=y
CONFIG_SERIO_ARC_PS2=y
CONFIG_SERIO_GPIO_PS2=y
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=y
# CONFIG_GAMEPORT_NS558 is not set
CONFIG_GAMEPORT_L4=y
# CONFIG_GAMEPORT_EMU10K1 is not set
CONFIG_GAMEPORT_FM801=y
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LEGACY_TIOCSTI=y
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_PCILIB=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
# CONFIG_SERIAL_8250_MEN_MCB is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_DWLIB=y
# CONFIG_SERIAL_8250_DW is not set
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_LPSS=y
CONFIG_SERIAL_8250_MID=y
CONFIG_SERIAL_8250_PERICOM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_UARTLITE=y
# CONFIG_SERIAL_UARTLITE_CONSOLE is not set
CONFIG_SERIAL_UARTLITE_NR_UARTS=1
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_SERIAL_JSM=y
# CONFIG_SERIAL_LANTIQ is not set
CONFIG_SERIAL_SCCNXP=y
CONFIG_SERIAL_SCCNXP_CONSOLE=y
# CONFIG_SERIAL_SC16IS7XX is not set
CONFIG_SERIAL_TIMBERDALE=y
CONFIG_SERIAL_ALTERA_JTAGUART=y
# CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE is not set
CONFIG_SERIAL_ALTERA_UART=y
CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
# CONFIG_SERIAL_ALTERA_UART_CONSOLE is not set
CONFIG_SERIAL_PCH_UART=y
# CONFIG_SERIAL_PCH_UART_CONSOLE is not set
CONFIG_SERIAL_ARC=y
# CONFIG_SERIAL_ARC_CONSOLE is not set
CONFIG_SERIAL_ARC_NR_PORTS=1
CONFIG_SERIAL_RP2=y
CONFIG_SERIAL_RP2_NR_UARTS=32
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_FSL_LINFLEXUART=y
CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
# CONFIG_SERIAL_MEN_Z135 is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
CONFIG_N_GSM=y
CONFIG_NOZOMI=y
# CONFIG_NULL_TTY is not set
CONFIG_RPMSG_TTY=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_PRINTER=y
CONFIG_LP_CONSOLE=y
CONFIG_PPDEV=y
# CONFIG_VIRTIO_CONSOLE is not set
CONFIG_IPMI_HANDLER=y
CONFIG_IPMI_DMI_DECODE=y
CONFIG_IPMI_PLAT_DATA=y
# CONFIG_IPMI_PANIC_EVENT is not set
CONFIG_IPMI_DEVICE_INTERFACE=y
CONFIG_IPMI_SI=y
CONFIG_IPMI_SSIF=y
# CONFIG_IPMI_IPMB is not set
CONFIG_IPMI_WATCHDOG=y
CONFIG_IPMI_POWEROFF=y
# CONFIG_SSIF_IPMI_BMC is not set
CONFIG_IPMB_DEVICE_INTERFACE=y
# CONFIG_HW_RANDOM is not set
CONFIG_APPLICOM=y
CONFIG_SONYPI=y
# CONFIG_MWAVE is not set
# CONFIG_SCx200_GPIO is not set
CONFIG_PC8736x_GPIO=y
CONFIG_NSC_GPIO=y
# CONFIG_DEVMEM is not set
CONFIG_NVRAM=y
CONFIG_DEVPORT=y
# CONFIG_HPET is not set
# CONFIG_HANGCHECK_TIMER is not set
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS_CORE=y
CONFIG_TCG_TIS=y
# CONFIG_TCG_TIS_I2C is not set
# CONFIG_TCG_TIS_I2C_CR50 is not set
# CONFIG_TCG_TIS_I2C_ATMEL is not set
CONFIG_TCG_TIS_I2C_INFINEON=y
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
# CONFIG_TCG_NSC is not set
CONFIG_TCG_ATMEL=y
# CONFIG_TCG_INFINEON is not set
CONFIG_TCG_CRB=y
# CONFIG_TCG_VTPM_PROXY is not set
# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
CONFIG_TELCLOCK=y
CONFIG_XILLYBUS_CLASS=y
CONFIG_XILLYBUS=y
# CONFIG_XILLYBUS_PCIE is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
# CONFIG_I2C_CHARDEV is not set
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_LTC4306=y
CONFIG_I2C_MUX_PCA9541=y
# CONFIG_I2C_MUX_PCA954x is not set
# CONFIG_I2C_MUX_REG is not set
CONFIG_I2C_MUX_MLXCPLD=y
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCA=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=y
CONFIG_I2C_ALI1535=y
CONFIG_I2C_ALI1563=y
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
CONFIG_I2C_I801=y
CONFIG_I2C_ISCH=y
CONFIG_I2C_ISMT=y
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
CONFIG_I2C_SIS5595=y
CONFIG_I2C_SIS630=y
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
CONFIG_I2C_VIAPRO=y

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CBUS_GPIO=y
CONFIG_I2C_DESIGNWARE_CORE=y
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
CONFIG_I2C_DESIGNWARE_PLATFORM=y
# CONFIG_I2C_DESIGNWARE_BAYTRAIL is not set
CONFIG_I2C_DESIGNWARE_PCI=y
CONFIG_I2C_EG20T=y
CONFIG_I2C_EMEV2=y
CONFIG_I2C_GPIO=y
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
CONFIG_I2C_KEMPLD=y
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_PCA_PLATFORM=y
# CONFIG_I2C_SIMTEC is not set
CONFIG_I2C_XILINX=y

#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_PARPORT=y
# CONFIG_I2C_PCI1XXXX is not set
CONFIG_I2C_TAOS_EVM=y

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SCx200_ACB=y
CONFIG_I2C_VIRTIO=y
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=y
CONFIG_I2C_SLAVE_TESTUNIT=y
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

CONFIG_I3C=y
CONFIG_CDNS_I3C_MASTER=y
CONFIG_DW_I3C_MASTER=y
# CONFIG_SVC_I3C_MASTER is not set
# CONFIG_MIPI_I3C_HCI is not set
# CONFIG_SPI is not set
# CONFIG_SPMI is not set
CONFIG_HSI=y
CONFIG_HSI_BOARDINFO=y

#
# HSI controllers
#

#
# HSI clients
#
# CONFIG_HSI_CHAR is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
# CONFIG_NTP_PPS is not set

#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=y
CONFIG_PPS_CLIENT_LDISC=y
CONFIG_PPS_CLIENT_PARPORT=y
CONFIG_PPS_CLIENT_GPIO=y

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_PCH=y
CONFIG_PTP_1588_CLOCK_KVM=y
CONFIG_PTP_1588_CLOCK_IDT82P33=y
CONFIG_PTP_1588_CLOCK_IDTCM=y
# CONFIG_PTP_1588_CLOCK_VMW is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_CY8C95X0 is not set
# CONFIG_PINCTRL_DA9062 is not set
# CONFIG_PINCTRL_MCP23S08 is not set
CONFIG_PINCTRL_SX150X=y

#
# Intel pinctrl drivers
#
# CONFIG_PINCTRL_BAYTRAIL is not set
# CONFIG_PINCTRL_CHERRYVIEW is not set
# CONFIG_PINCTRL_LYNXPOINT is not set
# CONFIG_PINCTRL_ALDERLAKE is not set
# CONFIG_PINCTRL_BROXTON is not set
# CONFIG_PINCTRL_CANNONLAKE is not set
# CONFIG_PINCTRL_CEDARFORK is not set
# CONFIG_PINCTRL_DENVERTON is not set
# CONFIG_PINCTRL_ELKHARTLAKE is not set
# CONFIG_PINCTRL_EMMITSBURG is not set
# CONFIG_PINCTRL_GEMINILAKE is not set
# CONFIG_PINCTRL_ICELAKE is not set
# CONFIG_PINCTRL_JASPERLAKE is not set
# CONFIG_PINCTRL_LAKEFIELD is not set
# CONFIG_PINCTRL_LEWISBURG is not set
# CONFIG_PINCTRL_METEORLAKE is not set
# CONFIG_PINCTRL_SUNRISEPOINT is not set
# CONFIG_PINCTRL_TIGERLAKE is not set
# end of Intel pinctrl drivers

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_IDIO_16=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_AMDPT is not set
CONFIG_GPIO_DWAPB=y
# CONFIG_GPIO_EXAR is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_ICH is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_MENZ127=y
# CONFIG_GPIO_SIOX is not set
CONFIG_GPIO_VX855=y
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# Port-mapped I/O GPIO drivers
#
# CONFIG_GPIO_F7188X is not set
# CONFIG_GPIO_IT87 is not set
# CONFIG_GPIO_SCH is not set
# CONFIG_GPIO_SCH311X is not set
CONFIG_GPIO_WINBOND=y
# CONFIG_GPIO_WS16C48 is not set
# end of Port-mapped I/O GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_FXL6408 is not set
# CONFIG_GPIO_MAX7300 is not set
CONFIG_GPIO_MAX732X=y
# CONFIG_GPIO_MAX732X_IRQ is not set
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_PCA9570=y
# CONFIG_GPIO_PCF857X is not set
CONFIG_GPIO_TPIC2810=y
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# CONFIG_GPIO_ARIZONA is not set
CONFIG_GPIO_BD9571MWV=y
CONFIG_GPIO_CS5535=y
# CONFIG_GPIO_ELKHARTLAKE is not set
# CONFIG_GPIO_KEMPLD is not set
# CONFIG_GPIO_LP873X is not set
# CONFIG_GPIO_RC5T583 is not set
CONFIG_GPIO_TPS65086=y
# CONFIG_GPIO_TPS6586X is not set
CONFIG_GPIO_TQMX86=y
CONFIG_GPIO_WM8994=y
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_AMD8111 is not set
# CONFIG_GPIO_BT8XX is not set
CONFIG_GPIO_ML_IOH=y
# CONFIG_GPIO_PCH is not set
CONFIG_GPIO_PCI_IDIO_16=y
# CONFIG_GPIO_PCIE_IDIO_24 is not set
CONFIG_GPIO_RDC321X=y
# end of PCI GPIO expanders

#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=y
# CONFIG_GPIO_LATCH is not set
# CONFIG_GPIO_MOCKUP is not set
CONFIG_GPIO_VIRTIO=y
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers

# CONFIG_W1 is not set
# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_POWER_SUPPLY_HWMON is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_MAX8925_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
CONFIG_BATTERY_DS2782=y
# CONFIG_BATTERY_SAMSUNG_SDI is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
CONFIG_MANAGER_SBS=y
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_DA9030 is not set
# CONFIG_BATTERY_MAX17040 is not set
CONFIG_BATTERY_MAX17042=y
# CONFIG_CHARGER_PCF50633 is not set
CONFIG_CHARGER_MAX8903=y
CONFIG_CHARGER_LP8727=y
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
CONFIG_CHARGER_LT3651=y
CONFIG_CHARGER_LTC4162L=y
# CONFIG_CHARGER_MAX77693 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_MT6360 is not set
CONFIG_CHARGER_BQ2415X=y
# CONFIG_CHARGER_BQ24190 is not set
CONFIG_CHARGER_BQ24257=y
CONFIG_CHARGER_BQ24735=y
CONFIG_CHARGER_BQ2515X=y
CONFIG_CHARGER_BQ25890=y
# CONFIG_CHARGER_BQ25980 is not set
CONFIG_CHARGER_BQ256XX=y
CONFIG_CHARGER_SMB347=y
CONFIG_CHARGER_TPS65090=y
CONFIG_BATTERY_GAUGE_LTC2941=y
CONFIG_BATTERY_GOLDFISH=y
CONFIG_BATTERY_RT5033=y
CONFIG_CHARGER_RT9455=y
# CONFIG_CHARGER_RT9467 is not set
# CONFIG_CHARGER_RT9471 is not set
CONFIG_CHARGER_CROS_PCHG=y
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
CONFIG_SENSORS_ABITUGURU=y
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
CONFIG_SENSORS_ADM1025=y
CONFIG_SENSORS_ADM1026=y
CONFIG_SENSORS_ADM1029=y
CONFIG_SENSORS_ADM1031=y
CONFIG_SENSORS_ADM1177=y
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7410 is not set
CONFIG_SENSORS_ADT7411=y
CONFIG_SENSORS_ADT7462=y
# CONFIG_SENSORS_ADT7470 is not set
CONFIG_SENSORS_ADT7475=y
CONFIG_SENSORS_AHT10=y
CONFIG_SENSORS_AS370=y
CONFIG_SENSORS_ASC7621=y
CONFIG_SENSORS_AXI_FAN_CONTROL=y
CONFIG_SENSORS_K8TEMP=y
# CONFIG_SENSORS_K10TEMP is not set
CONFIG_SENSORS_FAM15H_POWER=y
CONFIG_SENSORS_APPLESMC=y
# CONFIG_SENSORS_ASB100 is not set
CONFIG_SENSORS_ATXP1=y
CONFIG_SENSORS_CORSAIR_CPRO=y
CONFIG_SENSORS_CORSAIR_PSU=y
CONFIG_SENSORS_DRIVETEMP=y
CONFIG_SENSORS_DS620=y
# CONFIG_SENSORS_DS1621 is not set
CONFIG_SENSORS_DELL_SMM=y
CONFIG_I8K=y
CONFIG_SENSORS_I5K_AMB=y
CONFIG_SENSORS_F71805F=y
# CONFIG_SENSORS_F71882FG is not set
CONFIG_SENSORS_F75375S=y
# CONFIG_SENSORS_FSCHMD is not set
CONFIG_SENSORS_FTSTEUTATES=y
# CONFIG_SENSORS_GL518SM is not set
CONFIG_SENSORS_GL520SM=y
CONFIG_SENSORS_G760A=y
CONFIG_SENSORS_G762=y
CONFIG_SENSORS_HIH6130=y
CONFIG_SENSORS_IBMAEM=y
# CONFIG_SENSORS_IBMPEX is not set
CONFIG_SENSORS_I5500=y
CONFIG_SENSORS_CORETEMP=y
CONFIG_SENSORS_IT87=y
CONFIG_SENSORS_JC42=y
CONFIG_SENSORS_POWR1220=y
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2947_I2C is not set
CONFIG_SENSORS_LTC2990=y
CONFIG_SENSORS_LTC2992=y
CONFIG_SENSORS_LTC4151=y
CONFIG_SENSORS_LTC4215=y
# CONFIG_SENSORS_LTC4222 is not set
CONFIG_SENSORS_LTC4245=y
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
CONFIG_SENSORS_MAX127=y
CONFIG_SENSORS_MAX16065=y
CONFIG_SENSORS_MAX1619=y
CONFIG_SENSORS_MAX1668=y
CONFIG_SENSORS_MAX197=y
CONFIG_SENSORS_MAX31730=y
# CONFIG_SENSORS_MAX31760 is not set
CONFIG_SENSORS_MAX6620=y
CONFIG_SENSORS_MAX6621=y
CONFIG_SENSORS_MAX6639=y
CONFIG_SENSORS_MAX6650=y
# CONFIG_SENSORS_MAX6697 is not set
CONFIG_SENSORS_MAX31790=y
# CONFIG_SENSORS_MC34VR500 is not set
CONFIG_SENSORS_MCP3021=y
CONFIG_SENSORS_TC654=y
CONFIG_SENSORS_TPS23861=y
CONFIG_SENSORS_MR75203=y
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
CONFIG_SENSORS_LM77=y
CONFIG_SENSORS_LM78=y
CONFIG_SENSORS_LM80=y
CONFIG_SENSORS_LM83=y
# CONFIG_SENSORS_LM85 is not set
CONFIG_SENSORS_LM87=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM92=y
CONFIG_SENSORS_LM93=y
# CONFIG_SENSORS_LM95234 is not set
CONFIG_SENSORS_LM95241=y
CONFIG_SENSORS_LM95245=y
# CONFIG_SENSORS_PC87360 is not set
CONFIG_SENSORS_PC87427=y
# CONFIG_SENSORS_NCT6683 is not set
CONFIG_SENSORS_NCT6775_CORE=y
CONFIG_SENSORS_NCT6775=y
# CONFIG_SENSORS_NCT6775_I2C is not set
CONFIG_SENSORS_NCT7802=y
CONFIG_SENSORS_NCT7904=y
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_OXP is not set
CONFIG_SENSORS_PCF8591=y
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=y
# CONFIG_SENSORS_ACBEL_FSG032 is not set
CONFIG_SENSORS_ADM1266=y
CONFIG_SENSORS_ADM1275=y
CONFIG_SENSORS_BEL_PFE=y
CONFIG_SENSORS_BPA_RS600=y
# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
CONFIG_SENSORS_FSP_3Y=y
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_DPS920AB is not set
CONFIG_SENSORS_INSPUR_IPSPS=y
CONFIG_SENSORS_IR35221=y
CONFIG_SENSORS_IR36021=y
CONFIG_SENSORS_IR38064=y
# CONFIG_SENSORS_IR38064_REGULATOR is not set
# CONFIG_SENSORS_IRPS5401 is not set
CONFIG_SENSORS_ISL68137=y
CONFIG_SENSORS_LM25066=y
# CONFIG_SENSORS_LM25066_REGULATOR is not set
# CONFIG_SENSORS_LT7182S is not set
CONFIG_SENSORS_LTC2978=y
# CONFIG_SENSORS_LTC2978_REGULATOR is not set
CONFIG_SENSORS_LTC3815=y
# CONFIG_SENSORS_MAX15301 is not set
CONFIG_SENSORS_MAX16064=y
CONFIG_SENSORS_MAX16601=y
# CONFIG_SENSORS_MAX20730 is not set
# CONFIG_SENSORS_MAX20751 is not set
CONFIG_SENSORS_MAX31785=y
CONFIG_SENSORS_MAX34440=y
CONFIG_SENSORS_MAX8688=y
CONFIG_SENSORS_MP2888=y
CONFIG_SENSORS_MP2975=y
# CONFIG_SENSORS_MP5023 is not set
# CONFIG_SENSORS_MPQ7932 is not set
CONFIG_SENSORS_PIM4328=y
# CONFIG_SENSORS_PLI1209BC is not set
CONFIG_SENSORS_PM6764TR=y
CONFIG_SENSORS_PXE1610=y
CONFIG_SENSORS_Q54SJ108A2=y
CONFIG_SENSORS_STPDDC60=y
# CONFIG_SENSORS_TDA38640 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_TPS546D24 is not set
CONFIG_SENSORS_UCD9000=y
CONFIG_SENSORS_UCD9200=y
# CONFIG_SENSORS_XDPE152 is not set
CONFIG_SENSORS_XDPE122=y
# CONFIG_SENSORS_XDPE122_REGULATOR is not set
# CONFIG_SENSORS_ZL6100 is not set
CONFIG_SENSORS_SBTSI=y
# CONFIG_SENSORS_SBRMI is not set
CONFIG_SENSORS_SHT15=y
CONFIG_SENSORS_SHT21=y
CONFIG_SENSORS_SHT3x=y
CONFIG_SENSORS_SHT4x=y
CONFIG_SENSORS_SHTC1=y
CONFIG_SENSORS_SIS5595=y
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
CONFIG_SENSORS_EMC6W201=y
# CONFIG_SENSORS_SMSC47M1 is not set
CONFIG_SENSORS_SMSC47M192=y
CONFIG_SENSORS_SMSC47B397=y
CONFIG_SENSORS_SCH56XX_COMMON=y
CONFIG_SENSORS_SCH5627=y
CONFIG_SENSORS_SCH5636=y
CONFIG_SENSORS_STTS751=y
CONFIG_SENSORS_SMM665=y
CONFIG_SENSORS_ADC128D818=y
# CONFIG_SENSORS_ADS7828 is not set
CONFIG_SENSORS_AMC6821=y
CONFIG_SENSORS_INA209=y
CONFIG_SENSORS_INA2XX=y
# CONFIG_SENSORS_INA238 is not set
CONFIG_SENSORS_INA3221=y
CONFIG_SENSORS_TC74=y
CONFIG_SENSORS_THMC50=y
CONFIG_SENSORS_TMP102=y
# CONFIG_SENSORS_TMP103 is not set
CONFIG_SENSORS_TMP108=y
CONFIG_SENSORS_TMP401=y
CONFIG_SENSORS_TMP421=y
# CONFIG_SENSORS_TMP464 is not set
CONFIG_SENSORS_TMP513=y
# CONFIG_SENSORS_VIA_CPUTEMP is not set
CONFIG_SENSORS_VIA686A=y
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
CONFIG_SENSORS_W83773G=y
# CONFIG_SENSORS_W83781D is not set
CONFIG_SENSORS_W83791D=y
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
CONFIG_SENSORS_W83L785TS=y
CONFIG_SENSORS_W83L786NG=y
CONFIG_SENSORS_W83627HF=y
# CONFIG_SENSORS_W83627EHF is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
# CONFIG_SENSORS_ATK0110 is not set
# CONFIG_SENSORS_ASUS_WMI is not set
# CONFIG_SENSORS_ASUS_EC is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
# CONFIG_DEVFREQ_THERMAL is not set
# CONFIG_THERMAL_EMULATION is not set

#
# Intel thermal drivers
#
# CONFIG_INTEL_POWERCLAMP is not set
CONFIG_X86_THERMAL_VECTOR=y
CONFIG_INTEL_TCC=y
CONFIG_X86_PKG_TEMP_THERMAL=m
# CONFIG_INTEL_SOC_DTS_THERMAL is not set

#
# ACPI INT340X thermal drivers
#
# end of ACPI INT340X thermal drivers

# CONFIG_INTEL_PCH_THERMAL is not set
# CONFIG_INTEL_TCC_COOLING is not set
# CONFIG_INTEL_HFI_THERMAL is not set
# end of Intel thermal drivers

CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
CONFIG_WATCHDOG_SYSFS=y
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=y
CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y
CONFIG_DA9062_WATCHDOG=y
# CONFIG_MENZ069_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_RAVE_SP_WATCHDOG is not set
CONFIG_CADENCE_WATCHDOG=y
# CONFIG_DW_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_ACQUIRE_WDT=y
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ADVANTECH_EC_WDT is not set
CONFIG_ALIM1535_WDT=y
CONFIG_ALIM7101_WDT=y
CONFIG_EBC_C384_WDT=y
# CONFIG_EXAR_WDT is not set
# CONFIG_F71808E_WDT is not set
# CONFIG_SP5100_TCO is not set
CONFIG_SBC_FITPC2_WATCHDOG=y
# CONFIG_EUROTECH_WDT is not set
CONFIG_IB700_WDT=y
# CONFIG_IBMASR is not set
CONFIG_WAFER_WDT=y
# CONFIG_I6300ESB_WDT is not set
# CONFIG_IE6XX_WDT is not set
# CONFIG_ITCO_WDT is not set
# CONFIG_IT8712F_WDT is not set
# CONFIG_IT87_WDT is not set
CONFIG_HP_WATCHDOG=y
# CONFIG_HPWDT_NMI_DECODING is not set
# CONFIG_KEMPLD_WDT is not set
CONFIG_SC1200_WDT=y
CONFIG_SCx200_WDT=y
CONFIG_PC87413_WDT=y
# CONFIG_NV_TCO is not set
CONFIG_60XX_WDT=y
CONFIG_SBC8360_WDT=y
# CONFIG_SBC7240_WDT is not set
# CONFIG_CPU5_WDT is not set
CONFIG_SMSC_SCH311X_WDT=y
# CONFIG_SMSC37B787_WDT is not set
CONFIG_TQMX86_WDT=y
# CONFIG_VIA_WDT is not set
# CONFIG_W83627HF_WDT is not set
# CONFIG_W83877F_WDT is not set
CONFIG_W83977F_WDT=y
CONFIG_MACHZ_WDT=y
CONFIG_SBC_EPX_C3_WATCHDOG=y
CONFIG_INTEL_MEI_WDT=y
# CONFIG_NI903X_WDT is not set
# CONFIG_NIC7018_WDT is not set
CONFIG_MEN_A21_WDT=y

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=y
CONFIG_SSB_SPROM=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_SSB_DRIVER_GPIO=y
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_CS5535=y
CONFIG_MFD_AS3711=y
# CONFIG_MFD_SMPRO is not set
# CONFIG_PMIC_ADP5520 is not set
CONFIG_MFD_AAT2870_CORE=y
# CONFIG_MFD_BCM590XX is not set
CONFIG_MFD_BD9571MWV=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_CROS_EC_DEV=y
# CONFIG_MFD_MADERA is not set
CONFIG_PMIC_DA903X=y
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
CONFIG_MFD_DA9062=y
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
CONFIG_MFD_INTEL_QUARK_I2C_GPIO=y
CONFIG_LPC_ICH=y
CONFIG_LPC_SCH=y
# CONFIG_INTEL_SOC_PMIC is not set
# CONFIG_INTEL_SOC_PMIC_CHTWC is not set
# CONFIG_INTEL_SOC_PMIC_CHTDC_TI is not set
CONFIG_MFD_INTEL_LPSS=y
# CONFIG_MFD_INTEL_LPSS_ACPI is not set
CONFIG_MFD_INTEL_LPSS_PCI=y
# CONFIG_MFD_INTEL_PMC_BXT is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
CONFIG_MFD_KEMPLD=y
# CONFIG_MFD_88PM800 is not set
CONFIG_MFD_88PM805=y
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
CONFIG_MFD_MAX77693=y
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
CONFIG_MFD_MAX8925=y
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
CONFIG_MFD_MT6360=y
# CONFIG_MFD_MT6370 is not set
CONFIG_MFD_MT6397=y
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_RETU is not set
CONFIG_MFD_PCF50633=y
CONFIG_PCF50633_ADC=y
CONFIG_PCF50633_GPIO=y
# CONFIG_MFD_SY7636A is not set
CONFIG_MFD_RDC321X=y
CONFIG_MFD_RT4831=y
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
CONFIG_MFD_RC5T583=y
CONFIG_MFD_SI476X_CORE=y
CONFIG_MFD_SM501=y
# CONFIG_MFD_SM501_GPIO is not set
CONFIG_MFD_SKY81452=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
CONFIG_MFD_LP8788=y
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
CONFIG_TPS6507X=y
CONFIG_MFD_TPS65086=y
CONFIG_MFD_TPS65090=y
CONFIG_MFD_TI_LP873X=y
CONFIG_MFD_TPS6586X=y
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TIMBERDALE is not set
CONFIG_MFD_TQMX86=y
CONFIG_MFD_VX855=y
CONFIG_MFD_ARIZONA=y
CONFIG_MFD_ARIZONA_I2C=y
CONFIG_MFD_CS47L24=y
# CONFIG_MFD_WM5102 is not set
# CONFIG_MFD_WM5110 is not set
# CONFIG_MFD_WM8997 is not set
# CONFIG_MFD_WM8998 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM8350_I2C is not set
CONFIG_MFD_WM8994=y
# CONFIG_MFD_WCD934X is not set
# CONFIG_MFD_ATC260X_I2C is not set
CONFIG_RAVE_SP_CORE=y
# end of Multifunction device drivers

CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
CONFIG_REGULATOR_USERSPACE_CONSUMER=y
CONFIG_REGULATOR_88PG86X=y
CONFIG_REGULATOR_ACT8865=y
CONFIG_REGULATOR_AD5398=y
CONFIG_REGULATOR_AAT2870=y
CONFIG_REGULATOR_AS3711=y
# CONFIG_REGULATOR_AXP20X is not set
# CONFIG_REGULATOR_BD9571MWV is not set
CONFIG_REGULATOR_DA9062=y
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_DA9211=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
CONFIG_REGULATOR_LP3971=y
CONFIG_REGULATOR_LP3972=y
CONFIG_REGULATOR_LP872X=y
CONFIG_REGULATOR_LP8755=y
CONFIG_REGULATOR_LP8788=y
# CONFIG_REGULATOR_LTC3589 is not set
CONFIG_REGULATOR_LTC3676=y
CONFIG_REGULATOR_MAX1586=y
CONFIG_REGULATOR_MAX8649=y
CONFIG_REGULATOR_MAX8660=y
# CONFIG_REGULATOR_MAX8893 is not set
CONFIG_REGULATOR_MAX8925=y
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX20411 is not set
CONFIG_REGULATOR_MAX77693=y
# CONFIG_REGULATOR_MAX77826 is not set
CONFIG_REGULATOR_MP8859=y
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6323 is not set
# CONFIG_REGULATOR_MT6331 is not set
# CONFIG_REGULATOR_MT6332 is not set
# CONFIG_REGULATOR_MT6357 is not set
# CONFIG_REGULATOR_MT6358 is not set
CONFIG_REGULATOR_MT6359=y
CONFIG_REGULATOR_MT6360=y
# CONFIG_REGULATOR_MT6397 is not set
# CONFIG_REGULATOR_PCA9450 is not set
CONFIG_REGULATOR_PCF50633=y
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
CONFIG_REGULATOR_PV88090=y
# CONFIG_REGULATOR_PWM is not set
CONFIG_REGULATOR_RC5T583=y
CONFIG_REGULATOR_RT4801=y
# CONFIG_REGULATOR_RT4803 is not set
CONFIG_REGULATOR_RT4831=y
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5739 is not set
# CONFIG_REGULATOR_RT5759 is not set
CONFIG_REGULATOR_RT6160=y
# CONFIG_REGULATOR_RT6190 is not set
CONFIG_REGULATOR_RT6245=y
CONFIG_REGULATOR_RTQ2134=y
CONFIG_REGULATOR_RTMV20=y
CONFIG_REGULATOR_RTQ6752=y
# CONFIG_REGULATOR_SKY81452 is not set
CONFIG_REGULATOR_SLG51000=y
CONFIG_REGULATOR_TPS51632=y
# CONFIG_REGULATOR_TPS62360 is not set
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_REGULATOR_TPS65086=y
CONFIG_REGULATOR_TPS65090=y
CONFIG_REGULATOR_TPS65132=y
CONFIG_REGULATOR_TPS6586X=y
CONFIG_REGULATOR_WM8994=y
# CONFIG_RC_CORE is not set
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
# CONFIG_MEDIA_CEC_SUPPORT is not set
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
# CONFIG_MEDIA_CAMERA_SUPPORT is not set
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
# CONFIG_VIDEO_ADV_DEBUG is not set
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
# CONFIG_V4L2_FLASH_LED_CLASS is not set
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
# end of Media controller options

#
# Digital TV options
#
CONFIG_DVB_MMAP=y
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=16
# CONFIG_DVB_DYNAMIC_MINORS is not set
CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y
CONFIG_DVB_ULE_DEBUG=y
# end of Digital TV options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#

#
# Media drivers
#
# CONFIG_MEDIA_PCI_SUPPORT is not set
# CONFIG_RADIO_ADAPTERS is not set
CONFIG_MEDIA_PLATFORM_DRIVERS=y
# CONFIG_V4L_PLATFORM_DRIVERS is not set
# CONFIG_SDR_PLATFORM_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#

#
# Mediatek media platform drivers
#

#
# Microchip Technology, Inc. media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#

#
# MMC/SDIO DVB adapters
#
# CONFIG_SMS_SDIO_DRV is not set

#
# FireWire (IEEE 1394) Adapters
#
CONFIG_DVB_FIREDTV=y
CONFIG_DVB_FIREDTV_INPUT=y
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_VMALLOC=y
# end of Media drivers

CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y

#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y

#
# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers'
#

#
# Video and audio decoders
#
CONFIG_MEDIA_TUNER=y

#
# Tuner drivers auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_MEDIA_TUNER_MC44S803=y
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
CONFIG_MEDIA_TUNER_XC2028=y
CONFIG_MEDIA_TUNER_XC4000=y
CONFIG_MEDIA_TUNER_XC5000=y

#
# DVB Frontend drivers auto-selected by 'Autoselect ancillary drivers'
#

#
# Multistandard (satellite) frontends
#

#
# Multistandard (cable + terrestrial) frontends
#

#
# DVB-S (satellite) frontends
#

#
# DVB-T (terrestrial) frontends
#

#
# DVB-C (cable) frontends
#

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#

#
# ISDB-T (terrestrial) frontends
#

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#

#
# Digital terrestrial only tuners/PLL
#

#
# SEC control devices for DVB-S
#

#
# Common Interface (EN50221) controller drivers
#
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_VIDEO_CMDLINE=y
CONFIG_VIDEO_NOMODESET=y
# CONFIG_AGP is not set
CONFIG_INTEL_GTT=y
# CONFIG_VGA_SWITCHEROO is not set
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_DEBUG_MM=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_FBDEV_EMULATION is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDCP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DP_AUX_CHARDEV=y
CONFIG_DRM_DP_CEC=y
CONFIG_DRM_TTM=y
CONFIG_DRM_BUDDY=y
CONFIG_DRM_VRAM_HELPER=y
CONFIG_DRM_TTM_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y

#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=y
# CONFIG_DRM_I2C_SIL164 is not set
CONFIG_DRM_I2C_NXP_TDA998X=y
CONFIG_DRM_I2C_NXP_TDA9950=y
# end of I2C encoder or helper chips

#
# ARM devices
#
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_I915=y
CONFIG_DRM_I915_FORCE_PROBE=""
# CONFIG_DRM_I915_CAPTURE_ERROR is not set
CONFIG_DRM_I915_USERPTR=y
# CONFIG_DRM_I915_PXP is not set
CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
CONFIG_DRM_I915_FENCE_TIMEOUT=10000
CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500
CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
CONFIG_DRM_I915_STOP_TIMEOUT=100
CONFIG_DRM_I915_TIMESLICE_DURATION=1
CONFIG_DRM_VGEM=y
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_VMWGFX=y
# CONFIG_DRM_VMWGFX_MKSSTATS is not set
CONFIG_DRM_GMA500=y
CONFIG_DRM_AST=y
# CONFIG_DRM_MGAG200 is not set
CONFIG_DRM_QXL=y
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_DRM_VIRTIO_GPU_KMS=y
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
CONFIG_DRM_BOCHS=y
# CONFIG_DRM_CIRRUS_QEMU is not set
CONFIG_DRM_SIMPLEDRM=y
CONFIG_DRM_VBOXVIDEO=y
# CONFIG_DRM_SSD130X is not set
CONFIG_DRM_LEGACY=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_DDC=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
CONFIG_FB_FOREIGN_ENDIAN=y
CONFIG_FB_BOTH_ENDIAN=y
# CONFIG_FB_BIG_ENDIAN is not set
# CONFIG_FB_LITTLE_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_HECUBA=y
CONFIG_FB_SVGALIB=y
CONFIG_FB_BACKLIGHT=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y

#
# Frame buffer hardware drivers
#
CONFIG_FB_CIRRUS=y
CONFIG_FB_PM2=y
# CONFIG_FB_PM2_FIFO_DISCONNECT is not set
CONFIG_FB_CYBER2000=y
# CONFIG_FB_CYBER2000_DDC is not set
# CONFIG_FB_ARC is not set
# CONFIG_FB_ASILIANT is not set
CONFIG_FB_IMSTT=y
# CONFIG_FB_VGA16 is not set
CONFIG_FB_UVESA=y
CONFIG_FB_VESA=y
CONFIG_FB_N411=y
CONFIG_FB_HGA=y
# CONFIG_FB_OPENCORES is not set
CONFIG_FB_S1D13XXX=y
CONFIG_FB_NVIDIA=y
CONFIG_FB_NVIDIA_I2C=y
# CONFIG_FB_NVIDIA_DEBUG is not set
CONFIG_FB_NVIDIA_BACKLIGHT=y
CONFIG_FB_RIVA=y
CONFIG_FB_RIVA_I2C=y
# CONFIG_FB_RIVA_DEBUG is not set
CONFIG_FB_RIVA_BACKLIGHT=y
CONFIG_FB_I740=y
# CONFIG_FB_LE80578 is not set
CONFIG_FB_MATROX=y
CONFIG_FB_MATROX_MILLENIUM=y
CONFIG_FB_MATROX_MYSTIQUE=y
# CONFIG_FB_MATROX_G is not set
CONFIG_FB_MATROX_I2C=y
# CONFIG_FB_RADEON is not set
CONFIG_FB_ATY128=y
CONFIG_FB_ATY128_BACKLIGHT=y
CONFIG_FB_ATY=y
# CONFIG_FB_ATY_CT is not set
CONFIG_FB_ATY_GX=y
CONFIG_FB_ATY_BACKLIGHT=y
CONFIG_FB_S3=y
# CONFIG_FB_S3_DDC is not set
CONFIG_FB_SAVAGE=y
CONFIG_FB_SAVAGE_I2C=y
CONFIG_FB_SAVAGE_ACCEL=y
CONFIG_FB_SIS=y
CONFIG_FB_SIS_300=y
# CONFIG_FB_SIS_315 is not set
CONFIG_FB_VIA=y
CONFIG_FB_VIA_DIRECT_PROCFS=y
CONFIG_FB_VIA_X_COMPATIBILITY=y
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
CONFIG_FB_3DFX=y
# CONFIG_FB_3DFX_ACCEL is not set
# CONFIG_FB_3DFX_I2C is not set
# CONFIG_FB_VOODOO1 is not set
CONFIG_FB_VT8623=y
CONFIG_FB_TRIDENT=y
# CONFIG_FB_ARK is not set
CONFIG_FB_PM3=y
CONFIG_FB_CARMINE=y
# CONFIG_FB_CARMINE_DRAM_EVAL is not set
CONFIG_CARMINE_DRAM_CUSTOM=y
CONFIG_FB_GEODE=y
CONFIG_FB_GEODE_LX=y
CONFIG_FB_GEODE_GX=y
# CONFIG_FB_GEODE_GX1 is not set
CONFIG_FB_SM501=y
CONFIG_FB_IBM_GXT4500=y
# CONFIG_FB_VIRTUAL is not set
CONFIG_FB_METRONOME=y
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SSD1307=y
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_KTD253=y
# CONFIG_BACKLIGHT_KTZ8866 is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_DA903X is not set
# CONFIG_BACKLIGHT_MAX8925 is not set
# CONFIG_BACKLIGHT_APPLE is not set
CONFIG_BACKLIGHT_QCOM_WLED=y
CONFIG_BACKLIGHT_RT4831=y
CONFIG_BACKLIGHT_SAHARA=y
CONFIG_BACKLIGHT_ADP8860=y
CONFIG_BACKLIGHT_ADP8870=y
# CONFIG_BACKLIGHT_PCF50633 is not set
# CONFIG_BACKLIGHT_AAT2870 is not set
CONFIG_BACKLIGHT_LM3630A=y
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
CONFIG_BACKLIGHT_LP8788=y
# CONFIG_BACKLIGHT_SKY81452 is not set
CONFIG_BACKLIGHT_AS3711=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LV5207LP=y
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_RAVE_SP is not set
# end of Backlight & LCD device support

CONFIG_VGASTATE=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
# end of Console display driver support

CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
CONFIG_LOGO_LINUX_VGA16=y
# CONFIG_LOGO_LINUX_CLUT224 is not set
# end of Graphics support

# CONFIG_DRM_ACCEL is not set
CONFIG_SOUND=y
# CONFIG_SND is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
CONFIG_HIDRAW=y
CONFIG_UHID=y
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
# CONFIG_HID_ACRUX is not set
CONFIG_HID_APPLE=y
CONFIG_HID_AUREAL=y
CONFIG_HID_BELKIN=y
# CONFIG_HID_CHERRY is not set
CONFIG_HID_COUGAR=y
CONFIG_HID_MACALLY=y
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CYPRESS is not set
CONFIG_HID_DRAGONRISE=y
# CONFIG_DRAGONRISE_FF is not set
CONFIG_HID_EMS_FF=y
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_EVISION is not set
CONFIG_HID_EZKEY=y
CONFIG_HID_GEMBIRD=y
# CONFIG_HID_GFRM is not set
CONFIG_HID_GLORIOUS=y
CONFIG_HID_VIVALDI_COMMON=y
CONFIG_HID_VIVALDI=y
# CONFIG_HID_KEYTOUCH is not set
CONFIG_HID_KYE=y
CONFIG_HID_WALTOP=y
# CONFIG_HID_VIEWSONIC is not set
# CONFIG_HID_VRC2 is not set
# CONFIG_HID_XIAOMI is not set
# CONFIG_HID_GYRATION is not set
CONFIG_HID_ICADE=y
CONFIG_HID_ITE=y
# CONFIG_HID_JABRA is not set
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LED=y
CONFIG_HID_LENOVO=y
CONFIG_HID_MAGICMOUSE=y
# CONFIG_HID_MALTRON is not set
CONFIG_HID_MAYFLASH=y
CONFIG_HID_REDRAGON=y
CONFIG_HID_MICROSOFT=y
# CONFIG_HID_MONTEREY is not set
CONFIG_HID_MULTITOUCH=y
# CONFIG_HID_NINTENDO is not set
CONFIG_HID_NTI=y
CONFIG_HID_ORTEK=y
# CONFIG_HID_PANTHERLORD is not set
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
# CONFIG_HID_PLANTRONICS is not set
CONFIG_HID_PLAYSTATION=y
CONFIG_PLAYSTATION_FF=y
# CONFIG_HID_PXRC is not set
# CONFIG_HID_RAZER is not set
CONFIG_HID_PRIMAX=y
CONFIG_HID_SAITEK=y
CONFIG_HID_SEMITEK=y
CONFIG_HID_SPEEDLINK=y
# CONFIG_HID_STEAM is not set
CONFIG_HID_STEELSERIES=y
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_RMI is not set
CONFIG_HID_GREENASIA=y
# CONFIG_GREENASIA_FF is not set
CONFIG_HID_SMARTJOYPLUS=y
# CONFIG_SMARTJOYPLUS_FF is not set
CONFIG_HID_TIVO=y
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_TOPRE is not set
# CONFIG_HID_THINGM is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_WIIMOTE is not set
CONFIG_HID_XINMO=y
CONFIG_HID_ZEROPLUS=y
# CONFIG_ZEROPLUS_FF is not set
CONFIG_HID_ZYDACRON=y
CONFIG_HID_SENSOR_HUB=y
CONFIG_HID_SENSOR_CUSTOM_SENSOR=y
CONFIG_HID_ALPS=y
# end of Special HID drivers

#
# HID-BPF support
#
# end of HID-BPF support

CONFIG_I2C_HID=y
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_HID_OF is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_USB_CONN_GPIO is not set
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB is not set
CONFIG_USB_PCI=y

#
# USB dual-mode controller drivers
#

#
# USB port drivers
#

#
# USB Physical Layer drivers
#
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_USB_GPIO_VBUS is not set
# end of USB Physical Layer drivers

# CONFIG_USB_GADGET is not set
# CONFIG_TYPEC is not set
# CONFIG_USB_ROLE_SWITCH is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_SDIO_UART=y
# CONFIG_MMC_TEST is not set
CONFIG_MMC_CRYPTO=y

#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_DEBUG=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=y
CONFIG_MMC_RICOH_MMC=y
# CONFIG_MMC_SDHCI_ACPI is not set
CONFIG_MMC_SDHCI_PLTFM=y
# CONFIG_MMC_SDHCI_F_SDH30 is not set
CONFIG_MMC_WBSD=y
CONFIG_MMC_ALCOR=y
CONFIG_MMC_TIFM_SD=y
CONFIG_MMC_CB710=y
CONFIG_MMC_VIA_SDMMC=y
CONFIG_MMC_USDHI6ROL0=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=y
# CONFIG_SCSI_UFSHCD is not set
CONFIG_MEMSTICK=y
# CONFIG_MEMSTICK_DEBUG is not set

#
# MemoryStick drivers
#
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
CONFIG_MSPRO_BLOCK=y
CONFIG_MS_BLOCK=y

#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_TIFM_MS=y
CONFIG_MEMSTICK_JMICRON_38X=y
CONFIG_MEMSTICK_R592=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_APU is not set
CONFIG_LEDS_LM3530=y
CONFIG_LEDS_LM3532=y
CONFIG_LEDS_LM3642=y
CONFIG_LEDS_MT6323=y
CONFIG_LEDS_PCA9532=y
# CONFIG_LEDS_PCA9532_GPIO is not set
# CONFIG_LEDS_GPIO is not set
CONFIG_LEDS_LP3944=y
# CONFIG_LEDS_LP3952 is not set
CONFIG_LEDS_LP50XX=y
# CONFIG_LEDS_LP8788 is not set
CONFIG_LEDS_PCA955X=y
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=y
# CONFIG_LEDS_DA903X is not set
# CONFIG_LEDS_PWM is not set
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2606MVV is not set
CONFIG_LEDS_BD2802=y
CONFIG_LEDS_INTEL_SS4200=y
CONFIG_LEDS_LT3593=y
CONFIG_LEDS_TCA6507=y
# CONFIG_LEDS_TLC591XX is not set
CONFIG_LEDS_LM355x=y
CONFIG_LEDS_OT200=y
# CONFIG_LEDS_IS31FL319X is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
CONFIG_LEDS_MLXCPLD=y
CONFIG_LEDS_MLXREG=y
CONFIG_LEDS_USER=y
# CONFIG_LEDS_NIC78BX is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AS3645A=y
CONFIG_LEDS_LM3601X=y
CONFIG_LEDS_RT8515=y
CONFIG_LEDS_SGM3140=y

#
# RGB LED drivers
#
# CONFIG_LEDS_PWM_MULTICOLOR is not set

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
CONFIG_LEDS_TRIGGER_DISK=y
# CONFIG_LEDS_TRIGGER_MTD is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
# CONFIG_LEDS_TRIGGER_CPU is not set
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
# CONFIG_LEDS_TRIGGER_CAMERA is not set
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
# CONFIG_LEDS_TRIGGER_PATTERN is not set
CONFIG_LEDS_TRIGGER_AUDIO=y
CONFIG_LEDS_TRIGGER_TTY=y

#
# Simple LED drivers
#
CONFIG_ACCESSIBILITY=y
CONFIG_A11Y_BRAILLE_CONSOLE=y

#
# Speakup console speech
#
CONFIG_SPEAKUP=y
CONFIG_SPEAKUP_SYNTH_ACNTSA=y
# CONFIG_SPEAKUP_SYNTH_APOLLO is not set
# CONFIG_SPEAKUP_SYNTH_AUDPTR is not set
CONFIG_SPEAKUP_SYNTH_BNS=y
# CONFIG_SPEAKUP_SYNTH_DECTLK is not set
# CONFIG_SPEAKUP_SYNTH_DECEXT is not set
CONFIG_SPEAKUP_SYNTH_LTLK=y
# CONFIG_SPEAKUP_SYNTH_SOFT is not set
CONFIG_SPEAKUP_SYNTH_SPKOUT=y
# CONFIG_SPEAKUP_SYNTH_TXPRT is not set
# CONFIG_SPEAKUP_SYNTH_DUMMY is not set
# end of Speakup console speech

# CONFIG_INFINIBAND is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_RTC_LIB=y
CONFIG_RTC_MC146818_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
CONFIG_DMABUF_DEBUG=y
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=y
CONFIG_LINEDISP=y
CONFIG_HD44780_COMMON=y
CONFIG_HD44780=y
CONFIG_KS0108=y
CONFIG_KS0108_PORT=0x378
CONFIG_KS0108_DELAY=2
CONFIG_CFAG12864B=y
CONFIG_CFAG12864B_RATE=20
CONFIG_IMG_ASCII_LCD=y
CONFIG_HT16K33=y
CONFIG_LCD2S=y
CONFIG_PARPORT_PANEL=y
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_PANEL=y
CONFIG_UIO=y
CONFIG_UIO_CIF=y
# CONFIG_UIO_PDRV_GENIRQ is not set
CONFIG_UIO_DMEM_GENIRQ=y
CONFIG_UIO_AEC=y
CONFIG_UIO_SERCOS3=y
# CONFIG_UIO_PCI_GENERIC is not set
# CONFIG_UIO_NETX is not set
CONFIG_UIO_PRUSS=y
CONFIG_UIO_MF624=y
# CONFIG_VFIO is not set
CONFIG_IRQ_BYPASS_MANAGER=y
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=y
CONFIG_VIRTIO_PCI_LIB_LEGACY=y
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_VDPA=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
CONFIG_VDPA=y
# CONFIG_VDPA_SIM is not set
# CONFIG_VDPA_USER is not set
CONFIG_IFCVF=y
# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set
CONFIG_VP_VDPA=y
CONFIG_ALIBABA_ENI_VDPA=y
CONFIG_VHOST_IOTLB=y
CONFIG_VHOST_TASK=y
CONFIG_VHOST=y
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=y
CONFIG_VHOST_VSOCK=y
CONFIG_VHOST_VDPA=y
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
# CONFIG_STAGING is not set
CONFIG_CHROME_PLATFORMS=y
# CONFIG_CHROMEOS_ACPI is not set
CONFIG_CHROMEOS_LAPTOP=y
CONFIG_CHROMEOS_PSTORE=y
# CONFIG_CHROMEOS_TBMC is not set
CONFIG_CROS_EC=y
# CONFIG_CROS_EC_I2C is not set
# CONFIG_CROS_EC_UART is not set
# CONFIG_CROS_EC_LPC is not set
CONFIG_CROS_EC_PROTO=y
# CONFIG_CROS_KBD_LED_BACKLIGHT is not set
CONFIG_CROS_EC_CHARDEV=y
CONFIG_CROS_EC_LIGHTBAR=y
CONFIG_CROS_EC_DEBUGFS=y
# CONFIG_CROS_EC_SENSORHUB is not set
CONFIG_CROS_EC_SYSFS=y
# CONFIG_CROS_HPS_I2C is not set
# CONFIG_CROS_USBPD_NOTIFY is not set
# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
# CONFIG_SURFACE_3_POWER_OPREGION is not set
# CONFIG_SURFACE_GPE is not set
# CONFIG_SURFACE_HOTPLUG is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_SURFACE_AGGREGATOR is not set
CONFIG_X86_PLATFORM_DEVICES=y
CONFIG_ACPI_WMI=y
CONFIG_WMI_BMOF=y
# CONFIG_HUAWEI_WMI is not set
# CONFIG_MXM_WMI is not set
# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
# CONFIG_XIAOMI_WMI is not set
# CONFIG_GIGABYTE_WMI is not set
# CONFIG_YOGABOOK_WMI is not set
# CONFIG_ACERHDF is not set
# CONFIG_ACER_WIRELESS is not set
# CONFIG_ACER_WMI is not set
# CONFIG_AMD_PMF is not set
# CONFIG_ADV_SWBUTTON is not set
# CONFIG_APPLE_GMUX is not set
# CONFIG_ASUS_LAPTOP is not set
# CONFIG_ASUS_WIRELESS is not set
# CONFIG_ASUS_TF103C_DOCK is not set
# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set
CONFIG_AMILO_RFKILL=y
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_FUJITSU_TABLET is not set
# CONFIG_GPD_POCKET_FAN is not set
# CONFIG_X86_PLATFORM_DRIVERS_HP is not set
# CONFIG_WIRELESS_HOTKEY is not set
# CONFIG_IBM_RTL is not set
# CONFIG_IDEAPAD_LAPTOP is not set
# CONFIG_LENOVO_YMC is not set
CONFIG_SENSORS_HDAPS=y
# CONFIG_THINKPAD_ACPI is not set
# CONFIG_THINKPAD_LMI is not set
CONFIG_INTEL_ATOMISP2_PDX86=y
CONFIG_INTEL_ATOMISP2_PM=y
# CONFIG_INTEL_SAR_INT1092 is not set
# CONFIG_INTEL_SKL_INT3472 is not set
# CONFIG_INTEL_PMC_CORE is not set
# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
# CONFIG_INTEL_WMI_THUNDERBOLT is not set
# CONFIG_INTEL_HID_EVENT is not set
# CONFIG_INTEL_VBTN is not set
# CONFIG_INTEL_INT0002_VGPIO is not set
# CONFIG_INTEL_OAKTRAIL is not set
# CONFIG_INTEL_PUNIT_IPC is not set
# CONFIG_INTEL_RST is not set
# CONFIG_INTEL_SMARTCONNECT is not set
# CONFIG_INTEL_VSEC is not set
# CONFIG_MSI_EC is not set
# CONFIG_MSI_LAPTOP is not set
# CONFIG_MSI_WMI is not set
# CONFIG_PCENGINES_APU2 is not set
CONFIG_BARCO_P50_GPIO=y
CONFIG_SAMSUNG_LAPTOP=y
# CONFIG_SAMSUNG_Q10 is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_HAPS is not set
# CONFIG_TOSHIBA_WMI is not set
# CONFIG_ACPI_CMPC is not set
# CONFIG_COMPAL_LAPTOP is not set
# CONFIG_LG_LAPTOP is not set
# CONFIG_PANASONIC_LAPTOP is not set
# CONFIG_SONY_LAPTOP is not set
# CONFIG_SYSTEM76_ACPI is not set
# CONFIG_TOPSTAR_LAPTOP is not set
# CONFIG_MLX_PLATFORM is not set
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_SCU_PCI is not set
# CONFIG_INTEL_SCU_PLATFORM is not set
# CONFIG_SIEMENS_SIMATIC_IPC is not set
# CONFIG_WINMATE_FM07_KEYS is not set
CONFIG_P2SB=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_MAX9485 is not set
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
CONFIG_COMMON_CLK_SI544=y
CONFIG_COMMON_CLK_CDCE706=y
CONFIG_COMMON_CLK_CS2000_CP=y
CONFIG_COMMON_CLK_PWM=y
CONFIG_XILINX_VCU=y
CONFIG_HWSPINLOCK=y

#
# Clock Source drivers
#
CONFIG_CLKSRC_I8253=y
CONFIG_CLKEVT_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_CLKBLD_I8253=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
# CONFIG_PCC is not set
CONFIG_ALTERA_MBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
CONFIG_IOMMU_DMA=y
# CONFIG_INTEL_IOMMU is not set
# CONFIG_IOMMUFD is not set
CONFIG_VIRTIO_IOMMU=y

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
# CONFIG_RPMSG_CTRL is not set
CONFIG_RPMSG_NS=y
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=y
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# end of Enable LiteX SoC Builder specific drivers

# CONFIG_WPCM450_SOC is not set

#
# Qualcomm SoC drivers
#
# end of Qualcomm SoC drivers

# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
# CONFIG_EXTCON_AXP288 is not set
CONFIG_EXTCON_FSA9480=y
CONFIG_EXTCON_GPIO=y
# CONFIG_EXTCON_INTEL_INT3496 is not set
CONFIG_EXTCON_MAX3355=y
# CONFIG_EXTCON_MAX77693 is not set
CONFIG_EXTCON_PTN5150=y
CONFIG_EXTCON_RT8973A=y
CONFIG_EXTCON_SM5502=y
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
CONFIG_MEMORY=y
# CONFIG_IIO is not set
CONFIG_NTB=y
# CONFIG_NTB_MSI is not set
CONFIG_NTB_IDT=y
# CONFIG_NTB_EPF is not set
CONFIG_NTB_SWITCHTEC=y
CONFIG_NTB_PINGPONG=y
# CONFIG_NTB_TOOL is not set
CONFIG_NTB_PERF=y
CONFIG_NTB_TRANSPORT=y
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_CLK is not set
CONFIG_PWM_CROS_EC=y
CONFIG_PWM_DWC=y
CONFIG_PWM_LPSS=y
CONFIG_PWM_LPSS_PCI=y
CONFIG_PWM_LPSS_PLATFORM=y
# CONFIG_PWM_PCA9685 is not set

#
# IRQ chip support
#
# end of IRQ chip support

CONFIG_IPACK_BUS=y
CONFIG_BOARD_TPCI200=y
# CONFIG_SERIAL_IPOCTAL is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_TI_SYSCON=y
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
# CONFIG_USB_LGM_PHY is not set
CONFIG_PHY_CAN_TRANSCEIVER=y

#
# PHY drivers for Broadcom platforms
#
CONFIG_BCM_KONA_USB2_PHY=y
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_PXA_28NM_HSIC is not set
CONFIG_PHY_PXA_28NM_USB2=y
# CONFIG_PHY_INTEL_LGM_EMMC is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
CONFIG_MCB=y
CONFIG_MCB_PCI=y
# CONFIG_MCB_LPC is not set

#
# Performance monitor support
#
# end of Performance monitor support

# CONFIG_RAS is not set
CONFIG_USB4=y
# CONFIG_USB4_DEBUGFS_WRITE is not set
# CONFIG_USB4_DMA_TEST is not set

#
# Android
#
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android

CONFIG_DAX=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y

#
# Layout Types
#
# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set
# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set
# end of Layout Types

# CONFIG_NVMEM_RAVE_SP_EEPROM is not set
CONFIG_NVMEM_RMEM=y

#
# HW tracing support
#
# CONFIG_STM is not set
CONFIG_INTEL_TH=y
# CONFIG_INTEL_TH_PCI is not set
# CONFIG_INTEL_TH_ACPI is not set
CONFIG_INTEL_TH_GTH=y
CONFIG_INTEL_TH_MSU=y
CONFIG_INTEL_TH_PTI=y
CONFIG_INTEL_TH_DEBUG=y
# end of HW tracing support

CONFIG_FPGA=y
CONFIG_ALTERA_PR_IP_CORE=y
CONFIG_FPGA_MGR_ALTERA_CVP=y
# CONFIG_FPGA_BRIDGE is not set
# CONFIG_FPGA_DFL is not set
CONFIG_TEE=y
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
CONFIG_MUX_ADG792A=y
CONFIG_MUX_GPIO=y
# end of Multiplexer drivers

CONFIG_PM_OPP=y
CONFIG_SIOX=y
CONFIG_SIOX_BUS_GPIO=y
CONFIG_SLIMBUS=y
# CONFIG_SLIM_QCOM_CTRL is not set
CONFIG_INTERCONNECT=y
CONFIG_COUNTER=y
CONFIG_INTEL_QEP=y
CONFIG_INTERRUPT_CNT=y
CONFIG_MOST=y
CONFIG_MOST_CDEV=y
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_VALIDATE_FS_PARSER is not set
CONFIG_FS_IOMAP=y
CONFIG_LEGACY_DIRECT_IO=y
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_DEBUG=y
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
CONFIG_JFS_FS=y
# CONFIG_JFS_POSIX_ACL is not set
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_SUPPORT_ASCII_CI=y
# CONFIG_XFS_QUOTA is not set
CONFIG_XFS_POSIX_ACL=y
CONFIG_XFS_RT=y
CONFIG_XFS_DRAIN_INTENTS=y
CONFIG_XFS_ONLINE_SCRUB=y
# CONFIG_XFS_ONLINE_REPAIR is not set
CONFIG_XFS_DEBUG=y
CONFIG_XFS_ASSERT_FATAL=y
CONFIG_GFS2_FS=y
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
CONFIG_NILFS2_FS=y
# CONFIG_F2FS_FS is not set
CONFIG_ZONEFS_FS=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
# CONFIG_FS_ENCRYPTION is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_QUOTA_DEBUG=y
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS4_FS is not set
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=y
CONFIG_OVERLAY_FS=y
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set
CONFIG_OVERLAY_FS_INDEX=y
CONFIG_OVERLAY_FS_METACOPY=y

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
# CONFIG_NETFS_STATS is not set
# CONFIG_FSCACHE is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_NTFS_FS=y
CONFIG_NTFS_DEBUG=y
CONFIG_NTFS_RW=y
CONFIG_NTFS3_FS=y
# CONFIG_NTFS3_LZX_XPRESS is not set
CONFIG_NTFS3_FS_POSIX_ACL=y
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
# CONFIG_PROC_CHILDREN is not set
CONFIG_PROC_PID_ARCH_STATUS=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_TMPFS_XATTR is not set
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_CONFIGFS_FS=y
# end of Pseudo filesystems

# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=m
# CONFIG_NFS_SWAP is not set
# CONFIG_NFS_V4_1 is not set
# CONFIG_ROOT_NFS is not set
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
# CONFIG_CIFS_UPCALL is not set
# CONFIG_CIFS_XATTR is not set
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
# CONFIG_CIFS_DFS_UPCALL is not set
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_SMB_SERVER is not set
CONFIG_SMBFS_COMMON=m
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
# CONFIG_NLS_CODEPAGE_866 is not set
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
CONFIG_NLS_ISO8859_3=y
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
CONFIG_NLS_ISO8859_15=y
# CONFIG_NLS_KOI8_R is not set
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_MAC_ROMAN=y
CONFIG_NLS_MAC_CELTIC=y
CONFIG_NLS_MAC_CENTEURO=y
CONFIG_NLS_MAC_CROATIAN=y
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
CONFIG_NLS_MAC_ICELAND=y
CONFIG_NLS_MAC_INUIT=y
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
CONFIG_UNICODE=y
# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
CONFIG_TRUSTED_KEYS=y
CONFIG_TRUSTED_KEYS_TPM=y
CONFIG_TRUSTED_KEYS_TEE=y
CONFIG_ENCRYPTED_KEYS=y
# CONFIG_USER_DECRYPTED_DATA is not set
# CONFIG_KEY_DH_OPERATIONS is not set
CONFIG_KEY_NOTIFICATIONS=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_PATH=y
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper"
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
CONFIG_SECURITY_LOADPIN=y
# CONFIG_SECURITY_LOADPIN_ENFORCE is not set
# CONFIG_SECURITY_LOADPIN_VERITY is not set
# CONFIG_SECURITY_YAMA is not set
CONFIG_SECURITY_SAFESETID=y
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_IMA=y
CONFIG_IMA_MEASURE_PCR_IDX=10
CONFIG_IMA_NG_TEMPLATE=y
# CONFIG_IMA_SIG_TEMPLATE is not set
CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng"
CONFIG_IMA_DEFAULT_HASH_SHA1=y
# CONFIG_IMA_DEFAULT_HASH_SHA256 is not set
# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set
# CONFIG_IMA_DEFAULT_HASH_WP512 is not set
CONFIG_IMA_DEFAULT_HASH="sha1"
# CONFIG_IMA_WRITE_POLICY is not set
CONFIG_IMA_READ_POLICY=y
CONFIG_IMA_APPRAISE=y
# CONFIG_IMA_APPRAISE_BOOTPARAM is not set
# CONFIG_IMA_DISABLE_HTABLE is not set
CONFIG_EVM=y
# CONFIG_EVM_ATTR_FSUUID is not set
CONFIG_EVM_ADD_XATTRS=y
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,tomoyo,bpf"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_ENABLER=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
# CONFIG_INIT_STACK_NONE is not set
CONFIG_INIT_STACK_ALL_PATTERN=y
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
CONFIG_INIT_ON_FREE_DEFAULT_ON=y
# end of Memory initialization

CONFIG_RANDSTRUCT_NONE=y
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=y
CONFIG_ASYNC_XOR=y
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
# CONFIG_CRYPTO_PCRYPT is not set
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_SIMD=y
# end of Crypto core or helper

#
# Public-key cryptography
#
# CONFIG_CRYPTO_RSA is not set
CONFIG_CRYPTO_DH=y
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
# CONFIG_CRYPTO_ECDSA is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_SM2 is not set
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
# CONFIG_CRYPTO_ARIA is not set
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
# CONFIG_CRYPTO_CAST5 is not set
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_SERPENT=y
# CONFIG_CRYPTO_SM4_GENERIC is not set
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
# CONFIG_CRYPTO_ADIANTUM is not set
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
# CONFIG_CRYPTO_CFB is not set
CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_HCTR2 is not set
CONFIG_CRYPTO_KEYWRAP=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=y
# CONFIG_CRYPTO_XTS is not set
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=y
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ESSIV=y
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
# CONFIG_CRYPTO_BLAKE2B is not set
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
# CONFIG_CRYPTO_POLY1305 is not set
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SM3_GENERIC is not set
CONFIG_CRYPTO_STREEBOG=y
CONFIG_CRYPTO_VMAC=y
CONFIG_CRYPTO_WP512=y
# CONFIG_CRYPTO_XCBC is not set
CONFIG_CRYPTO_XXHASH=y
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_LZO is not set
CONFIG_CRYPTO_842=y
# CONFIG_CRYPTO_LZ4 is not set
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set
# CONFIG_CRYPTO_STATS is not set
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y

#
# Accelerated Cryptographic Algorithms for CPU (x86)
#
CONFIG_CRYPTO_AES_NI_INTEL=y
CONFIG_CRYPTO_SERPENT_SSE2_586=y
CONFIG_CRYPTO_TWOFISH_586=y
CONFIG_CRYPTO_CRC32C_INTEL=y
CONFIG_CRYPTO_CRC32_PCLMUL=y
# end of Accelerated Cryptographic Algorithms for CPU (x86)

# CONFIG_CRYPTO_HW is not set
# CONFIG_ASYMMETRIC_KEY_TYPE is not set

#
# Certificates for signature checking
#
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=y
CONFIG_PRIME_NUMBERS=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
CONFIG_CRC4=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_MICROLZMA=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_DEC16=y
CONFIG_BCH=y
CONFIG_INTERVAL_TREE=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_DMA_API_DEBUG is not set
CONFIG_DMA_MAP_BENCHMARK=y
CONFIG_SGL_ALLOC=y
CONFIG_CHECK_SIGNATURE=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_OID_REGISTRY=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
CONFIG_FONTS=y
# CONFIG_FONT_8x8 is not set
CONFIG_FONT_8x16=y
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
CONFIG_FONT_PEARL_8x8=y
# CONFIG_FONT_ACORN_8x8 is not set
CONFIG_FONT_MINI_4x6=y
CONFIG_FONT_6x10=y
# CONFIG_FONT_10x18 is not set
CONFIG_FONT_SUN8x16=y
# CONFIG_FONT_SUN12x22 is not set
CONFIG_FONT_TER16x32=y
# CONFIG_FONT_6x8 is not set
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_STACKDEPOT_ALWAYS_INIT=y
CONFIG_SBITMAP=y
# end of Library routines

CONFIG_ASN1_ENCODER=y
CONFIG_POLYNOMIAL=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_CALLER=y
CONFIG_STACKTRACE_BUILD_ID=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
CONFIG_DYNAMIC_DEBUG_CORE=y
# CONFIG_SYMBOLIC_ERRNAME is not set
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_AS_HAS_NON_CONST_LEB128=y
# CONFIG_DEBUG_INFO_NONE is not set
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
CONFIG_PAHOLE_HAS_BTF_TAG=y
CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=8192
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_HEADERS_INSTALL=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_FS_ALLOW_ALL is not set
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
CONFIG_DEBUG_FS_ALLOW_NONE=y
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
CONFIG_UBSAN=y
# CONFIG_UBSAN_TRAP is not set
CONFIG_CC_HAS_UBSAN_BOUNDS=y
CONFIG_CC_HAS_UBSAN_ARRAY_BOUNDS=y
CONFIG_UBSAN_BOUNDS=y
CONFIG_UBSAN_ARRAY_BOUNDS=y
CONFIG_UBSAN_SHIFT=y
CONFIG_UBSAN_UNREACHABLE=y
# CONFIG_UBSAN_BOOL is not set
# CONFIG_UBSAN_ENUM is not set
# CONFIG_UBSAN_ALIGNMENT is not set
CONFIG_UBSAN_SANITIZE_ALL=y
# CONFIG_TEST_UBSAN is not set
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
CONFIG_SLUB_DEBUG_ON=y
CONFIG_PAGE_OWNER=y
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
CONFIG_DEBUG_WX=y
CONFIG_GENERIC_PTDUMP=y
CONFIG_PTDUMP_CORE=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000
# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set
CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y
CONFIG_DEBUG_OBJECTS=y
# CONFIG_DEBUG_OBJECTS_SELFTEST is not set
# CONFIG_DEBUG_OBJECTS_FREE is not set
# CONFIG_DEBUG_OBJECTS_TIMERS is not set
# CONFIG_DEBUG_OBJECTS_WORK is not set
# CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set
# CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER is not set
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
# CONFIG_SHRINKER_DEBUG is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PER_CPU_MAPS is not set
# CONFIG_DEBUG_KMAP_LOCAL is not set
CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y
# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
# CONFIG_DEBUG_HIGHMEM is not set
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
# CONFIG_DEBUG_STACKOVERFLOW is not set
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
CONFIG_HAVE_KMSAN_COMPILER=y
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=480
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_WQ_WATCHDOG=y
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

CONFIG_DEBUG_TIMEKEEPING=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_PROVE_LOCKING=y
# CONFIG_PROVE_RAW_LOCK_NESTING is not set
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_LOCKDEP=y
CONFIG_LOCKDEP_BITS=15
CONFIG_LOCKDEP_CHAINS_BITS=16
CONFIG_LOCKDEP_STACK_TRACE_BITS=19
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_LOCK_TORTURE_TEST=m
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

CONFIG_TRACE_IRQFLAGS=y
CONFIG_TRACE_IRQFLAGS_NMI=y
# CONFIG_NMI_CHECK_CPU is not set
CONFIG_DEBUG_IRQFLAGS=y
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
# CONFIG_PROVE_RCU_LIST is not set
CONFIG_TORTURE_TEST=m
CONFIG_RCU_SCALE_TEST=m
CONFIG_RCU_TORTURE_TEST=m
CONFIG_RCU_REF_SCALE_TEST=m
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_CPU_STALL_CPUTIME is not set
CONFIG_RCU_TRACE=y
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
CONFIG_LATENCYTOP=y
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_RETHOOK=y
CONFIG_RETHOOK=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_PREEMPTIRQ_TRACEPOINTS=y
CONFIG_TRACING=y
CONFIG_GLOBAL_TRACE_BUF_SIZE=1441792
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
# CONFIG_MMIOTRACE is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
CONFIG_BPF_KPROBE_OVERRIDE=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_USER_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_RV is not set
CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
CONFIG_SAMPLES=y
# CONFIG_SAMPLE_AUXDISPLAY is not set
# CONFIG_SAMPLE_TRACE_EVENTS is not set
# CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS is not set
# CONFIG_SAMPLE_TRACE_PRINTK is not set
# CONFIG_SAMPLE_TRACE_ARRAY is not set
CONFIG_SAMPLE_KOBJECT=y
# CONFIG_SAMPLE_KPROBES is not set
# CONFIG_SAMPLE_HW_BREAKPOINT is not set
# CONFIG_SAMPLE_KFIFO is not set
# CONFIG_SAMPLE_RPMSG_CLIENT is not set
# CONFIG_SAMPLE_CONFIGFS is not set
# CONFIG_SAMPLE_CONNECTOR is not set
# CONFIG_SAMPLE_FANOTIFY_ERROR is not set
CONFIG_SAMPLE_HIDRAW=y
CONFIG_SAMPLE_LANDLOCK=y
CONFIG_SAMPLE_PIDFD=y
# CONFIG_SAMPLE_SECCOMP is not set
CONFIG_SAMPLE_TIMER=y
CONFIG_SAMPLE_UHID=y
# CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set
# CONFIG_SAMPLE_ANDROID_BINDERFS is not set
CONFIG_SAMPLE_VFS=y
CONFIG_SAMPLE_INTEL_MEI=y
CONFIG_SAMPLE_WATCHDOG=y
# CONFIG_SAMPLE_WATCH_QUEUE is not set
# CONFIG_SAMPLE_KMEMLEAK is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set

#
# x86 Debugging
#
CONFIG_EARLY_PRINTK_USB=y
CONFIG_X86_VERBOSE_BOOTUP=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_DBGP=y
CONFIG_EARLY_PRINTK_USB_XDBC=y
# CONFIG_DEBUG_TLBFLUSH is not set
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
# CONFIG_X86_DECODER_SELFTEST is not set
# CONFIG_IO_DELAY_0X80 is not set
CONFIG_IO_DELAY_0XED=y
# CONFIG_IO_DELAY_UDELAY is not set
# CONFIG_IO_DELAY_NONE is not set
# CONFIG_DEBUG_BOOT_PARAMS is not set
# CONFIG_CPA_DEBUG is not set
# CONFIG_DEBUG_ENTRY is not set
# CONFIG_DEBUG_NMI_SELFTEST is not set
CONFIG_X86_DEBUG_FPU=y
CONFIG_PUNIT_ATOM_DEBUG=y
CONFIG_UNWINDER_FRAME_POINTER=y
# end of x86 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FUNCTION_ERROR_INJECTION=y
# CONFIG_FAULT_INJECTION is not set
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_TEST_DHRY is not set
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TEST_REF_TRACKER is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_STRING_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_MAPLE_TREE is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
# CONFIG_TEST_FPU is not set
# CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set
CONFIG_ARCH_USE_MEMTEST=y
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
  2023-05-18  7:53   ` kernel test robot
@ 2023-05-18  9:28   ` kernel test robot
  2023-05-18 10:44   ` Andrzej Hajda
  2 siblings, 0 replies; 21+ messages in thread
From: kernel test robot @ 2023-05-18  9:28 UTC (permalink / raw)
  To: Matt Roper, intel-gfx; +Cc: Matt Roper, intel-xe, oe-kbuild-all

[-- Attachment #1: Type: text/plain, Size: 2110 bytes --]

Hi Matt,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Matt-Roper/drm-i915-display-Move-display-device-info-to-header-under-display/20230518-112007
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230518031804.3133486-6-matthew.d.roper%40intel.com
patch subject: [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code
config: i386-randconfig-s001
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.4-39-gce1a6720-dirty
        # https://github.com/intel-lab-lkp/linux/commit/fc14367208dfb37157d27e941b61827dc058c60b
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Matt-Roper/drm-i915-display-Move-display-device-info-to-header-under-display/20230518-112007
        git checkout fc14367208dfb37157d27e941b61827dc058c60b
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=i386 olddefconfig
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202305181708.Ze7kK58y-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/display/intel_display_device.c:691:3: sparse: sparse: symbol 'gmdid_display_map' was not declared. Should it be static?

vim +/gmdid_display_map +691 drivers/gpu/drm/i915/display/intel_display_device.c

   686	
   687	struct {
   688		u16 ver;
   689		u16 rel;
   690		const struct intel_display_device_info *display;
 > 691	} gmdid_display_map[] = {
   692		{ 14,  0, &xe_lpdp_display },
   693	};
   694	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[-- Attachment #2: config --]
[-- Type: text/plain, Size: 152619 bytes --]

#
# Automatically generated file; DO NOT EDIT.
# Linux/i386 6.4.0-rc2 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="gcc-11 (Debian 11.3.0-12) 11.3.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=110300
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24000
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24000
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=125
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_HAVE_KERNEL_ZSTD=y
# CONFIG_KERNEL_GZIP is not set
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_KERNEL_LZ4=y
# CONFIG_KERNEL_ZSTD is not set
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_WATCH_QUEUE is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_USELIB=y
# CONFIG_AUDIT is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_GENERIC_IRQ_DEBUGFS=y
# end of IRQ subsystem

CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_ARCH_CLOCKSOURCE_INIT=y
CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=125
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y

#
# BPF subsystem
#
# CONFIG_BPF_SYSCALL is not set
# CONFIG_BPF_JIT is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_DYNAMIC is not set

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_IRQ_TIME_ACCOUNTING=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

#
# RCU Subsystem
#
CONFIG_TINY_RCU=y
CONFIG_RCU_EXPERT=y
CONFIG_TINY_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_FORCE_TASKS_RCU=y
CONFIG_TASKS_RCU=y
CONFIG_FORCE_TASKS_RUDE_RCU=y
CONFIG_TASKS_RUDE_RCU=y
CONFIG_FORCE_TASKS_TRACE_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_TASKS_TRACE_RCU_READ_MB=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=20
# CONFIG_PRINTK_INDEX is not set
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y

#
# Scheduler features
#
# end of Scheduler features

CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
# CONFIG_RT_GROUP_SCHED is not set
# CONFIG_CGROUP_PIDS is not set
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
# CONFIG_CGROUP_DEVICE is not set
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
# CONFIG_CGROUP_MISC is not set
# CONFIG_CGROUP_DEBUG is not set
# CONFIG_NAMESPACES is not set
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
# CONFIG_BOOT_CONFIG is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_PCSPKR_PLATFORM=y
# CONFIG_BASE_FULL is not set
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
# CONFIG_ADVISE_SYSCALLS is not set
# CONFIG_MEMBARRIER is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
# CONFIG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_X86_32=y
CONFIG_FORCE_DYNAMIC_FTRACE=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf32-i386"
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_BUG=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_CC_HAS_SANE_STACKPROTECTOR=y

#
# Processor type and features
#
# CONFIG_SMP is not set
CONFIG_X86_FEATURE_NAMES=y
CONFIG_X86_MPPARSE=y
CONFIG_GOLDFISH=y
# CONFIG_X86_EXTENDED_PLATFORM is not set
# CONFIG_X86_INTEL_LPSS is not set
# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
CONFIG_IOSF_MBI=y
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_X86_32_IRIS=y
# CONFIG_SCHED_OMIT_FRAME_POINTER is not set
CONFIG_HYPERVISOR_GUEST=y
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_DEBUG is not set
CONFIG_X86_HV_CALLBACK_VECTOR=y
CONFIG_KVM_GUEST=y
CONFIG_ARCH_CPUIDLE_HALTPOLL=y
# CONFIG_PVH is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_PARAVIRT_CLOCK=y
# CONFIG_M486SX is not set
# CONFIG_M486 is not set
# CONFIG_M586 is not set
# CONFIG_M586TSC is not set
# CONFIG_M586MMX is not set
# CONFIG_M686 is not set
# CONFIG_MPENTIUMII is not set
# CONFIG_MPENTIUMIII is not set
# CONFIG_MPENTIUMM is not set
# CONFIG_MPENTIUM4 is not set
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
# CONFIG_MCRUSOE is not set
# CONFIG_MEFFICEON is not set
# CONFIG_MWINCHIPC6 is not set
CONFIG_MWINCHIP3D=y
# CONFIG_MELAN is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
# CONFIG_MCYRIXIII is not set
# CONFIG_MVIAC3_2 is not set
# CONFIG_MVIAC7 is not set
# CONFIG_MCORE2 is not set
# CONFIG_MATOM is not set
CONFIG_X86_GENERIC=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_ALIGNMENT_16=y
CONFIG_X86_INTEL_USERCOPY=y
CONFIG_X86_USE_PPRO_CHECKSUM=y
CONFIG_X86_TSC=y
CONFIG_X86_MINIMUM_CPU_FAMILY=4
CONFIG_PROCESSOR_SELECT=y
# CONFIG_CPU_SUP_INTEL is not set
# CONFIG_CPU_SUP_CYRIX_32 is not set
# CONFIG_CPU_SUP_AMD is not set
# CONFIG_CPU_SUP_HYGON is not set
# CONFIG_CPU_SUP_CENTAUR is not set
# CONFIG_CPU_SUP_TRANSMETA_32 is not set
# CONFIG_CPU_SUP_UMC_32 is not set
# CONFIG_CPU_SUP_ZHAOXIN is not set
CONFIG_CPU_SUP_VORTEX_32=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_EMULATE_RTC=y
CONFIG_DMI=y
CONFIG_NR_CPUS_RANGE_BEGIN=1
CONFIG_NR_CPUS_RANGE_END=1
CONFIG_NR_CPUS_DEFAULT=1
CONFIG_NR_CPUS=1
CONFIG_UP_LATE_INIT=y
CONFIG_X86_UP_APIC=y
# CONFIG_X86_UP_IOAPIC is not set
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
# CONFIG_X86_MCE is not set

#
# Performance monitoring
#
# end of Performance monitoring

# CONFIG_X86_LEGACY_VM86 is not set
CONFIG_X86_IOPL_IOPERM=y
CONFIG_TOSHIBA=y
# CONFIG_X86_REBOOTFIXUPS is not set
CONFIG_X86_MSR=y
CONFIG_X86_CPUID=m
# CONFIG_NOHIGHMEM is not set
CONFIG_HIGHMEM4G=y
# CONFIG_VMSPLIT_3G is not set
# CONFIG_VMSPLIT_3G_OPT is not set
CONFIG_VMSPLIT_2G=y
# CONFIG_VMSPLIT_2G_OPT is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0x80000000
CONFIG_HIGHMEM=y
# CONFIG_X86_CPA_STATISTICS is not set
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ILLEGAL_POINTER_VALUE=0
CONFIG_HIGHPTE=y
# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
# CONFIG_MTRR is not set
CONFIG_X86_UMIP=y
CONFIG_CC_HAS_IBT=y
# CONFIG_EFI is not set
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
CONFIG_PHYSICAL_START=0x1000000
# CONFIG_RELOCATABLE is not set
CONFIG_PHYSICAL_ALIGN=0x200000
# CONFIG_COMPAT_VDSO is not set
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_MODIFY_LDT_SYSCALL is not set
# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
# end of Processor type and features

CONFIG_CC_HAS_SLS=y
CONFIG_CC_HAS_RETURN_THUNK=y
CONFIG_CC_HAS_ENTRY_PADDING=y
CONFIG_FUNCTION_PADDING_CFI=11
CONFIG_FUNCTION_PADDING_BYTES=16
CONFIG_SPECULATION_MITIGATIONS=y
# CONFIG_RETPOLINE is not set
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y

#
# Power management and ACPI options
#
# CONFIG_SUSPEND is not set
# CONFIG_PM is not set
CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=y
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_CPU_FREQ_PSS=y
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_PROCESSOR=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_CUSTOM_DSDT_FILE=""
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_PCI_SLOT is not set
# CONFIG_ACPI_CONTAINER is not set
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_SBS is not set
# CONFIG_ACPI_HED is not set
# CONFIG_ACPI_CUSTOM_METHOD is not set
# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
CONFIG_HAVE_ACPI_APEI=y
CONFIG_HAVE_ACPI_APEI_NMI=y
# CONFIG_ACPI_APEI is not set
# CONFIG_ACPI_DPTF is not set
# CONFIG_ACPI_CONFIGFS is not set
# CONFIG_ACPI_FFH is not set
# CONFIG_PMIC_OPREGION is not set
CONFIG_X86_PM_TIMER=y

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_X86_INTEL_PSTATE=y
# CONFIG_X86_PCC_CPUFREQ is not set
# CONFIG_X86_AMD_PSTATE is not set
# CONFIG_X86_AMD_PSTATE_UT is not set
# CONFIG_X86_ACPI_CPUFREQ is not set
CONFIG_X86_POWERNOW_K6=m
CONFIG_X86_POWERNOW_K7=m
CONFIG_X86_POWERNOW_K7_ACPI=y
CONFIG_X86_GX_SUSPMOD=m
CONFIG_X86_SPEEDSTEP_CENTRINO=y
CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE=y
CONFIG_X86_SPEEDSTEP_ICH=y
# CONFIG_X86_SPEEDSTEP_SMI is not set
CONFIG_X86_P4_CLOCKMOD=y
# CONFIG_X86_CPUFREQ_NFORCE2 is not set
# CONFIG_X86_LONGRUN is not set
# CONFIG_X86_LONGHAUL is not set
# CONFIG_X86_E_POWERSAVER is not set

#
# shared options
#
CONFIG_X86_SPEEDSTEP_LIB=y
# CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK is not set
# end of CPU Frequency scaling

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
# CONFIG_CPU_IDLE_GOV_MENU is not set
CONFIG_CPU_IDLE_GOV_TEO=y
CONFIG_CPU_IDLE_GOV_HALTPOLL=y
CONFIG_HALTPOLL_CPUIDLE=y
# end of CPU Idle
# end of Power management and ACPI options

#
# Bus options (PCI etc.)
#
# CONFIG_PCI_GOBIOS is not set
# CONFIG_PCI_GOMMCONFIG is not set
# CONFIG_PCI_GODIRECT is not set
CONFIG_PCI_GOOLPC=y
# CONFIG_PCI_GOANY is not set
CONFIG_PCI_DIRECT=y
CONFIG_PCI_OLPC=y
CONFIG_PCI_CNB20LE_QUIRK=y
CONFIG_ISA_BUS=y
CONFIG_ISA_DMA_API=y
# CONFIG_ISA is not set
# CONFIG_SCx200 is not set
CONFIG_OLPC=y
# CONFIG_OLPC_XO15_SCI is not set
CONFIG_ALIX=y
# CONFIG_NET5501 is not set
CONFIG_GEOS=y
# end of Bus options (PCI etc.)

#
# Binary Emulations
#
CONFIG_COMPAT_32=y
# end of Binary Emulations

CONFIG_HAVE_ATOMIC_IOMAP=y
CONFIG_HAVE_KVM=y
CONFIG_VIRTUALIZATION=y
# CONFIG_KVM is not set
CONFIG_AS_AVX512=y
CONFIG_AS_SHA1_NI=y
CONFIG_AS_SHA256_NI=y
CONFIG_AS_TPAUSE=y
CONFIG_AS_GFNI=y

#
# General architecture-dependent options
#
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_GENERIC_ENTRY=y
CONFIG_KPROBES=y
# CONFIG_JUMP_LABEL is not set
# CONFIG_STATIC_CALL_SELFTEST is not set
CONFIG_OPTPROBES=y
CONFIG_KPROBES_ON_FTRACE=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_KRETPROBES=y
CONFIG_KRETPROBE_ON_RETHOOK=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_GATHER_MERGE_VMAS=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
# CONFIG_SECCOMP is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
# CONFIG_STACKPROTECTOR_STRONG is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=8
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ISA_BUS_API=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_MEM_ENCRYPT=y
CONFIG_HAVE_STATIC_CALL=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SPLIT_ARG64=y
CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
CONFIG_DYNAMIC_SIGFRAME=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT_16B=y
CONFIG_FUNCTION_ALIGNMENT=16
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=1
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y
CONFIG_MODPROBE_PATH="/sbin/modprobe"
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_UNUSED_KSYMS_WHITELIST=""
CONFIG_MODULES_TREE_LOOKUP=y
# CONFIG_BLOCK is not set
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ELFCORE=y
CONFIG_BINFMT_SCRIPT=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_COREDUMP is not set
# end of Executable file formats

#
# Memory Management options
#

#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLUB_TINY is not set
# CONFIG_SLAB_MERGE_DEFAULT is not set
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
# CONFIG_SLUB_STATS is not set
# end of SLAB allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
CONFIG_COMPAT_BRK=y
CONFIG_SELECT_MEMORY_MODEL=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_MMU_NOTIFIER=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_READ_ONLY_THP_FOR_FS=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_CMA=y
CONFIG_CMA_DEBUG=y
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_VMAP_PFN=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PERCPU_STATS=y
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_MAPPING_DIRTY_HELPERS=y
CONFIG_KMAP_LOCAL=y
CONFIG_SECRETMEM=y
# CONFIG_USERFAULTFD is not set

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_TLS is not set
# CONFIG_XFRM_USER is not set
# CONFIG_NET_KEY is not set
CONFIG_NET_HANDSHAKE=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_NET_IP_TUNNEL=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_NET_IPVTI is not set
# CONFIG_NET_FOU is not set
# CONFIG_NET_FOU_IP_TUNNELS is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_INET_UDP_DIAG is not set
# CONFIG_INET_RAW_DIAG is not set
# CONFIG_INET_DIAG_DESTROY is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_IPV6_VTI is not set
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
# CONFIG_IPV6_TUNNEL is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_IPV6_MROUTE is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
# CONFIG_NETLABEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_BPFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC2 is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=m
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
# CONFIG_NET_SWITCHDEV is not set
# CONFIG_NET_L3_MASTER_DEV is not set
# CONFIG_QRTR is not set
# CONFIG_NET_NCSI is not set
CONFIG_MAX_SKB_FRAGS=17
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
# CONFIG_MCTP is not set
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set

#
# CFG80211 needs to be enabled for MAC80211
#
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_RFKILL is not set
CONFIG_NET_9P=y
CONFIG_NET_9P_FD=y
CONFIG_NET_9P_VIRTIO=y
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_FAILOVER=m
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_HAVE_EISA=y
# CONFIG_EISA is not set
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=m
# CONFIG_PCIE_ECRC is not set
# CONFIG_PCIEASPM is not set
# CONFIG_PCIE_DPC is not set
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
CONFIG_PCI_REALLOC_ENABLE_AUTO=y
CONFIG_PCI_STUB=m
# CONFIG_PCI_PF_STUB is not set
CONFIG_PCI_ATS=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_LOCKLESS_CONFIG=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_VGA_ARB is not set
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_ACPI is not set
CONFIG_HOTPLUG_PCI_CPCI=y
CONFIG_HOTPLUG_PCI_CPCI_ZT5550=y
# CONFIG_HOTPLUG_PCI_CPCI_GENERIC is not set
CONFIG_HOTPLUG_PCI_SHPC=y

#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
# CONFIG_PCI_HOST_GENERIC is not set
CONFIG_PCIE_MICROCHIP_HOST=y
# CONFIG_PCIE_XILINX is not set

#
# Cadence-based PCIe controllers
#
CONFIG_PCIE_CADENCE=y
CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_CADENCE_EP=y
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCIE_CADENCE_PLAT_EP is not set
CONFIG_PCI_J721E=y
CONFIG_PCI_J721E_HOST=y
CONFIG_PCI_J721E_EP=y
# end of Cadence-based PCIe controllers

#
# DesignWare-based PCIe controllers
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
CONFIG_PCI_MESON=y
CONFIG_PCIE_INTEL_GW=y
CONFIG_PCIE_DW_PLAT=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_DW_PLAT_EP=y
# end of DesignWare-based PCIe controllers

#
# Mobiveil-based PCIe controllers
#
# end of Mobiveil-based PCIe controllers
# end of PCI controller drivers

#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_EPF_TEST is not set
# CONFIG_PCI_EPF_NTB is not set
# CONFIG_PCI_EPF_VNTB is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=y
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_DEVTMPFS=y
# CONFIG_DEVTMPFS_MOUNT is not set
# CONFIG_DEVTMPFS_SAFE is not set
# CONFIG_STANDALONE is not set
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
# CONFIG_FW_LOADER_COMPRESS_ZSTD is not set
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGMAP_W1=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_REGMAP_I3C=m
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_FENCE_TRACE=y
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
# CONFIG_MHI_BUS_PCI_GENERIC is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

# CONFIG_CONNECTOR is not set

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
# end of ARM System Control and Management Interface Protocol

CONFIG_EDD=y
CONFIG_EDD_OFF=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
# CONFIG_SYSFB_SIMPLEFB is not set
# CONFIG_GOOGLE_FIRMWARE is not set

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

# CONFIG_GNSS is not set
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_OF_PARTS is not set
CONFIG_MTD_REDBOOT_PARTS=m
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_OOPS=y
CONFIG_MTD_PARTITIONED_MASTER=y

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=m
# CONFIG_MTD_CFI_AMDSTD is not set
CONFIG_MTD_CFI_STAA=m
CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
CONFIG_MTD_ABSENT=y
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_PHYSMAP_COMPAT=y
CONFIG_MTD_PHYSMAP_START=0x8000000
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_PHYSMAP_OF is not set
CONFIG_MTD_PHYSMAP_GPIO_ADDR=y
CONFIG_MTD_SBC_GXX=m
CONFIG_MTD_PCI=m
CONFIG_MTD_INTEL_VR_NOR=y
CONFIG_MTD_PLATRAM=y
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
CONFIG_MTD_PMC551=y
CONFIG_MTD_PMC551_BUGFIX=y
CONFIG_MTD_PMC551_DEBUG=y
# CONFIG_MTD_SLRAM is not set
CONFIG_MTD_PHRAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=4096
CONFIG_MTDRAM_ERASE_SIZE=128

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_ONENAND=m
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
# CONFIG_MTD_ONENAND_GENERIC is not set
CONFIG_MTD_ONENAND_OTP=y
# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
# CONFIG_MTD_RAW_NAND is not set

#
# ECC engine support
#
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
# CONFIG_MTD_NAND_ECC_MXIC is not set
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
CONFIG_MTD_LPDDR=y
CONFIG_MTD_QINFO_PROBE=y
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
CONFIG_MTD_UBI_GLUEBI=y
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_PROMTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_PARPORT=y
CONFIG_PARPORT_PC=y
# CONFIG_PARPORT_SERIAL is not set
# CONFIG_PARPORT_PC_FIFO is not set
# CONFIG_PARPORT_PC_SUPERIO is not set
CONFIG_PARPORT_1284=y
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y

#
# NVME Support
#
# end of NVME Support

#
# Misc devices
#
CONFIG_AD525X_DPOT=y
# CONFIG_AD525X_DPOT_I2C is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_IBM_ASM is not set
CONFIG_PHANTOM=y
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
CONFIG_ICS932S401=m
CONFIG_ENCLOSURE_SERVICES=y
CONFIG_CS5535_MFGPT=m
CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7
CONFIG_CS5535_CLOCK_EVENT_SRC=m
# CONFIG_HI6421V600_IRQ is not set
CONFIG_HP_ILO=y
CONFIG_APDS9802ALS=y
# CONFIG_ISL29003 is not set
CONFIG_ISL29020=m
CONFIG_SENSORS_TSL2550=m
CONFIG_SENSORS_BH1770=y
CONFIG_SENSORS_APDS990X=m
CONFIG_HMC6352=y
CONFIG_DS1682=y
CONFIG_PCH_PHUB=y
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
CONFIG_XILINX_SDFEC=m
CONFIG_MISC_RTSX=m
CONFIG_HISI_HIKEY_USB=m
# CONFIG_VCPU_STALL_DETECTOR is not set
CONFIG_C2PORT=y
CONFIG_C2PORT_DURAMAR_2150=y

#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
# CONFIG_EEPROM_LEGACY is not set
CONFIG_EEPROM_MAX6875=y
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=m
CONFIG_CB710_DEBUG=y
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
CONFIG_ALTERA_STAPL=m
CONFIG_INTEL_MEI=y
CONFIG_INTEL_MEI_ME=y
CONFIG_INTEL_MEI_TXE=m
# CONFIG_INTEL_MEI_GSC is not set
# CONFIG_INTEL_MEI_HDCP is not set
CONFIG_INTEL_MEI_PXP=y
# CONFIG_INTEL_MEI_GSC_PROXY is not set
# CONFIG_VMWARE_VMCI is not set
CONFIG_ECHO=m
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
CONFIG_UACCE=m
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
# end of SCSI device support

# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
CONFIG_FIREWIRE=y
CONFIG_FIREWIRE_OHCI=y
# CONFIG_FIREWIRE_NET is not set
CONFIG_FIREWIRE_NOSY=y
# end of IEEE 1394 (FireWire) support

CONFIG_MACINTOSH_DRIVERS=y
# CONFIG_MAC_EMUMOUSEBTN is not set
CONFIG_NETDEVICES=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_WIREGUARD is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_IPVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_GENEVE is not set
# CONFIG_BAREUDP is not set
# CONFIG_GTP is not set
# CONFIG_MACSEC is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_TUN is not set
# CONFIG_TUN_VNET_CROSS_LE is not set
# CONFIG_VETH is not set
CONFIG_VIRTIO_NET=m
# CONFIG_NLMON is not set
# CONFIG_MHI_NET is not set
# CONFIG_ARCNET is not set
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_3COM=y
# CONFIG_VORTEX is not set
# CONFIG_TYPHOON is not set
CONFIG_NET_VENDOR_ADAPTEC=y
# CONFIG_ADAPTEC_STARFIRE is not set
CONFIG_NET_VENDOR_AGERE=y
# CONFIG_ET131X is not set
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_SLICOSS is not set
CONFIG_NET_VENDOR_ALTEON=y
# CONFIG_ACENIC is not set
# CONFIG_ALTERA_TSE is not set
CONFIG_NET_VENDOR_AMAZON=y
# CONFIG_ENA_ETHERNET is not set
# CONFIG_NET_VENDOR_AMD is not set
CONFIG_NET_VENDOR_AQUANTIA=y
# CONFIG_AQTION is not set
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ASIX=y
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
# CONFIG_ALX is not set
# CONFIG_CX_ECAT is not set
CONFIG_NET_VENDOR_BROADCOM=y
# CONFIG_B44 is not set
# CONFIG_BCMGENET is not set
# CONFIG_BNX2 is not set
# CONFIG_CNIC is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2X is not set
# CONFIG_SYSTEMPORT is not set
# CONFIG_BNXT is not set
CONFIG_NET_VENDOR_CADENCE=y
# CONFIG_MACB is not set
CONFIG_NET_VENDOR_CAVIUM=y
CONFIG_NET_VENDOR_CHELSIO=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_CHELSIO_T4 is not set
# CONFIG_CHELSIO_T4VF is not set
CONFIG_NET_VENDOR_CISCO=y
# CONFIG_ENIC is not set
CONFIG_NET_VENDOR_CORTINA=y
# CONFIG_GEMINI_ETHERNET is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DNET is not set
CONFIG_NET_VENDOR_DEC=y
# CONFIG_NET_TULIP is not set
CONFIG_NET_VENDOR_DLINK=y
# CONFIG_DL2K is not set
# CONFIG_SUNDANCE is not set
CONFIG_NET_VENDOR_EMULEX=y
# CONFIG_BE2NET is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
CONFIG_NET_VENDOR_EZCHIP=y
# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
CONFIG_NET_VENDOR_GOOGLE=y
# CONFIG_GVE is not set
CONFIG_NET_VENDOR_HUAWEI=y
# CONFIG_HINIC is not set
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=y
# CONFIG_E1000E is not set
# CONFIG_IGB is not set
# CONFIG_IGBVF is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
# CONFIG_IGC is not set
# CONFIG_JME is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
CONFIG_NET_VENDOR_MARVELL=y
# CONFIG_MVMDIO is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
CONFIG_NET_VENDOR_MELLANOX=y
# CONFIG_MLX4_EN is not set
# CONFIG_MLX5_CORE is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8851_MLL is not set
# CONFIG_KSZ884X_PCI is not set
CONFIG_NET_VENDOR_MICROCHIP=y
# CONFIG_LAN743X is not set
# CONFIG_VCAP is not set
CONFIG_NET_VENDOR_MICROSEMI=y
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_MYRI=y
# CONFIG_MYRI10GE is not set
# CONFIG_FEALNX is not set
CONFIG_NET_VENDOR_NI=y
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_NATSEMI=y
# CONFIG_NATSEMI is not set
# CONFIG_NS83820 is not set
CONFIG_NET_VENDOR_NETERION=y
# CONFIG_S2IO is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_8390=y
# CONFIG_NE2K_PCI is not set
CONFIG_NET_VENDOR_NVIDIA=y
# CONFIG_FORCEDETH is not set
CONFIG_NET_VENDOR_OKI=y
# CONFIG_PCH_GBE is not set
# CONFIG_ETHOC is not set
CONFIG_NET_VENDOR_PACKET_ENGINES=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
CONFIG_NET_VENDOR_PENSANDO=y
CONFIG_NET_VENDOR_QLOGIC=y
# CONFIG_QLA3XXX is not set
# CONFIG_QLCNIC is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_QED is not set
CONFIG_NET_VENDOR_BROCADE=y
# CONFIG_BNA is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCOM_EMAC is not set
# CONFIG_RMNET is not set
CONFIG_NET_VENDOR_RDC=y
# CONFIG_R6040 is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_ATP is not set
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_R8169 is not set
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_NET_VENDOR_SAMSUNG=y
# CONFIG_SXGBE_ETH is not set
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SILAN=y
# CONFIG_SC92031 is not set
CONFIG_NET_VENDOR_SIS=y
# CONFIG_SIS900 is not set
# CONFIG_SIS190 is not set
CONFIG_NET_VENDOR_SOLARFLARE=y
# CONFIG_SFC is not set
# CONFIG_SFC_FALCON is not set
# CONFIG_SFC_SIENA is not set
CONFIG_NET_VENDOR_SMSC=y
# CONFIG_EPIC100 is not set
# CONFIG_SMSC911X is not set
# CONFIG_SMSC9420 is not set
CONFIG_NET_VENDOR_SOCIONEXT=y
CONFIG_NET_VENDOR_STMICRO=y
# CONFIG_STMMAC_ETH is not set
CONFIG_NET_VENDOR_SUN=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NIU is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_NET_VENDOR_TEHUTI=y
# CONFIG_TEHUTI is not set
CONFIG_NET_VENDOR_TI=y
# CONFIG_TI_CPSW_PHY_SEL is not set
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
CONFIG_NET_VENDOR_VIA=y
# CONFIG_VIA_RHINE is not set
# CONFIG_VIA_VELOCITY is not set
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
CONFIG_NET_VENDOR_WIZNET=y
# CONFIG_WIZNET_W5100 is not set
# CONFIG_WIZNET_W5300 is not set
CONFIG_NET_VENDOR_XILINX=y
# CONFIG_XILINX_EMACLITE is not set
# CONFIG_XILINX_AXI_EMAC is not set
# CONFIG_XILINX_LL_TEMAC is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
# CONFIG_PHYLIB is not set
# CONFIG_PSE_CONTROLLER is not set
# CONFIG_MDIO_DEVICE is not set

#
# PCS device drivers
#
# end of PCS device drivers

# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set

#
# Host-side USB support is needed for USB Network Adapter support
#
CONFIG_USB_NET_DRIVERS=m
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_LAN78XX is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
# CONFIG_ATH5K_PCI is not set
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_WLAN_VENDOR_CISCO=y
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_WLAN_VENDOR_INTERSIL=y
# CONFIG_HOSTAP is not set
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WLAN_VENDOR_PURELIFI=y
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_WLAN_VENDOR_SILABS=y
CONFIG_WLAN_VENDOR_ST=y
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_WLAN_VENDOR_QUANTENNA=y
# CONFIG_WAN is not set

#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN

# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_USB4_NET is not set
# CONFIG_NETDEVSIM is not set
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=m
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_VIVALDIFMAP=y

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
CONFIG_KEYBOARD_ADP5520=m
CONFIG_KEYBOARD_ADP5588=m
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1050 is not set
CONFIG_KEYBOARD_QT1070=m
# CONFIG_KEYBOARD_QT2160 is not set
CONFIG_KEYBOARD_DLINK_DIR685=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_GPIO=m
CONFIG_KEYBOARD_GPIO_POLLED=m
# CONFIG_KEYBOARD_TCA6416 is not set
CONFIG_KEYBOARD_TCA8418=m
CONFIG_KEYBOARD_MATRIX=m
# CONFIG_KEYBOARD_LM8323 is not set
CONFIG_KEYBOARD_LM8333=m
CONFIG_KEYBOARD_MAX7359=m
# CONFIG_KEYBOARD_MCS is not set
CONFIG_KEYBOARD_MPR121=m
# CONFIG_KEYBOARD_NEWTON is not set
CONFIG_KEYBOARD_OPENCORES=m
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
CONFIG_KEYBOARD_GOLDFISH_EVENTS=m
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_OMAP4=m
CONFIG_KEYBOARD_TC3589X=m
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
CONFIG_KEYBOARD_XTKBD=m
# CONFIG_KEYBOARD_CAP11XX is not set
CONFIG_KEYBOARD_BCM=m
# CONFIG_KEYBOARD_CYPRESS_SF is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
# CONFIG_JOYSTICK_GUILLEMOT is not set
CONFIG_JOYSTICK_INTERACT=m
# CONFIG_JOYSTICK_SIDEWINDER is not set
# CONFIG_JOYSTICK_TMDC is not set
# CONFIG_JOYSTICK_IFORCE is not set
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
# CONFIG_JOYSTICK_STINGER is not set
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_DB9=m
CONFIG_JOYSTICK_GAMECON=m
# CONFIG_JOYSTICK_TURBOGRAFX is not set
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_JOYSTICK_XPAD=m
# CONFIG_JOYSTICK_XPAD_FF is not set
# CONFIG_JOYSTICK_XPAD_LEDS is not set
CONFIG_JOYSTICK_WALKERA0701=m
CONFIG_JOYSTICK_PXRC=m
# CONFIG_JOYSTICK_QWIIC is not set
CONFIG_JOYSTICK_FSIA6B=m
# CONFIG_JOYSTICK_SENSEHAT is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_RMI4_CORE is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_CT82C710=m
CONFIG_SERIO_PARKBD=y
CONFIG_SERIO_PCIPS2=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=y
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
CONFIG_SERIO_ARC_PS2=y
CONFIG_SERIO_APBPS2=y
CONFIG_SERIO_GPIO_PS2=m
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
CONFIG_GAMEPORT_NS558=m
# CONFIG_GAMEPORT_L4 is not set
CONFIG_GAMEPORT_EMU10K1=m
CONFIG_GAMEPORT_FM801=m
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
# CONFIG_VT is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LEGACY_TIOCSTI=y
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_PCILIB=y
CONFIG_SERIAL_8250_PCI=m
CONFIG_SERIAL_8250_EXAR=m
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
# CONFIG_SERIAL_8250_LPSS is not set
CONFIG_SERIAL_8250_MID=y
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_UARTLITE=m
CONFIG_SERIAL_UARTLITE_NR_UARTS=1
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_SERIAL_JSM=m
CONFIG_SERIAL_SIFIVE=y
CONFIG_SERIAL_SIFIVE_CONSOLE=y
CONFIG_SERIAL_LANTIQ=y
# CONFIG_SERIAL_LANTIQ_CONSOLE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_SERIAL_ALTERA_JTAGUART=m
CONFIG_SERIAL_ALTERA_UART=y
CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
# CONFIG_SERIAL_ALTERA_UART_CONSOLE is not set
# CONFIG_SERIAL_PCH_UART is not set
CONFIG_SERIAL_XILINX_PS_UART=m
CONFIG_SERIAL_ARC=m
CONFIG_SERIAL_ARC_NR_PORTS=1
CONFIG_SERIAL_RP2=m
CONFIG_SERIAL_RP2_NR_UARTS=32
CONFIG_SERIAL_FSL_LPUART=y
# CONFIG_SERIAL_FSL_LPUART_CONSOLE is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
CONFIG_SERIAL_SPRD=m
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_MOXA_INTELLIO=m
CONFIG_MOXA_SMARTIO=m
CONFIG_SYNCLINK_GT=y
# CONFIG_N_HDLC is not set
# CONFIG_GOLDFISH_TTY is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
# CONFIG_RPMSG_TTY is not set
# CONFIG_SERIAL_DEV_BUS is not set
CONFIG_TTY_PRINTK=m
CONFIG_TTY_PRINTK_LEVEL=6
CONFIG_PRINTER=y
CONFIG_LP_CONSOLE=y
# CONFIG_PPDEV is not set
# CONFIG_VIRTIO_CONSOLE is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_SSIF_IPMI_BMC is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_INTEL is not set
# CONFIG_HW_RANDOM_AMD is not set
CONFIG_HW_RANDOM_BA431=m
CONFIG_HW_RANDOM_GEODE=y
# CONFIG_HW_RANDOM_VIA is not set
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_HW_RANDOM_CCTRNG=y
CONFIG_HW_RANDOM_XIPHERA=y
# CONFIG_APPLICOM is not set
CONFIG_SONYPI=m
# CONFIG_MWAVE is not set
CONFIG_PC8736x_GPIO=y
CONFIG_NSC_GPIO=y
# CONFIG_DEVMEM is not set
CONFIG_NVRAM=m
CONFIG_DEVPORT=y
# CONFIG_HPET is not set
CONFIG_HANGCHECK_TIMER=y
CONFIG_TCG_TPM=y
# CONFIG_HW_RANDOM_TPM is not set
CONFIG_TCG_TIS_CORE=m
CONFIG_TCG_TIS=m
# CONFIG_TCG_TIS_I2C is not set
# CONFIG_TCG_TIS_I2C_CR50 is not set
CONFIG_TCG_TIS_I2C_ATMEL=m
# CONFIG_TCG_TIS_I2C_INFINEON is not set
CONFIG_TCG_TIS_I2C_NUVOTON=y
CONFIG_TCG_NSC=y
# CONFIG_TCG_ATMEL is not set
# CONFIG_TCG_INFINEON is not set
# CONFIG_TCG_CRB is not set
CONFIG_TCG_VTPM_PROXY=y
CONFIG_TCG_TIS_ST33ZP24=m
CONFIG_TCG_TIS_ST33ZP24_I2C=m
# CONFIG_TELCLOCK is not set
CONFIG_XILLYBUS_CLASS=m
CONFIG_XILLYBUS=m
# CONFIG_XILLYBUS_PCIE is not set
CONFIG_XILLYBUS_OF=m
# CONFIG_XILLYUSB is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
# CONFIG_I2C_MUX_GPIO is not set
CONFIG_I2C_MUX_GPMUX=y
# CONFIG_I2C_MUX_LTC4306 is not set
# CONFIG_I2C_MUX_PCA9541 is not set
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_I2C_MUX_PINCTRL is not set
# CONFIG_I2C_MUX_REG is not set
# CONFIG_I2C_DEMUX_PINCTRL is not set
CONFIG_I2C_MUX_MLXCPLD=y
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCA=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
CONFIG_I2C_ALI1535=m
# CONFIG_I2C_ALI1563 is not set
CONFIG_I2C_ALI15X3=m
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
CONFIG_I2C_I801=y
# CONFIG_I2C_ISCH is not set
CONFIG_I2C_ISMT=m
CONFIG_I2C_PIIX4=m
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
CONFIG_I2C_SIS5595=m
# CONFIG_I2C_SIS630 is not set
CONFIG_I2C_SIS96X=m
CONFIG_I2C_VIA=y
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CBUS_GPIO=y
CONFIG_I2C_DESIGNWARE_CORE=m
CONFIG_I2C_DESIGNWARE_SLAVE=y
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
CONFIG_I2C_DESIGNWARE_PCI=m
CONFIG_I2C_EG20T=m
CONFIG_I2C_EMEV2=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_PCA_PLATFORM=y
# CONFIG_I2C_PXA is not set
# CONFIG_I2C_RK3X is not set
CONFIG_I2C_SIMTEC=m
CONFIG_I2C_XILINX=y

#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=m
# CONFIG_I2C_DLN2 is not set
# CONFIG_I2C_CP2615 is not set
CONFIG_I2C_PARPORT=y
# CONFIG_I2C_PCI1XXXX is not set
CONFIG_I2C_ROBOTFUZZ_OSIF=m
CONFIG_I2C_TAOS_EVM=y
CONFIG_I2C_TINY_USB=m
# CONFIG_I2C_VIPERBOARD is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_SCx200_ACB is not set
CONFIG_I2C_FSI=m
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
# CONFIG_I2C_SLAVE_EEPROM is not set
# CONFIG_I2C_SLAVE_TESTUNIT is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

CONFIG_I3C=m
CONFIG_CDNS_I3C_MASTER=m
CONFIG_DW_I3C_MASTER=m
# CONFIG_SVC_I3C_MASTER is not set
# CONFIG_MIPI_I3C_HCI is not set
# CONFIG_SPI is not set
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
CONFIG_PPS_CLIENT_LDISC=m
CONFIG_PPS_CLIENT_PARPORT=m
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# CONFIG_PTP_1588_CLOCK_PCH is not set
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_VMW is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
CONFIG_PINCTRL_AXP209=m
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_EQUILIBRIUM=m
# CONFIG_PINCTRL_MAX77620 is not set
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
CONFIG_PINCTRL_OCELOT=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_STMFX=m
CONFIG_PINCTRL_SX150X=y
CONFIG_PINCTRL_MADERA=m
CONFIG_PINCTRL_CS47L90=y

#
# Intel pinctrl drivers
#
# CONFIG_PINCTRL_BAYTRAIL is not set
# CONFIG_PINCTRL_CHERRYVIEW is not set
# CONFIG_PINCTRL_LYNXPOINT is not set
# CONFIG_PINCTRL_ALDERLAKE is not set
# CONFIG_PINCTRL_BROXTON is not set
# CONFIG_PINCTRL_CANNONLAKE is not set
# CONFIG_PINCTRL_CEDARFORK is not set
# CONFIG_PINCTRL_DENVERTON is not set
# CONFIG_PINCTRL_ELKHARTLAKE is not set
# CONFIG_PINCTRL_EMMITSBURG is not set
# CONFIG_PINCTRL_GEMINILAKE is not set
# CONFIG_PINCTRL_ICELAKE is not set
# CONFIG_PINCTRL_JASPERLAKE is not set
# CONFIG_PINCTRL_LAKEFIELD is not set
# CONFIG_PINCTRL_LEWISBURG is not set
# CONFIG_PINCTRL_METEORLAKE is not set
# CONFIG_PINCTRL_SUNRISEPOINT is not set
# CONFIG_PINCTRL_TIGERLAKE is not set
# end of Intel pinctrl drivers

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers
#
CONFIG_GPIO_74XX_MMIO=y
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
CONFIG_GPIO_EXAR=m
CONFIG_GPIO_FTGPIO010=y
CONFIG_GPIO_GENERIC_PLATFORM=m
CONFIG_GPIO_GRGPIO=y
CONFIG_GPIO_HLWD=y
CONFIG_GPIO_LOGICVC=y
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
# CONFIG_GPIO_VX855 is not set
CONFIG_GPIO_XILINX=y
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# Port-mapped I/O GPIO drivers
#
CONFIG_GPIO_F7188X=m
CONFIG_GPIO_IT87=y
# CONFIG_GPIO_SCH is not set
CONFIG_GPIO_SCH311X=y
CONFIG_GPIO_WINBOND=m
CONFIG_GPIO_WS16C48=y
# end of Port-mapped I/O GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADNP=y
# CONFIG_GPIO_FXL6408 is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
CONFIG_GPIO_MAX732X=y
# CONFIG_GPIO_MAX732X_IRQ is not set
# CONFIG_GPIO_PCA953X is not set
CONFIG_GPIO_PCA9570=m
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TPIC2810=y
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# CONFIG_GPIO_ADP5520 is not set
# CONFIG_GPIO_BD71815 is not set
CONFIG_GPIO_BD71828=m
CONFIG_GPIO_CS5535=m
CONFIG_GPIO_DA9055=y
CONFIG_GPIO_DLN2=m
# CONFIG_GPIO_ELKHARTLAKE is not set
# CONFIG_GPIO_JANZ_TTL is not set
CONFIG_GPIO_LP3943=y
CONFIG_GPIO_LP873X=m
CONFIG_GPIO_MADERA=m
CONFIG_GPIO_MAX77620=m
CONFIG_GPIO_MAX77650=m
# CONFIG_GPIO_TC3589X is not set
CONFIG_GPIO_TPS65086=m
CONFIG_GPIO_TPS65218=y
# CONFIG_GPIO_TPS6586X is not set
CONFIG_GPIO_TPS65912=m
# CONFIG_GPIO_TQMX86 is not set
CONFIG_GPIO_TWL6040=y
CONFIG_GPIO_WM8994=y
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_AMD8111 is not set
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_ML_IOH is not set
CONFIG_GPIO_PCH=y
# CONFIG_GPIO_PCI_IDIO_16 is not set
CONFIG_GPIO_PCIE_IDIO_24=y
# CONFIG_GPIO_RDC321X is not set
CONFIG_GPIO_SODAVILLE=y
# end of PCI GPIO expanders

#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=m
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=y
# CONFIG_GPIO_LATCH is not set
CONFIG_GPIO_MOCKUP=y
# CONFIG_GPIO_VIRTIO is not set
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers

CONFIG_W1=m

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
# CONFIG_W1_MASTER_GPIO is not set
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
# CONFIG_W1_SLAVE_DS2408_READBACK is not set
# CONFIG_W1_SLAVE_DS2413 is not set
CONFIG_W1_SLAVE_DS2406=m
# CONFIG_W1_SLAVE_DS2423 is not set
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
# CONFIG_W1_SLAVE_DS2433 is not set
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_POWER_SUPPLY_HWMON is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_MAX8925_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_BATTERY_88PM860X is not set
CONFIG_CHARGER_ADP5061=m
CONFIG_BATTERY_CW2015=y
CONFIG_BATTERY_DS2760=m
CONFIG_BATTERY_DS2780=m
# CONFIG_BATTERY_DS2781 is not set
CONFIG_BATTERY_DS2782=y
CONFIG_BATTERY_OLPC=m
# CONFIG_BATTERY_SAMSUNG_SDI is not set
CONFIG_BATTERY_SBS=y
CONFIG_CHARGER_SBS=m
CONFIG_MANAGER_SBS=m
CONFIG_BATTERY_BQ27XXX=y
# CONFIG_BATTERY_BQ27XXX_I2C is not set
CONFIG_BATTERY_BQ27XXX_HDQ=m
CONFIG_BATTERY_DA9030=m
CONFIG_BATTERY_DA9150=m
CONFIG_AXP20X_POWER=m
CONFIG_AXP288_FUEL_GAUGE=m
# CONFIG_BATTERY_MAX17040 is not set
CONFIG_BATTERY_MAX17042=m
CONFIG_BATTERY_MAX1721X=m
CONFIG_CHARGER_PCF50633=m
CONFIG_CHARGER_ISP1704=m
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MANAGER=y
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_LTC4162L is not set
CONFIG_CHARGER_MAX14577=m
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
CONFIG_CHARGER_MAX77650=m
CONFIG_CHARGER_MAX77693=m
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_MAX8998 is not set
# CONFIG_CHARGER_MT6360 is not set
CONFIG_CHARGER_BQ2415X=y
CONFIG_CHARGER_BQ24190=m
CONFIG_CHARGER_BQ24257=y
CONFIG_CHARGER_BQ24735=y
# CONFIG_CHARGER_BQ2515X is not set
CONFIG_CHARGER_BQ25890=m
CONFIG_CHARGER_BQ25980=m
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_CHARGER_SMB347=m
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
CONFIG_BATTERY_GOLDFISH=y
# CONFIG_BATTERY_RT5033 is not set
CONFIG_CHARGER_RT9455=m
# CONFIG_CHARGER_RT9467 is not set
# CONFIG_CHARGER_RT9471 is not set
CONFIG_CHARGER_UCS1002=y
CONFIG_CHARGER_BD99954=y
# CONFIG_RN5T618_POWER is not set
# CONFIG_BATTERY_UG3105 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_ABITUGURU is not set
CONFIG_SENSORS_ABITUGURU3=m
CONFIG_SENSORS_AD7414=m
# CONFIG_SENSORS_AD7418 is not set
CONFIG_SENSORS_ADM1021=m
CONFIG_SENSORS_ADM1025=y
# CONFIG_SENSORS_ADM1026 is not set
CONFIG_SENSORS_ADM1029=m
# CONFIG_SENSORS_ADM1031 is not set
CONFIG_SENSORS_ADM1177=y
# CONFIG_SENSORS_ADM9240 is not set
CONFIG_SENSORS_ADT7X10=m
CONFIG_SENSORS_ADT7410=m
CONFIG_SENSORS_ADT7411=m
CONFIG_SENSORS_ADT7462=y
CONFIG_SENSORS_ADT7470=y
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AHT10 is not set
CONFIG_SENSORS_AS370=m
CONFIG_SENSORS_ASC7621=y
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_K8TEMP=m
CONFIG_SENSORS_APPLESMC=m
CONFIG_SENSORS_ASB100=y
CONFIG_SENSORS_ATXP1=m
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DS620 is not set
CONFIG_SENSORS_DS1621=y
CONFIG_SENSORS_DELL_SMM=y
# CONFIG_I8K is not set
CONFIG_SENSORS_DA9055=y
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
CONFIG_SENSORS_F71882FG=y
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FSCHMD is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_HIH6130=y
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_I5500=m
CONFIG_SENSORS_CORETEMP=y
# CONFIG_SENSORS_IT87 is not set
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_POWR1220=y
CONFIG_SENSORS_LINEAGE=y
# CONFIG_SENSORS_LTC2945 is not set
CONFIG_SENSORS_LTC2947=m
CONFIG_SENSORS_LTC2947_I2C=m
CONFIG_SENSORS_LTC2990=m
# CONFIG_SENSORS_LTC2992 is not set
# CONFIG_SENSORS_LTC4151 is not set
CONFIG_SENSORS_LTC4215=y
# CONFIG_SENSORS_LTC4222 is not set
CONFIG_SENSORS_LTC4245=y
# CONFIG_SENSORS_LTC4260 is not set
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX127 is not set
CONFIG_SENSORS_MAX16065=y
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=y
# CONFIG_SENSORS_MAX197 is not set
CONFIG_SENSORS_MAX31730=y
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_SENSORS_MAX6620 is not set
CONFIG_SENSORS_MAX6621=y
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
CONFIG_SENSORS_MAX6697=y
CONFIG_SENSORS_MAX31790=y
# CONFIG_SENSORS_MC34VR500 is not set
CONFIG_SENSORS_MCP3021=y
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
CONFIG_SENSORS_MENF21BMC_HWMON=m
CONFIG_SENSORS_MR75203=m
# CONFIG_SENSORS_LM63 is not set
CONFIG_SENSORS_LM73=y
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
CONFIG_SENSORS_LM87=y
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=y
# CONFIG_SENSORS_PC87360 is not set
CONFIG_SENSORS_PC87427=y
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775_CORE=y
CONFIG_SENSORS_NCT6775=y
# CONFIG_SENSORS_NCT6775_I2C is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_OXP is not set
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ACBEL_FSG032 is not set
CONFIG_SENSORS_ADM1266=y
CONFIG_SENSORS_ADM1275=m
CONFIG_SENSORS_BEL_PFE=y
# CONFIG_SENSORS_BPA_RS600 is not set
# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
# CONFIG_SENSORS_FSP_3Y is not set
CONFIG_SENSORS_IBM_CFFPS=m
# CONFIG_SENSORS_DPS920AB is not set
CONFIG_SENSORS_INSPUR_IPSPS=m
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR36021 is not set
# CONFIG_SENSORS_IR38064 is not set
CONFIG_SENSORS_IRPS5401=m
CONFIG_SENSORS_ISL68137=m
CONFIG_SENSORS_LM25066=y
# CONFIG_SENSORS_LM25066_REGULATOR is not set
# CONFIG_SENSORS_LT7182S is not set
CONFIG_SENSORS_LTC2978=y
# CONFIG_SENSORS_LTC2978_REGULATOR is not set
# CONFIG_SENSORS_LTC3815 is not set
# CONFIG_SENSORS_MAX15301 is not set
CONFIG_SENSORS_MAX16064=y
CONFIG_SENSORS_MAX16601=y
CONFIG_SENSORS_MAX20730=m
CONFIG_SENSORS_MAX20751=y
CONFIG_SENSORS_MAX31785=y
CONFIG_SENSORS_MAX34440=y
CONFIG_SENSORS_MAX8688=m
# CONFIG_SENSORS_MP2888 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_MP5023 is not set
# CONFIG_SENSORS_MPQ7932 is not set
# CONFIG_SENSORS_PIM4328 is not set
# CONFIG_SENSORS_PLI1209BC is not set
# CONFIG_SENSORS_PM6764TR is not set
CONFIG_SENSORS_PXE1610=m
# CONFIG_SENSORS_Q54SJ108A2 is not set
# CONFIG_SENSORS_STPDDC60 is not set
# CONFIG_SENSORS_TDA38640 is not set
CONFIG_SENSORS_TPS40422=y
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_TPS546D24 is not set
CONFIG_SENSORS_UCD9000=y
CONFIG_SENSORS_UCD9200=m
# CONFIG_SENSORS_XDPE152 is not set
# CONFIG_SENSORS_XDPE122 is not set
CONFIG_SENSORS_ZL6100=y
# CONFIG_SENSORS_PWM_FAN is not set
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
CONFIG_SENSORS_SHT15=m
CONFIG_SENSORS_SHT21=y
CONFIG_SENSORS_SHT3x=y
# CONFIG_SENSORS_SHT4x is not set
CONFIG_SENSORS_SHTC1=y
CONFIG_SENSORS_SIS5595=y
CONFIG_SENSORS_DME1737=y
CONFIG_SENSORS_EMC1403=y
CONFIG_SENSORS_EMC2103=m
# CONFIG_SENSORS_EMC2305 is not set
# CONFIG_SENSORS_EMC6W201 is not set
CONFIG_SENSORS_SMSC47M1=m
CONFIG_SENSORS_SMSC47M192=m
CONFIG_SENSORS_SMSC47B397=m
# CONFIG_SENSORS_STTS751 is not set
CONFIG_SENSORS_SMM665=y
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
CONFIG_SENSORS_INA2XX=y
# CONFIG_SENSORS_INA238 is not set
CONFIG_SENSORS_INA3221=m
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
CONFIG_SENSORS_TMP401=y
CONFIG_SENSORS_TMP421=y
# CONFIG_SENSORS_TMP464 is not set
CONFIG_SENSORS_TMP513=y
CONFIG_SENSORS_VIA_CPUTEMP=y
CONFIG_SENSORS_VIA686A=m
CONFIG_SENSORS_VT1211=y
CONFIG_SENSORS_VT8231=y
CONFIG_SENSORS_W83773G=y
CONFIG_SENSORS_W83781D=y
CONFIG_SENSORS_W83791D=m
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=m
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
CONFIG_SENSORS_W83L786NG=m
CONFIG_SENSORS_W83627HF=y
CONFIG_SENSORS_W83627EHF=m

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
# CONFIG_SENSORS_ATK0110 is not set
# CONFIG_SENSORS_ASUS_WMI is not set
# CONFIG_SENSORS_ASUS_EC is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
CONFIG_THERMAL_STATISTICS=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_ACPI=y
# CONFIG_THERMAL_WRITABLE_TRIPS is not set
# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE=y
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
# CONFIG_THERMAL_GOV_STEP_WISE is not set
CONFIG_THERMAL_GOV_BANG_BANG=y
# CONFIG_THERMAL_GOV_USER_SPACE is not set
CONFIG_CPU_THERMAL=y
# CONFIG_CPU_FREQ_THERMAL is not set
CONFIG_THERMAL_EMULATION=y
CONFIG_THERMAL_MMIO=y
CONFIG_MAX77620_THERMAL=y

#
# Intel thermal drivers
#
# CONFIG_INTEL_SOC_DTS_THERMAL is not set

#
# ACPI INT340X thermal drivers
#
# end of ACPI INT340X thermal drivers

CONFIG_INTEL_PCH_THERMAL=y
# CONFIG_INTEL_TCC_COOLING is not set
# end of Intel thermal drivers

CONFIG_GENERIC_ADC_THERMAL=m
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
# CONFIG_SSB_PCIHOST is not set
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_CS5535=m
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
CONFIG_PMIC_ADP5520=y
# CONFIG_MFD_AAT2870_CORE is not set
CONFIG_MFD_ATMEL_FLEXCOM=m
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_MADERA=m
# CONFIG_MFD_MADERA_I2C is not set
# CONFIG_MFD_MAX597X is not set
# CONFIG_MFD_CS47L15 is not set
# CONFIG_MFD_CS47L35 is not set
# CONFIG_MFD_CS47L85 is not set
CONFIG_MFD_CS47L90=y
# CONFIG_MFD_CS47L92 is not set
CONFIG_PMIC_DA903X=y
# CONFIG_MFD_DA9052_I2C is not set
CONFIG_MFD_DA9055=y
# CONFIG_MFD_DA9062 is not set
CONFIG_MFD_DA9063=y
CONFIG_MFD_DA9150=m
CONFIG_MFD_DLN2=m
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_I2C is not set
CONFIG_MFD_MP2629=y
CONFIG_MFD_HI6421_PMIC=y
# CONFIG_MFD_HI6421_SPMI is not set
CONFIG_MFD_INTEL_QUARK_I2C_GPIO=y
# CONFIG_LPC_ICH is not set
CONFIG_LPC_SCH=y
CONFIG_MFD_INTEL_LPSS=y
# CONFIG_MFD_INTEL_LPSS_ACPI is not set
CONFIG_MFD_INTEL_LPSS_PCI=y
# CONFIG_MFD_INTEL_PMC_BXT is not set
# CONFIG_MFD_IQS62X is not set
CONFIG_MFD_JANZ_CMODIO=m
# CONFIG_MFD_KEMPLD is not set
CONFIG_MFD_88PM800=m
# CONFIG_MFD_88PM805 is not set
CONFIG_MFD_88PM860X=y
CONFIG_MFD_MAX14577=m
CONFIG_MFD_MAX77620=y
CONFIG_MFD_MAX77650=m
CONFIG_MFD_MAX77686=m
CONFIG_MFD_MAX77693=m
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
CONFIG_MFD_MAX8907=y
CONFIG_MFD_MAX8925=y
# CONFIG_MFD_MAX8997 is not set
CONFIG_MFD_MAX8998=y
CONFIG_MFD_MT6360=y
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
CONFIG_MFD_MENF21BMC=m
CONFIG_MFD_VIPERBOARD=m
# CONFIG_MFD_NTXEC is not set
CONFIG_MFD_RETU=m
CONFIG_MFD_PCF50633=m
CONFIG_PCF50633_ADC=m
# CONFIG_PCF50633_GPIO is not set
# CONFIG_MFD_SY7636A is not set
CONFIG_MFD_RDC321X=m
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_RK808 is not set
CONFIG_MFD_RN5T618=y
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_SI476X_CORE=y
CONFIG_MFD_SM501=m
CONFIG_MFD_SM501_GPIO=y
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
CONFIG_MFD_TI_AM335X_TSCADC=m
CONFIG_MFD_LP3943=y
# CONFIG_MFD_LP8788 is not set
CONFIG_MFD_TI_LMU=m
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
CONFIG_TPS6507X=m
CONFIG_MFD_TPS65086=m
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
CONFIG_MFD_TI_LP873X=m
# CONFIG_MFD_TI_LP87565 is not set
CONFIG_MFD_TPS65218=y
# CONFIG_MFD_TPS65219 is not set
CONFIG_MFD_TPS6586X=y
# CONFIG_MFD_TPS65910 is not set
CONFIG_MFD_TPS65912=m
CONFIG_MFD_TPS65912_I2C=m
# CONFIG_TWL4030_CORE is not set
CONFIG_TWL6040_CORE=y
CONFIG_MFD_WL1273_CORE=y
CONFIG_MFD_LM3533=y
# CONFIG_MFD_TIMBERDALE is not set
CONFIG_MFD_TC3589X=y
CONFIG_MFD_TQMX86=m
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM8350_I2C is not set
CONFIG_MFD_WM8994=y
CONFIG_MFD_ROHM_BD718XX=y
CONFIG_MFD_ROHM_BD71828=m
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_WCD934X is not set
# CONFIG_MFD_ATC260X_I2C is not set
CONFIG_MFD_QCOM_PM8008=y
# CONFIG_MFD_RSMU_I2C is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
CONFIG_REGULATOR_USERSPACE_CONSUMER=y
# CONFIG_REGULATOR_88PG86X is not set
CONFIG_REGULATOR_88PM800=m
CONFIG_REGULATOR_88PM8607=m
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_AXP20X is not set
# CONFIG_REGULATOR_BD71815 is not set
CONFIG_REGULATOR_BD71828=m
# CONFIG_REGULATOR_BD718XX is not set
CONFIG_REGULATOR_DA903X=y
CONFIG_REGULATOR_DA9055=y
CONFIG_REGULATOR_DA9063=y
# CONFIG_REGULATOR_DA9121 is not set
CONFIG_REGULATOR_DA9210=y
# CONFIG_REGULATOR_DA9211 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_FAN53880 is not set
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_HI6421=y
CONFIG_REGULATOR_HI6421V530=m
CONFIG_REGULATOR_ISL9305=y
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LM363X is not set
# CONFIG_REGULATOR_LP3971 is not set
CONFIG_REGULATOR_LP3972=m
CONFIG_REGULATOR_LP872X=y
# CONFIG_REGULATOR_LP873X is not set
CONFIG_REGULATOR_LP8755=m
CONFIG_REGULATOR_LTC3589=y
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX14577 is not set
CONFIG_REGULATOR_MAX1586=y
CONFIG_REGULATOR_MAX77620=m
CONFIG_REGULATOR_MAX77650=m
CONFIG_REGULATOR_MAX8649=m
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
CONFIG_REGULATOR_MAX8907=m
CONFIG_REGULATOR_MAX8925=m
CONFIG_REGULATOR_MAX8952=m
CONFIG_REGULATOR_MAX8973=m
CONFIG_REGULATOR_MAX8998=m
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX20411 is not set
CONFIG_REGULATOR_MAX77686=m
CONFIG_REGULATOR_MAX77693=m
CONFIG_REGULATOR_MAX77802=m
CONFIG_REGULATOR_MAX77826=m
CONFIG_REGULATOR_MCP16502=y
CONFIG_REGULATOR_MP5416=m
# CONFIG_REGULATOR_MP8859 is not set
CONFIG_REGULATOR_MP886X=m
# CONFIG_REGULATOR_MPQ7920 is not set
CONFIG_REGULATOR_MT6311=m
CONFIG_REGULATOR_MT6315=y
CONFIG_REGULATOR_MT6360=m
CONFIG_REGULATOR_PCA9450=y
# CONFIG_REGULATOR_PCF50633 is not set
# CONFIG_REGULATOR_PF8X00 is not set
CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PV88060=m
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=m
# CONFIG_REGULATOR_QCOM_SPMI is not set
CONFIG_REGULATOR_QCOM_USB_VBUS=m
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RN5T618=m
CONFIG_REGULATOR_ROHM=m
CONFIG_REGULATOR_RT4801=m
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5739 is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6190 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_S2MPA01 is not set
# CONFIG_REGULATOR_S2MPS11 is not set
CONFIG_REGULATOR_S5M8767=m
CONFIG_REGULATOR_SLG51000=m
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
CONFIG_REGULATOR_SY8827N=m
CONFIG_REGULATOR_TPS51632=y
CONFIG_REGULATOR_TPS62360=m
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65086 is not set
CONFIG_REGULATOR_TPS65132=m
# CONFIG_REGULATOR_TPS65218 is not set
CONFIG_REGULATOR_TPS6586X=y
CONFIG_REGULATOR_TPS65912=m
CONFIG_REGULATOR_VCTRL=m
CONFIG_REGULATOR_WM8994=m
CONFIG_REGULATOR_QCOM_LABIBB=m
# CONFIG_RC_CORE is not set
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=y
CONFIG_CEC_SECO=m
CONFIG_USB_PULSE8_CEC=m
# CONFIG_USB_RAINSHADOW_CEC is not set
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_SUPPORT_FILTER is not set
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types

#
# Media core support
#
CONFIG_VIDEO_DEV=m
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=y
# end of Media core support

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_MEM2MEM_DEV=m
CONFIG_V4L2_FLASH_LED_CLASS=m
CONFIG_V4L2_FWNODE=m
CONFIG_V4L2_ASYNC=m
# end of Video4Linux options

#
# Media controller options
#
# CONFIG_MEDIA_CONTROLLER_DVB is not set
# end of Media controller options

#
# Digital TV options
#
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=16
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
CONFIG_DVB_ULE_DEBUG=y
# end of Digital TV options

#
# Media drivers
#

#
# Media drivers
#
# CONFIG_MEDIA_USB_SUPPORT is not set
CONFIG_MEDIA_PCI_SUPPORT=y

#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=m
# CONFIG_VIDEO_TW5864 is not set
# CONFIG_VIDEO_TW68 is not set
CONFIG_VIDEO_TW686X=m
# CONFIG_VIDEO_ZORAN is not set

#
# Media capture/analog TV support
#
# CONFIG_VIDEO_DT3155 is not set
# CONFIG_VIDEO_HEXIUM_GEMINI is not set
# CONFIG_VIDEO_HEXIUM_ORION is not set
CONFIG_VIDEO_MXB=m

#
# Media capture/analog/hybrid TV support
#
CONFIG_VIDEO_CX25821=m
CONFIG_VIDEO_CX25821_ALSA=m
# CONFIG_VIDEO_SAA7134 is not set
CONFIG_VIDEO_SAA7164=m

#
# Media digital TV PCI Adapters
#
# CONFIG_DVB_B2C2_FLEXCOP_PCI is not set
CONFIG_DVB_DDBRIDGE=y
CONFIG_DVB_DDBRIDGE_MSIENABLE=y
# CONFIG_DVB_NGENE is not set
CONFIG_DVB_PLUTO2=y
CONFIG_DVB_PT1=y
# CONFIG_DVB_PT3 is not set
# CONFIG_DVB_BUDGET_CORE is not set
# CONFIG_VIDEO_IPU3_CIO2 is not set
CONFIG_RADIO_ADAPTERS=m
CONFIG_RADIO_MAXIRADIO=m
# CONFIG_RADIO_SAA7706H is not set
CONFIG_RADIO_SHARK=m
# CONFIG_RADIO_SHARK2 is not set
CONFIG_RADIO_SI4713=m
CONFIG_RADIO_TEA575X=m
# CONFIG_RADIO_TEA5764 is not set
CONFIG_RADIO_TEF6862=m
# CONFIG_RADIO_WL1273 is not set
# CONFIG_USB_DSBR is not set
CONFIG_USB_KEENE=m
# CONFIG_USB_MA901 is not set
CONFIG_USB_MR800=m
CONFIG_USB_RAREMONO=m
# CONFIG_RADIO_SI470X is not set
# CONFIG_USB_SI4713 is not set
CONFIG_PLATFORM_SI4713=m
CONFIG_I2C_SI4713=m
CONFIG_MEDIA_PLATFORM_DRIVERS=y
# CONFIG_V4L_PLATFORM_DRIVERS is not set
# CONFIG_SDR_PLATFORM_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#

#
# Mediatek media platform drivers
#

#
# Microchip Technology, Inc. media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_TEST_DRIVERS is not set

#
# FireWire (IEEE 1394) Adapters
#
CONFIG_DVB_FIREDTV=m
CONFIG_DVB_FIREDTV_INPUT=y
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEO_SAA7146=m
CONFIG_VIDEO_SAA7146_VV=m
CONFIG_VIDEOBUF2_CORE=m
CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=m
CONFIG_VIDEOBUF2_DMA_SG=m
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y

#
# Camera sensor devices
#
# CONFIG_VIDEO_AR0521 is not set
CONFIG_VIDEO_HI556=m
# CONFIG_VIDEO_HI846 is not set
# CONFIG_VIDEO_HI847 is not set
# CONFIG_VIDEO_IMX208 is not set
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX274=m
# CONFIG_VIDEO_IMX290 is not set
# CONFIG_VIDEO_IMX296 is not set
CONFIG_VIDEO_IMX319=m
# CONFIG_VIDEO_IMX334 is not set
# CONFIG_VIDEO_IMX335 is not set
# CONFIG_VIDEO_IMX355 is not set
# CONFIG_VIDEO_IMX412 is not set
# CONFIG_VIDEO_IMX415 is not set
CONFIG_VIDEO_MAX9271_LIB=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M111=m
# CONFIG_VIDEO_MT9P031 is not set
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
# CONFIG_VIDEO_OG01A1B is not set
CONFIG_VIDEO_OV02A10=m
# CONFIG_VIDEO_OV08D10 is not set
# CONFIG_VIDEO_OV08X40 is not set
CONFIG_VIDEO_OV13858=m
# CONFIG_VIDEO_OV13B10 is not set
# CONFIG_VIDEO_OV2640 is not set
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
# CONFIG_VIDEO_OV2740 is not set
# CONFIG_VIDEO_OV4689 is not set
# CONFIG_VIDEO_OV5640 is not set
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
# CONFIG_VIDEO_OV5693 is not set
# CONFIG_VIDEO_OV5695 is not set
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7740=m
# CONFIG_VIDEO_OV8856 is not set
# CONFIG_VIDEO_OV9282 is not set
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
# CONFIG_VIDEO_OV9734 is not set
CONFIG_VIDEO_RDACM20=m
# CONFIG_VIDEO_RDACM21 is not set
CONFIG_VIDEO_RJ54N1=m
# CONFIG_VIDEO_S5K5BAF is not set
CONFIG_VIDEO_S5K6A3=m
# CONFIG_VIDEO_ST_VGXY61 is not set
# CONFIG_VIDEO_CCS is not set
CONFIG_VIDEO_ET8EK8=m
# end of Camera sensor devices

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_DW9714=m
CONFIG_VIDEO_DW9768=m
# CONFIG_VIDEO_DW9807_VCM is not set
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
# CONFIG_VIDEO_LM3646 is not set
# end of Flash devices

#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_CS3308 is not set
# CONFIG_VIDEO_CS5345 is not set
# CONFIG_VIDEO_CS53L32A is not set
CONFIG_VIDEO_MSP3400=m
# CONFIG_VIDEO_SONY_BTF_MPX is not set
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_TVAUDIO=m
# CONFIG_VIDEO_UDA1342 is not set
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
# CONFIG_VIDEO_WM8775 is not set
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_ADV7183 is not set
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=m
# CONFIG_VIDEO_ADV7842_CEC is not set
CONFIG_VIDEO_BT819=m
# CONFIG_VIDEO_BT856 is not set
CONFIG_VIDEO_BT866=m
# CONFIG_VIDEO_ISL7998X is not set
# CONFIG_VIDEO_KS0127 is not set
CONFIG_VIDEO_MAX9286=m
# CONFIG_VIDEO_ML86V7667 is not set
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
# CONFIG_VIDEO_TC358743 is not set
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
# CONFIG_VIDEO_TW9903 is not set
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m

#
# Video and audio decoders
#
# CONFIG_VIDEO_SAA717X is not set
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_ADV7170=m
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_ADV7393 is not set
# CONFIG_VIDEO_AK881X is not set
# CONFIG_VIDEO_SAA7127 is not set
CONFIG_VIDEO_SAA7185=m
# CONFIG_VIDEO_THS8200 is not set
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
# CONFIG_VIDEO_UPD64083 is not set
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
CONFIG_SDR_MAX2175=m
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_I2C is not set
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_ST_MIPID02=m
# CONFIG_VIDEO_THS7303 is not set
# end of Miscellaneous helper chips

CONFIG_MEDIA_TUNER=y

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
# CONFIG_MEDIA_TUNER_FC2580 is not set
# CONFIG_MEDIA_TUNER_IT913X is not set
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_MAX2165=y
CONFIG_MEDIA_TUNER_MC44S803=y
# CONFIG_MEDIA_TUNER_MT2060 is not set
CONFIG_MEDIA_TUNER_MT2063=y
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_MT2131=y
# CONFIG_MEDIA_TUNER_MT2266 is not set
CONFIG_MEDIA_TUNER_MXL301RF=y
CONFIG_MEDIA_TUNER_MXL5005S=y
CONFIG_MEDIA_TUNER_MXL5007T=y
CONFIG_MEDIA_TUNER_QM1D1B0004=y
CONFIG_MEDIA_TUNER_QM1D1C0042=y
CONFIG_MEDIA_TUNER_QT1010=y
# CONFIG_MEDIA_TUNER_R820T is not set
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA18212=y
CONFIG_MEDIA_TUNER_TDA18218=m
# CONFIG_MEDIA_TUNER_TDA18250 is not set
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_XC2028=y
CONFIG_MEDIA_TUNER_XC4000=y
CONFIG_MEDIA_TUNER_XC5000=y
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
CONFIG_DVB_M88DS3103=m
CONFIG_DVB_MXL5XX=y
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=y
CONFIG_DVB_STV0910=y
CONFIG_DVB_STV6110x=y
CONFIG_DVB_STV6111=y

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=y
CONFIG_DVB_MN88472=y
CONFIG_DVB_MN88473=m
# CONFIG_DVB_SI2165 is not set
CONFIG_DVB_TDA18271C2DD=y

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
# CONFIG_DVB_CX24116 is not set
# CONFIG_DVB_CX24117 is not set
CONFIG_DVB_CX24120=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_DS3000=y
CONFIG_DVB_MB86A16=y
# CONFIG_DVB_MT312 is not set
# CONFIG_DVB_S5H1420 is not set
CONFIG_DVB_SI21XX=y
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0288=y
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV0900=y
CONFIG_DVB_STV6110=y
CONFIG_DVB_TDA10071=m
# CONFIG_DVB_TDA10086 is not set
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_TDA826X=m
# CONFIG_DVB_TS2020 is not set
CONFIG_DVB_TUA6100=y
# CONFIG_DVB_TUNER_CX24113 is not set
CONFIG_DVB_TUNER_ITD1000=y
CONFIG_DVB_VES1X93=m
# CONFIG_DVB_ZL10036 is not set
CONFIG_DVB_ZL10039=y

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_AF9013=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=y
# CONFIG_DVB_CXD2820R is not set
CONFIG_DVB_CXD2841ER=y
# CONFIG_DVB_DIB3000MB is not set
# CONFIG_DVB_DIB3000MC is not set
# CONFIG_DVB_DIB7000M is not set
CONFIG_DVB_DIB7000P=m
# CONFIG_DVB_DIB9000 is not set
CONFIG_DVB_DRXD=y
CONFIG_DVB_EC100=m
CONFIG_DVB_L64781=y
CONFIG_DVB_MT352=y
CONFIG_DVB_NXT6000=y
# CONFIG_DVB_RTL2830 is not set
# CONFIG_DVB_RTL2832 is not set
# CONFIG_DVB_RTL2832_SDR is not set
# CONFIG_DVB_S5H1432 is not set
# CONFIG_DVB_SI2168 is not set
CONFIG_DVB_SP887X=m
CONFIG_DVB_STV0367=y
CONFIG_DVB_TDA10048=m
CONFIG_DVB_TDA1004X=y
# CONFIG_DVB_ZD1301_DEMOD is not set
# CONFIG_DVB_ZL10353 is not set

#
# DVB-C (cable) frontends
#
CONFIG_DVB_STV0297=m
CONFIG_DVB_TDA10021=y
CONFIG_DVB_TDA10023=y
# CONFIG_DVB_VES1820 is not set

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
# CONFIG_DVB_BCM3510 is not set
# CONFIG_DVB_LG2160 is not set
# CONFIG_DVB_LGDT3305 is not set
# CONFIG_DVB_LGDT3306A is not set
CONFIG_DVB_LGDT330X=m
# CONFIG_DVB_MXL692 is not set
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_S5H1411=m

#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_DIB8000=y
# CONFIG_DVB_MB86A20S is not set
CONFIG_DVB_S921=y

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
# CONFIG_DVB_MN88443X is not set
CONFIG_DVB_TC90522=y

#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=y
CONFIG_DVB_TUNER_DIB0070=m
# CONFIG_DVB_TUNER_DIB0090 is not set

#
# SEC control devices for DVB-S
#
# CONFIG_DVB_A8293 is not set
CONFIG_DVB_AF9033=y
CONFIG_DVB_ASCOT2E=y
CONFIG_DVB_ATBM8830=m
# CONFIG_DVB_HELENE is not set
CONFIG_DVB_HORUS3A=y
CONFIG_DVB_ISL6405=y
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_IX2505V=m
CONFIG_DVB_LGS8GL5=m
# CONFIG_DVB_LGS8GXX is not set
CONFIG_DVB_LNBH25=y
CONFIG_DVB_LNBH29=y
CONFIG_DVB_LNBP21=y
# CONFIG_DVB_LNBP22 is not set
CONFIG_DVB_M88RS2000=y
# CONFIG_DVB_TDA665x is not set
# CONFIG_DVB_DRX39XYJ is not set

#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=y
CONFIG_DVB_SP2=y
# end of Customise DVB Frontends

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=m
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_VIDEO_CMDLINE=y
CONFIG_VIDEO_NOMODESET=y
# CONFIG_AGP is not set
CONFIG_INTEL_GTT=y
# CONFIG_VGA_SWITCHEROO is not set
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_DEBUG_MM=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
CONFIG_DRM_DEBUG_MODESET_LOCK=y
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDCP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DP_AUX_CHARDEV=y
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=y
CONFIG_DRM_BUDDY=y
CONFIG_DRM_VRAM_HELPER=m
CONFIG_DRM_TTM_HELPER=y
CONFIG_DRM_GEM_DMA_HELPER=m
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_SCHED=y

#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=m
CONFIG_DRM_I2C_SIL164=m
# CONFIG_DRM_I2C_NXP_TDA998X is not set
CONFIG_DRM_I2C_NXP_TDA9950=m
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_KOMEDA=m
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_I915=y
CONFIG_DRM_I915_FORCE_PROBE=""
CONFIG_DRM_I915_CAPTURE_ERROR=y
# CONFIG_DRM_I915_COMPRESS_ERROR is not set
CONFIG_DRM_I915_USERPTR=y
# CONFIG_DRM_I915_PXP is not set

#
# drm/i915 Debugging
#
CONFIG_DRM_I915_WERROR=y
# CONFIG_DRM_I915_DEBUG is not set
CONFIG_DRM_I915_DEBUG_MMIO=y
CONFIG_DRM_I915_DEBUG_GEM=y
CONFIG_DRM_I915_DEBUG_GEM_ONCE=y
CONFIG_DRM_I915_ERRLOG_GEM=y
# CONFIG_DRM_I915_TRACE_GEM is not set
# CONFIG_DRM_I915_TRACE_GTT is not set
CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS=y
CONFIG_DRM_I915_SW_FENCE_CHECK_DAG=y
# CONFIG_DRM_I915_DEBUG_GUC is not set
# CONFIG_DRM_I915_SELFTEST is not set
# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
CONFIG_DRM_I915_DEBUG_RUNTIME_PM=y
# end of drm/i915 Debugging

#
# drm/i915 Profile Guided Optimisation
#
CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
CONFIG_DRM_I915_FENCE_TIMEOUT=10000
CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500
CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
CONFIG_DRM_I915_STOP_TIMEOUT=100
CONFIG_DRM_I915_TIMESLICE_DURATION=1
# end of drm/i915 Profile Guided Optimisation

CONFIG_DRM_VGEM=y
CONFIG_DRM_VKMS=y
CONFIG_DRM_VMWGFX=y
# CONFIG_DRM_VMWGFX_MKSSTATS is not set
CONFIG_DRM_GMA500=m
CONFIG_DRM_UDL=m
CONFIG_DRM_AST=m
# CONFIG_DRM_MGAG200 is not set
CONFIG_DRM_QXL=m
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ARM_VERSATILE=y
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
CONFIG_DRM_PANEL_BOE_HIMAX8279D=y
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y
CONFIG_DRM_PANEL_DSI_CM=m
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_EBBG_FT8719 is not set
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
# CONFIG_DRM_PANEL_JDI_R63452 is not set
CONFIG_DRM_PANEL_KHADAS_TS050=y
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=y
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=y
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=y
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=y
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=y
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=y
CONFIG_DRM_PANEL_RAYDIUM_RM68200=y
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=y
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
CONFIG_DRM_PANEL_TDO_TL070WSH30=y
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
CONFIG_DRM_CHIPONE_ICN6211=y
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
# CONFIG_DRM_ITE_IT6505 is not set
CONFIG_DRM_LONTIUM_LT8912B=y
# CONFIG_DRM_LONTIUM_LT9211 is not set
CONFIG_DRM_LONTIUM_LT9611=y
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
CONFIG_DRM_ITE_IT66121=y
CONFIG_DRM_LVDS_CODEC=y
CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=y
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_NXP_PTN3460=y
CONFIG_DRM_PARADE_PS8622=m
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SAMSUNG_DSIM is not set
# CONFIG_DRM_SIL_SII8620 is not set
CONFIG_DRM_SII902X=m
CONFIG_DRM_SII9234=m
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_THINE_THC63LVD1024=y
CONFIG_DRM_TOSHIBA_TC358762=m
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
CONFIG_DRM_TOSHIBA_TC358768=m
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
# CONFIG_DRM_TI_TFP410 is not set
CONFIG_DRM_TI_SN65DSI83=y
# CONFIG_DRM_TI_SN65DSI86 is not set
CONFIG_DRM_TI_TPD12S015=y
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
CONFIG_DRM_ANALOGIX_ANX78XX=y
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_CEC=y
# CONFIG_DRM_CDNS_DSI is not set
CONFIG_DRM_CDNS_MHDP8546=y
# end of Display Interface Bridges

CONFIG_DRM_ETNAVIV=y
CONFIG_DRM_ETNAVIV_THERMAL=y
# CONFIG_DRM_LOGICVC is not set
CONFIG_DRM_ARCPGU=m
# CONFIG_DRM_BOCHS is not set
CONFIG_DRM_CIRRUS_QEMU=m
CONFIG_DRM_GM12U320=m
CONFIG_DRM_SIMPLEDRM=y
CONFIG_DRM_VBOXVIDEO=m
CONFIG_DRM_GUD=m
# CONFIG_DRM_SSD130X is not set
CONFIG_DRM_LEGACY=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB_NOTIFY=y
CONFIG_FB=m
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_DDC=m
CONFIG_FB_CFB_FILLRECT=m
CONFIG_FB_CFB_COPYAREA=m
CONFIG_FB_CFB_IMAGEBLIT=m
CONFIG_FB_SYS_FILLRECT=m
CONFIG_FB_SYS_COPYAREA=m
CONFIG_FB_SYS_IMAGEBLIT=m
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=m
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_HECUBA=m
CONFIG_FB_SVGALIB=m
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y

#
# Frame buffer hardware drivers
#
CONFIG_FB_CIRRUS=m
CONFIG_FB_PM2=m
CONFIG_FB_PM2_FIFO_DISCONNECT=y
CONFIG_FB_CYBER2000=m
# CONFIG_FB_CYBER2000_DDC is not set
CONFIG_FB_ARC=m
# CONFIG_FB_VGA16 is not set
CONFIG_FB_N411=m
CONFIG_FB_HGA=m
# CONFIG_FB_OPENCORES is not set
CONFIG_FB_S1D13XXX=m
CONFIG_FB_NVIDIA=m
# CONFIG_FB_NVIDIA_I2C is not set
CONFIG_FB_NVIDIA_DEBUG=y
CONFIG_FB_NVIDIA_BACKLIGHT=y
CONFIG_FB_RIVA=m
CONFIG_FB_RIVA_I2C=y
CONFIG_FB_RIVA_DEBUG=y
# CONFIG_FB_RIVA_BACKLIGHT is not set
CONFIG_FB_I740=m
# CONFIG_FB_LE80578 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
CONFIG_FB_ATY128=m
CONFIG_FB_ATY128_BACKLIGHT=y
CONFIG_FB_ATY=m
# CONFIG_FB_ATY_CT is not set
CONFIG_FB_ATY_GX=y
CONFIG_FB_ATY_BACKLIGHT=y
CONFIG_FB_S3=m
CONFIG_FB_S3_DDC=y
# CONFIG_FB_SAVAGE is not set
CONFIG_FB_SIS=m
CONFIG_FB_SIS_300=y
# CONFIG_FB_SIS_315 is not set
CONFIG_FB_VIA=m
# CONFIG_FB_VIA_DIRECT_PROCFS is not set
CONFIG_FB_VIA_X_COMPATIBILITY=y
CONFIG_FB_NEOMAGIC=m
CONFIG_FB_KYRO=m
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
CONFIG_FB_VT8623=m
CONFIG_FB_TRIDENT=m
# CONFIG_FB_ARK is not set
CONFIG_FB_PM3=m
CONFIG_FB_CARMINE=m
CONFIG_FB_CARMINE_DRAM_EVAL=y
# CONFIG_CARMINE_DRAM_CUSTOM is not set
CONFIG_FB_GEODE=y
CONFIG_FB_GEODE_LX=m
CONFIG_FB_GEODE_GX=m
CONFIG_FB_GEODE_GX1=m
# CONFIG_FB_SM501 is not set
CONFIG_FB_SMSCUFX=m
CONFIG_FB_UDL=m
# CONFIG_FB_IBM_GXT4500 is not set
CONFIG_FB_GOLDFISH=m
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SSD1307=m
CONFIG_FB_SM712=m
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_KTD253=m
# CONFIG_BACKLIGHT_KTZ8866 is not set
CONFIG_BACKLIGHT_LM3533=m
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_DA903X is not set
CONFIG_BACKLIGHT_MAX8925=y
# CONFIG_BACKLIGHT_APPLE is not set
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_BACKLIGHT_SAHARA=m
CONFIG_BACKLIGHT_ADP5520=y
# CONFIG_BACKLIGHT_ADP8860 is not set
CONFIG_BACKLIGHT_ADP8870=m
CONFIG_BACKLIGHT_88PM860X=m
CONFIG_BACKLIGHT_PCF50633=m
# CONFIG_BACKLIGHT_LM3630A is not set
CONFIG_BACKLIGHT_LM3639=m
CONFIG_BACKLIGHT_LP855X=y
CONFIG_BACKLIGHT_GPIO=y
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
CONFIG_BACKLIGHT_ARCXCNN=m
CONFIG_BACKLIGHT_LED=m
# end of Backlight & LCD device support

CONFIG_VGASTATE=m
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
# CONFIG_LOGO is not set
# end of Graphics support

# CONFIG_DRM_ACCEL is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
# CONFIG_SND_DYNAMIC_MINORS is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_PROC_FS is not set
CONFIG_SND_VERBOSE_PRINTK=y
CONFIG_SND_CTL_FAST_LOOKUP=y
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_VERBOSE=y
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
# CONFIG_SND_CTL_DEBUG is not set
CONFIG_SND_DMA_SGBUF=y
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
# end of HD-Audio

CONFIG_SND_HDA_PREALLOC_SIZE=0
# CONFIG_SND_USB is not set
# CONFIG_SND_FIREWIRE is not set
# CONFIG_SND_SOC is not set
# CONFIG_SND_X86 is not set
# CONFIG_SND_VIRTIO is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=m
# CONFIG_HID_BATTERY_STRENGTH is not set
CONFIG_HIDRAW=y
CONFIG_UHID=m
# CONFIG_HID_GENERIC is not set

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_AUREAL is not set
CONFIG_HID_BELKIN=m
# CONFIG_HID_CHERRY is not set
CONFIG_HID_COUGAR=m
# CONFIG_HID_MACALLY is not set
# CONFIG_HID_CMEDIA is not set
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
# CONFIG_DRAGONRISE_FF is not set
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELECOM=m
# CONFIG_HID_EVISION is not set
CONFIG_HID_EZKEY=m
CONFIG_HID_GEMBIRD=m
# CONFIG_HID_GFRM is not set
CONFIG_HID_GLORIOUS=m
CONFIG_HID_VIVALDI_COMMON=m
CONFIG_HID_VIVALDI=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
# CONFIG_HID_WALTOP is not set
CONFIG_HID_VIEWSONIC=m
# CONFIG_HID_VRC2 is not set
# CONFIG_HID_XIAOMI is not set
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
# CONFIG_HID_TWINHAN is not set
CONFIG_HID_KENSINGTON=m
# CONFIG_HID_LCPOWER is not set
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
# CONFIG_HID_MAGICMOUSE is not set
CONFIG_HID_MALTRON=m
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_REDRAGON is not set
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
# CONFIG_HID_MULTITOUCH is not set
CONFIG_HID_NINTENDO=m
# CONFIG_NINTENDO_FF is not set
# CONFIG_HID_NTI is not set
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
# CONFIG_HID_PETALYNX is not set
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
# CONFIG_HID_PICOLCD_LEDS is not set
CONFIG_HID_PLANTRONICS=m
# CONFIG_HID_PLAYSTATION is not set
# CONFIG_HID_PXRC is not set
# CONFIG_HID_RAZER is not set
CONFIG_HID_PRIMAX=m
CONFIG_HID_SAITEK=m
# CONFIG_HID_SEMITEK is not set
# CONFIG_HID_SPEEDLINK is not set
CONFIG_HID_STEAM=m
# CONFIG_STEAM_FF is not set
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
CONFIG_HID_SMARTJOYPLUS=m
# CONFIG_SMARTJOYPLUS_FF is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_TOPRE is not set
CONFIG_HID_THINGM=m
CONFIG_HID_UDRAW_PS3=m
# CONFIG_HID_WIIMOTE is not set
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
# end of Special HID drivers

#
# HID-BPF support
#
# end of HID-BPF support

#
# USB HID support
#
# CONFIG_USB_HID is not set
# CONFIG_HID_PID is not set

#
# USB HID Boot Protocol drivers
#
CONFIG_USB_KBD=m
# CONFIG_USB_MOUSE is not set
# end of USB HID Boot Protocol drivers
# end of USB HID support

CONFIG_I2C_HID=m
# CONFIG_I2C_HID_ACPI is not set
CONFIG_I2C_HID_OF=m
# CONFIG_I2C_HID_OF_ELAN is not set
CONFIG_I2C_HID_OF_GOODIX=m
CONFIG_I2C_HID_CORE=m
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
# CONFIG_USB_LED_TRIG is not set
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=m
CONFIG_USB_PCI=y
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set

#
# Miscellaneous USB options
#
# CONFIG_USB_DEFAULT_PERSIST is not set
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG_PRODUCTLIST=y
CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=m

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_XHCI_HCD is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_OXU210HP_HCD is not set
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_OHCI_HCD=m
# CONFIG_USB_OHCI_HCD_PCI is not set
CONFIG_USB_OHCI_HCD_SSB=y
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_UHCI_HCD=m
# CONFIG_USB_SL811_HCD is not set
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_SSB=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
# CONFIG_USBIP_CORE is not set

#
# USB dual-mode controller drivers
#
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=m
# CONFIG_USB_MUSB_HOST is not set
CONFIG_USB_MUSB_GADGET=y
# CONFIG_USB_MUSB_DUAL_ROLE is not set

#
# Platform Glue Layer
#

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
# CONFIG_USB_DWC3 is not set
CONFIG_USB_DWC2=m
CONFIG_USB_DWC2_HOST=y

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
# CONFIG_USB_DWC2_DUAL_ROLE is not set
CONFIG_USB_DWC2_PCI=m
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
# CONFIG_USB_CHIPIDEA_UDC is not set
# CONFIG_USB_CHIPIDEA_PCI is not set
# CONFIG_USB_CHIPIDEA_MSM is not set
# CONFIG_USB_CHIPIDEA_IMX is not set
# CONFIG_USB_CHIPIDEA_GENERIC is not set
CONFIG_USB_CHIPIDEA_TEGRA=m
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
CONFIG_USB_ISP1760_GADGET_ROLE=y
# CONFIG_USB_ISP1760_DUAL_ROLE is not set

#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_USS720 is not set
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
CONFIG_USB_CYPRESS_CY7C63=m
# CONFIG_USB_CYTHERM is not set
CONFIG_USB_IDMOUSE=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_LINK_LAYER_TEST is not set
CONFIG_USB_CHAOSKEY=m
# CONFIG_USB_ONBOARD_HUB is not set

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
# CONFIG_USB_GPIO_VBUS is not set
CONFIG_TAHVO_USB=m
# CONFIG_TAHVO_USB_HOST_BY_DEFAULT is not set
# CONFIG_USB_ISP1301 is not set
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG=y
# CONFIG_USB_GADGET_VERBOSE is not set
CONFIG_USB_GADGET_DEBUG_FILES=y
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
CONFIG_U_SERIAL_CONSOLE=y

#
# USB Peripheral Controller
#
CONFIG_USB_FUSB300=y
CONFIG_USB_GR_UDC=m
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=y
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
CONFIG_USB_NET2280=y
CONFIG_USB_GOKU=y
# CONFIG_USB_EG20T is not set
CONFIG_USB_GADGET_XILINX=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_FS=y
CONFIG_USB_F_UAC1_LEGACY=y
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_HID=y
CONFIG_USB_F_PRINTER=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
# CONFIG_USB_CONFIGFS_OBEX is not set
# CONFIG_USB_CONFIGFS_NCM is not set
# CONFIG_USB_CONFIGFS_ECM is not set
# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
# CONFIG_USB_CONFIGFS_RNDIS is not set
# CONFIG_USB_CONFIGFS_EEM is not set
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
CONFIG_USB_CONFIGFS_F_FS=y
# CONFIG_USB_CONFIGFS_F_UAC1 is not set
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
# CONFIG_USB_CONFIGFS_F_UAC2 is not set
# CONFIG_USB_CONFIGFS_F_MIDI is not set
CONFIG_USB_CONFIGFS_F_HID=y
# CONFIG_USB_CONFIGFS_F_UVC is not set
CONFIG_USB_CONFIGFS_F_PRINTER=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_AUDIO=m
# CONFIG_GADGET_UAC1 is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_G_NCM is not set
# CONFIG_USB_GADGETFS is not set
CONFIG_USB_FUNCTIONFS=y
# CONFIG_USB_FUNCTIONFS_ETH is not set
# CONFIG_USB_FUNCTIONFS_RNDIS is not set
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_G_SERIAL=m
# CONFIG_USB_MIDI_GADGET is not set
CONFIG_USB_G_PRINTER=y
# CONFIG_USB_CDC_COMPOSITE is not set
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
# CONFIG_USB_G_WEBCAM is not set
CONFIG_USB_RAW_GADGET=y
# end of USB Gadget precomposed configurations

# CONFIG_TYPEC is not set
CONFIG_USB_ROLE_SWITCH=y
# CONFIG_USB_ROLES_INTEL_XHCI is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
CONFIG_LEDS_CLASS_MULTICOLOR=m
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_88PM860X is not set
# CONFIG_LEDS_AN30259A is not set
CONFIG_LEDS_APU=m
CONFIG_LEDS_AW2013=m
# CONFIG_LEDS_BCM6328 is not set
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_LM3530=m
# CONFIG_LEDS_LM3532 is not set
CONFIG_LEDS_LM3533=y
# CONFIG_LEDS_LM3642 is not set
CONFIG_LEDS_LM3692X=y
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
# CONFIG_LEDS_PCA963X is not set
CONFIG_LEDS_DA903X=y
CONFIG_LEDS_PWM=m
CONFIG_LEDS_REGULATOR=y
# CONFIG_LEDS_BD2606MVV is not set
CONFIG_LEDS_BD2802=m
# CONFIG_LEDS_INTEL_SS4200 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_ADP5520=y
# CONFIG_LEDS_TCA6507 is not set
CONFIG_LEDS_TLC591XX=m
# CONFIG_LEDS_MAX77650 is not set
CONFIG_LEDS_LM355x=y
CONFIG_LEDS_OT200=y
CONFIG_LEDS_MENF21BMC=m
# CONFIG_LEDS_IS31FL319X is not set
CONFIG_LEDS_IS31FL32XX=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXCPLD=y
CONFIG_LEDS_MLXREG=y
CONFIG_LEDS_USER=m
# CONFIG_LEDS_NIC78BX is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set
# CONFIG_LEDS_LGM is not set

#
# Flash and Torch LED drivers
#
# CONFIG_LEDS_AAT1290 is not set
CONFIG_LEDS_AS3645A=m
# CONFIG_LEDS_KTD2692 is not set
CONFIG_LEDS_LM3601X=m
# CONFIG_LEDS_MAX77693 is not set
# CONFIG_LEDS_MT6360 is not set
# CONFIG_LEDS_RT4505 is not set
# CONFIG_LEDS_RT8515 is not set
CONFIG_LEDS_SGM3140=m

#
# RGB LED drivers
#
# CONFIG_LEDS_PWM_MULTICOLOR is not set
# CONFIG_LEDS_QCOM_LPG is not set

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
# CONFIG_LEDS_TRIGGER_MTD is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
# CONFIG_LEDS_TRIGGER_CPU is not set
CONFIG_LEDS_TRIGGER_ACTIVITY=m
CONFIG_LEDS_TRIGGER_DEFAULT_ON=m

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=m
# CONFIG_LEDS_TRIGGER_PANIC is not set
# CONFIG_LEDS_TRIGGER_NETDEV is not set
# CONFIG_LEDS_TRIGGER_PATTERN is not set
# CONFIG_LEDS_TRIGGER_AUDIO is not set
# CONFIG_LEDS_TRIGGER_TTY is not set

#
# Simple LED drivers
#
CONFIG_ACCESSIBILITY=y

#
# Speakup console speech
#
# end of Speakup console speech

# CONFIG_INFINIBAND is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_SYSTOHC is not set
CONFIG_RTC_DEBUG=y
# CONFIG_RTC_NVMEM is not set

#
# RTC interfaces
#
# CONFIG_RTC_INTF_SYSFS is not set
# CONFIG_RTC_INTF_PROC is not set
# CONFIG_RTC_INTF_DEV is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_88PM860X=y
CONFIG_RTC_DRV_88PM80X=m
CONFIG_RTC_DRV_ABB5ZES3=m
CONFIG_RTC_DRV_ABEOZ9=m
CONFIG_RTC_DRV_ABX80X=y
CONFIG_RTC_DRV_DS1307=m
# CONFIG_RTC_DRV_DS1307_CENTURY is not set
CONFIG_RTC_DRV_DS1374=m
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=m
CONFIG_RTC_DRV_MAX6900=m
# CONFIG_RTC_DRV_MAX8907 is not set
CONFIG_RTC_DRV_MAX8925=y
CONFIG_RTC_DRV_MAX8998=y
CONFIG_RTC_DRV_MAX77686=m
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RS5C372=y
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
CONFIG_RTC_DRV_ISL12026=y
CONFIG_RTC_DRV_X1205=y
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=y
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_PCF8583=m
CONFIG_RTC_DRV_M41T80=y
# CONFIG_RTC_DRV_M41T80_WDT is not set
# CONFIG_RTC_DRV_BD70528 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_TPS6586X is not set
CONFIG_RTC_DRV_RC5T619=m
# CONFIG_RTC_DRV_S35390A is not set
CONFIG_RTC_DRV_FM3130=y
CONFIG_RTC_DRV_RX8010=y
# CONFIG_RTC_DRV_RX8581 is not set
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
CONFIG_RTC_DRV_RV8803=m
CONFIG_RTC_DRV_S5M=m
CONFIG_RTC_DRV_SD3078=y

#
# SPI RTC drivers
#
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
CONFIG_RTC_DRV_PCF2127=y
CONFIG_RTC_DRV_RV3029C2=y
CONFIG_RTC_DRV_RV3029_HWMON=y
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=m
CONFIG_RTC_DRV_DS1286=y
CONFIG_RTC_DRV_DS1511=y
# CONFIG_RTC_DRV_DS1553 is not set
CONFIG_RTC_DRV_DS1685_FAMILY=y
# CONFIG_RTC_DRV_DS1685 is not set
# CONFIG_RTC_DRV_DS1689 is not set
CONFIG_RTC_DRV_DS17285=y
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=y
# CONFIG_RTC_DRV_DA9055 is not set
CONFIG_RTC_DRV_DA9063=m
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=y
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=y
CONFIG_RTC_DRV_PCF50633=m
CONFIG_RTC_DRV_ZYNQMP=m

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_CADENCE=m
CONFIG_RTC_DRV_FTRTC010=y
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_GOLDFISH=y
# CONFIG_DMADEVICES is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
CONFIG_DMABUF_DEBUG=y
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
# CONFIG_DMABUF_SYSFS_STATS is not set
# CONFIG_DMABUF_HEAPS_SYSTEM is not set
CONFIG_DMABUF_HEAPS_CMA=y
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=y
CONFIG_LINEDISP=y
CONFIG_HD44780_COMMON=y
CONFIG_HD44780=m
CONFIG_KS0108=y
CONFIG_KS0108_PORT=0x378
CONFIG_KS0108_DELAY=2
# CONFIG_CFAG12864B is not set
CONFIG_IMG_ASCII_LCD=y
CONFIG_HT16K33=m
# CONFIG_LCD2S is not set
CONFIG_PARPORT_PANEL=y
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
CONFIG_PANEL_CHANGE_MESSAGE=y
CONFIG_PANEL_BOOT_MESSAGE=""
# CONFIG_CHARLCD_BL_OFF is not set
CONFIG_CHARLCD_BL_ON=y
# CONFIG_CHARLCD_BL_FLASH is not set
# CONFIG_PANEL is not set
CONFIG_UIO=m
# CONFIG_UIO_CIF is not set
CONFIG_UIO_PDRV_GENIRQ=m
CONFIG_UIO_DMEM_GENIRQ=m
CONFIG_UIO_AEC=m
CONFIG_UIO_SERCOS3=m
CONFIG_UIO_PCI_GENERIC=m
CONFIG_UIO_NETX=m
CONFIG_UIO_PRUSS=m
CONFIG_UIO_MF624=m
CONFIG_VFIO=y
CONFIG_VFIO_CONTAINER=y
CONFIG_VFIO_IOMMU_TYPE1=y
# CONFIG_VFIO_NOIOMMU is not set
CONFIG_VFIO_VIRQFD=y
CONFIG_VFIO_PCI_CORE=y
CONFIG_VFIO_PCI_MMAP=y
CONFIG_VFIO_PCI_INTX=y
CONFIG_VFIO_PCI=y
CONFIG_VFIO_PCI_IGD=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
CONFIG_VBOXGUEST=m
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
# CONFIG_VIRTIO_MENU is not set
CONFIG_VDPA=y
# CONFIG_VDPA_USER is not set
# CONFIG_IFCVF is not set
# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set
# CONFIG_VP_VDPA is not set
# CONFIG_ALIBABA_ENI_VDPA is not set
# CONFIG_SNET_VDPA is not set
# CONFIG_VHOST_MENU is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
# CONFIG_STAGING is not set
CONFIG_GOLDFISH_PIPE=m
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_OLPC_EC=y
CONFIG_SURFACE_PLATFORMS=y
# CONFIG_SURFACE_3_POWER_OPREGION is not set
# CONFIG_SURFACE_GPE is not set
# CONFIG_SURFACE_HOTPLUG is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
CONFIG_X86_PLATFORM_DEVICES=y
CONFIG_ACPI_WMI=y
CONFIG_WMI_BMOF=y
# CONFIG_HUAWEI_WMI is not set
# CONFIG_MXM_WMI is not set
# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
# CONFIG_XIAOMI_WMI is not set
# CONFIG_GIGABYTE_WMI is not set
# CONFIG_YOGABOOK_WMI is not set
# CONFIG_ACERHDF is not set
# CONFIG_ACER_WIRELESS is not set
# CONFIG_ACER_WMI is not set
# CONFIG_ADV_SWBUTTON is not set
# CONFIG_APPLE_GMUX is not set
# CONFIG_ASUS_LAPTOP is not set
# CONFIG_ASUS_WIRELESS is not set
# CONFIG_ASUS_WMI is not set
# CONFIG_ASUS_TF103C_DOCK is not set
# CONFIG_EEEPC_LAPTOP is not set
# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_FUJITSU_TABLET is not set
# CONFIG_GPD_POCKET_FAN is not set
# CONFIG_X86_PLATFORM_DRIVERS_HP is not set
# CONFIG_WIRELESS_HOTKEY is not set
# CONFIG_IBM_RTL is not set
# CONFIG_LENOVO_YMC is not set
# CONFIG_SENSORS_HDAPS is not set
# CONFIG_THINKPAD_ACPI is not set
# CONFIG_THINKPAD_LMI is not set
# CONFIG_INTEL_ATOMISP2_LED is not set
# CONFIG_INTEL_SAR_INT1092 is not set
# CONFIG_INTEL_SKL_INT3472 is not set
# CONFIG_INTEL_PMC_CORE is not set
# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
# CONFIG_INTEL_WMI_THUNDERBOLT is not set
# CONFIG_INTEL_HID_EVENT is not set
# CONFIG_INTEL_VBTN is not set
# CONFIG_INTEL_PUNIT_IPC is not set
# CONFIG_INTEL_RST is not set
# CONFIG_INTEL_SMARTCONNECT is not set
# CONFIG_INTEL_VSEC is not set
# CONFIG_MSI_EC is not set
# CONFIG_MSI_WMI is not set
# CONFIG_XO15_EBOOK is not set
# CONFIG_PCENGINES_APU2 is not set
# CONFIG_BARCO_P50_GPIO is not set
# CONFIG_SAMSUNG_LAPTOP is not set
# CONFIG_SAMSUNG_Q10 is not set
# CONFIG_ACPI_TOSHIBA is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_HAPS is not set
# CONFIG_TOSHIBA_WMI is not set
# CONFIG_ACPI_CMPC is not set
# CONFIG_LG_LAPTOP is not set
# CONFIG_PANASONIC_LAPTOP is not set
# CONFIG_SYSTEM76_ACPI is not set
# CONFIG_TOPSTAR_LAPTOP is not set
# CONFIG_MLX_PLATFORM is not set
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_SCU_PCI is not set
# CONFIG_INTEL_SCU_PLATFORM is not set
# CONFIG_SIEMENS_SIMATIC_IPC is not set
# CONFIG_WINMATE_FM07_KEYS is not set
CONFIG_P2SB=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_MAX77686 is not set
CONFIG_COMMON_CLK_MAX9485=m
# CONFIG_COMMON_CLK_SI5341 is not set
CONFIG_COMMON_CLK_SI5351=y
CONFIG_COMMON_CLK_SI514=y
CONFIG_COMMON_CLK_SI544=m
CONFIG_COMMON_CLK_SI570=y
CONFIG_COMMON_CLK_CDCE706=m
CONFIG_COMMON_CLK_CDCE925=y
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_S2MPS11 is not set
CONFIG_CLK_TWL6040=y
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_SI521XX is not set
CONFIG_COMMON_CLK_VC5=m
# CONFIG_COMMON_CLK_VC7 is not set
CONFIG_COMMON_CLK_BD718XX=m
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
# CONFIG_CLK_LGM_CGU is not set
CONFIG_XILINX_VCU=m
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_HWSPINLOCK is not set

#
# Clock Source drivers
#
CONFIG_CLKSRC_I8253=y
CONFIG_CLKEVT_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_CLKBLD_I8253=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PCC is not set
CONFIG_ALTERA_MBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_SUPPORT is not set

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
# CONFIG_RPMSG_CHAR is not set
# CONFIG_RPMSG_CTRL is not set
CONFIG_RPMSG_NS=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

CONFIG_SOUNDWIRE=y

#
# SoundWire Devices
#

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

# CONFIG_WPCM450_SOC is not set

#
# Qualcomm SoC drivers
#
# end of Qualcomm SoC drivers

CONFIG_SOC_TI=y

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

# CONFIG_PM_DEVFREQ is not set
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
# CONFIG_EXTCON_AXP288 is not set
CONFIG_EXTCON_FSA9480=m
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_INTEL_INT3496 is not set
CONFIG_EXTCON_MAX14577=m
CONFIG_EXTCON_MAX3355=m
CONFIG_EXTCON_MAX77693=m
CONFIG_EXTCON_PTN5150=m
# CONFIG_EXTCON_RT8973A is not set
CONFIG_EXTCON_SM5502=m
# CONFIG_EXTCON_USB_GPIO is not set
CONFIG_MEMORY=y
CONFIG_IIO=m
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=m
CONFIG_IIO_TRIGGERED_BUFFER=m
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
# CONFIG_ADXL313_I2C is not set
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
# CONFIG_ADXL355_I2C is not set
# CONFIG_ADXL367_I2C is not set
CONFIG_ADXL372=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA180=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
# CONFIG_BMC150_ACCEL is not set
CONFIG_DA280=m
# CONFIG_DA311 is not set
CONFIG_DMARD06=m
# CONFIG_DMARD09 is not set
CONFIG_DMARD10=m
# CONFIG_FXLS8962AF_I2C is not set
# CONFIG_HID_SENSOR_ACCEL_3D is not set
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
# CONFIG_IIO_KX022A_I2C is not set
# CONFIG_KXSD9 is not set
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
# CONFIG_MMA7455_I2C is not set
# CONFIG_MMA7660 is not set
CONFIG_MMA8452=m
# CONFIG_MMA9551 is not set
# CONFIG_MMA9553 is not set
# CONFIG_MSA311 is not set
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD7091R5=m
# CONFIG_AD7291 is not set
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD799X=m
CONFIG_ADI_AXI_ADC=m
# CONFIG_AXP20X_ADC is not set
CONFIG_AXP288_ADC=m
# CONFIG_CC10001_ADC is not set
# CONFIG_DA9150_GPADC is not set
# CONFIG_DLN2_ADC is not set
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_HX711 is not set
# CONFIG_LTC2471 is not set
CONFIG_LTC2485=m
CONFIG_LTC2497=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP3422=m
# CONFIG_MEDIATEK_MT6360_ADC is not set
# CONFIG_MP2629_ADC is not set
# CONFIG_NAU7802 is not set
CONFIG_QCOM_VADC_COMMON=m
# CONFIG_QCOM_SPMI_IADC is not set
CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_RN5T618_ADC=m
# CONFIG_RICHTEK_RTQ6056 is not set
# CONFIG_SD_ADC_MODULATOR is not set
CONFIG_TI_ADC081C=m
# CONFIG_TI_ADS1015 is not set
# CONFIG_TI_ADS7924 is not set
# CONFIG_TI_ADS1100 is not set
# CONFIG_TI_AM335X_ADC is not set
# CONFIG_VF610_ADC is not set
CONFIG_VIPERBOARD_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# CONFIG_AD7746 is not set
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_CCS811=m
# CONFIG_IAQCORE is not set
# CONFIG_SCD30_CORE is not set
# CONFIG_SCD4X is not set
CONFIG_SENSIRION_SGP30=m
# CONFIG_SENSIRION_SGP40 is not set
# CONFIG_SPS30_I2C is not set
# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
# CONFIG_AD5064 is not set
# CONFIG_AD5380 is not set
CONFIG_AD5446=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5593R=m
CONFIG_AD5686=m
CONFIG_AD5696_I2C=m
# CONFIG_CIO_DAC is not set
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_M62332=m
CONFIG_MAX517=m
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_TI_DAC5571=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
# CONFIG_HDC2010 is not set
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
# CONFIG_BMI160_I2C is not set
# CONFIG_BOSCH_BNO055_I2C is not set
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_I3C=m
# CONFIG_IIO_ST_LSM9DS0 is not set
# end of Inertial measurement units

#
# Light sensors
#
# CONFIG_ACPI_ALS is not set
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
# CONFIG_AS73211 is not set
CONFIG_BH1750=m
# CONFIG_BH1780 is not set
CONFIG_CM32181=m
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
# CONFIG_CM3605 is not set
CONFIG_CM36651=m
CONFIG_GP2AP002=m
# CONFIG_GP2AP020A00F is not set
CONFIG_SENSORS_ISL29018=m
# CONFIG_SENSORS_ISL29028 is not set
# CONFIG_ISL29125 is not set
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
# CONFIG_ROHM_BU27034 is not set
# CONFIG_RPR0521 is not set
# CONFIG_SENSORS_LM3533 is not set
CONFIG_LTR501=m
# CONFIG_LTRF216A is not set
CONFIG_LV0104CS=m
# CONFIG_MAX44000 is not set
CONFIG_MAX44009=m
CONFIG_NOA1305=m
# CONFIG_OPT3001 is not set
# CONFIG_PA12203001 is not set
# CONFIG_SI1133 is not set
# CONFIG_SI1145 is not set
CONFIG_STK3310=m
# CONFIG_ST_UVIS25 is not set
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
# CONFIG_TSL2591 is not set
# CONFIG_TSL2772 is not set
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
# CONFIG_VCNL4035 is not set
CONFIG_VEML6030=m
# CONFIG_VEML6070 is not set
# CONFIG_VL6180 is not set
# CONFIG_ZOPT2201 is not set
# end of Light sensors

#
# Magnetometer sensors
#
# CONFIG_AK8974 is not set
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
# CONFIG_MMC35240 is not set
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
# CONFIG_TI_TMAG5273 is not set
# CONFIG_YAMAHA_YAS530 is not set
# end of Magnetometer sensors

#
# Multiplexers
#
# CONFIG_IIO_MUX is not set
# end of Multiplexers

#
# Inclinometer sensors
#
# CONFIG_HID_SENSOR_INCLINOMETER_3D is not set
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
# CONFIG_IIO_INTERRUPT_TRIGGER is not set
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
# CONFIG_IIO_SYSFS_TRIGGER is not set
# end of Triggers - standalone

#
# Linear and angular position sensors
#
# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set
# end of Linear and angular position sensors

#
# Digital potentiometers
#
# CONFIG_AD5110 is not set
# CONFIG_AD5272 is not set
CONFIG_DS1803=m
# CONFIG_MAX5432 is not set
# CONFIG_MCP4018 is not set
CONFIG_MCP4531=m
CONFIG_TPL0102=m
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
# CONFIG_DLHL60D is not set
# CONFIG_DPS310 is not set
CONFIG_HID_SENSOR_PRESS=m
# CONFIG_HP03 is not set
# CONFIG_ICP10100 is not set
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
# CONFIG_MPL3115 is not set
# CONFIG_MS5611 is not set
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_T5403=m
# CONFIG_HP206C is not set
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
# end of Pressure sensors

#
# Lightning sensors
#
# end of Lightning sensors

#
# Proximity and distance sensors
#
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
# CONFIG_MB1232 is not set
# CONFIG_PING is not set
# CONFIG_RFD77402 is not set
CONFIG_SRF04=m
# CONFIG_SX9310 is not set
# CONFIG_SX9324 is not set
# CONFIG_SX9360 is not set
# CONFIG_SX9500 is not set
CONFIG_SRF08=m
CONFIG_VCNL3020=m
# CONFIG_VL53L0X_I2C is not set
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
# end of Resolver to digital converters

#
# Temperature sensors
#
# CONFIG_HID_SENSOR_TEMP is not set
CONFIG_MLX90614=m
CONFIG_MLX90632=m
# CONFIG_TMP006 is not set
CONFIG_TMP007=m
# CONFIG_TMP117 is not set
# CONFIG_TSYS01 is not set
CONFIG_TSYS02D=m
# CONFIG_MAX30208 is not set
# end of Temperature sensors

CONFIG_NTB=m
CONFIG_NTB_MSI=y
# CONFIG_NTB_IDT is not set
# CONFIG_NTB_EPF is not set
CONFIG_NTB_SWITCHTEC=m
CONFIG_NTB_PINGPONG=m
CONFIG_NTB_TOOL=m
# CONFIG_NTB_PERF is not set
# CONFIG_NTB_MSI_TEST is not set
# CONFIG_NTB_TRANSPORT is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_DEBUG=y
# CONFIG_PWM_ATMEL_TCB is not set
# CONFIG_PWM_CLK is not set
# CONFIG_PWM_DWC is not set
CONFIG_PWM_FSL_FTM=m
# CONFIG_PWM_INTEL_LGM is not set
CONFIG_PWM_LP3943=m
CONFIG_PWM_LPSS=m
CONFIG_PWM_LPSS_PCI=m
# CONFIG_PWM_LPSS_PLATFORM is not set
CONFIG_PWM_PCA9685=m
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_AL_FIC=y
CONFIG_MADERA_IRQ=m
# CONFIG_XILINX_INTC is not set
# end of IRQ chip support

CONFIG_IPACK_BUS=y
CONFIG_BOARD_TPCI200=m
# CONFIG_SERIAL_IPOCTAL is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_INTEL_GW=y
# CONFIG_RESET_SIMPLE is not set
CONFIG_RESET_TI_SYSCON=y
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_USB_LGM_PHY is not set
# CONFIG_PHY_CAN_TRANSCEIVER is not set

#
# PHY drivers for Broadcom platforms
#
CONFIG_BCM_KONA_USB2_PHY=m
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
CONFIG_PHY_CADENCE_SIERRA=y
# CONFIG_PHY_CADENCE_SALVO is not set
CONFIG_PHY_PXA_28NM_HSIC=y
CONFIG_PHY_PXA_28NM_USB2=m
# CONFIG_PHY_LAN966X_SERDES is not set
CONFIG_PHY_CPCAP_USB=m
CONFIG_PHY_MAPPHONE_MDM6600=y
CONFIG_PHY_OCELOT_SERDES=y
# CONFIG_PHY_QCOM_USB_HS is not set
CONFIG_PHY_QCOM_USB_HSIC=y
CONFIG_PHY_SAMSUNG_USB2=m
CONFIG_PHY_TUSB1210=m
CONFIG_PHY_INTEL_LGM_COMBO=y
# CONFIG_PHY_INTEL_LGM_EMMC is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
# end of Performance monitor support

CONFIG_RAS=y
CONFIG_USB4=m
CONFIG_USB4_DEBUGFS_WRITE=y
# CONFIG_USB4_DEBUGFS_MARGINING is not set
# CONFIG_USB4_DMA_TEST is not set

#
# Android
#
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android

# CONFIG_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y

#
# Layout Types
#
# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set
# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set
# end of Layout Types

# CONFIG_NVMEM_RMEM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
# CONFIG_NVMEM_U_BOOT_ENV is not set

#
# HW tracing support
#
CONFIG_STM=y
CONFIG_STM_PROTO_BASIC=y
CONFIG_STM_PROTO_SYS_T=m
CONFIG_STM_DUMMY=m
CONFIG_STM_SOURCE_CONSOLE=y
CONFIG_STM_SOURCE_HEARTBEAT=y
CONFIG_STM_SOURCE_FTRACE=y
CONFIG_INTEL_TH=y
CONFIG_INTEL_TH_PCI=m
# CONFIG_INTEL_TH_ACPI is not set
CONFIG_INTEL_TH_GTH=y
CONFIG_INTEL_TH_STH=m
# CONFIG_INTEL_TH_MSU is not set
CONFIG_INTEL_TH_PTI=m
CONFIG_INTEL_TH_DEBUG=y
# end of HW tracing support

# CONFIG_FPGA is not set
CONFIG_FSI=m
CONFIG_FSI_NEW_DEV_NODE=y
CONFIG_FSI_MASTER_GPIO=m
CONFIG_FSI_MASTER_HUB=m
CONFIG_FSI_MASTER_ASPEED=m
CONFIG_FSI_SCOM=m
# CONFIG_FSI_SBEFIFO is not set
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
CONFIG_MUX_ADG792A=y
# CONFIG_MUX_GPIO is not set
CONFIG_MUX_MMIO=y
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
CONFIG_SLIMBUS=y
CONFIG_SLIM_QCOM_CTRL=m
# CONFIG_INTERCONNECT is not set
CONFIG_COUNTER=m
# CONFIG_INTEL_QEP is not set
# CONFIG_INTERRUPT_CNT is not set
CONFIG_MOST=y
# CONFIG_MOST_USB_HDM is not set
CONFIG_MOST_CDEV=y
# CONFIG_MOST_SND is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS4_FS=m
CONFIG_AUTOFS_FS=m
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=y
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set
# CONFIG_OVERLAY_FS_INDEX is not set
CONFIG_OVERLAY_FS_METACOPY=y

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
# CONFIG_NETFS_STATS is not set
# CONFIG_FSCACHE is not set
# end of Caches

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_PROC_CHILDREN=y
CONFIG_PROC_PID_ARCH_STATUS=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_HUGETLBFS is not set
CONFIG_MEMFD_CREATE=y
CONFIG_CONFIGFS_FS=y
# end of Pseudo filesystems

# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=m
# CONFIG_NFS_V4_1 is not set
# CONFIG_ROOT_NFS is not set
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
CONFIG_RPCSEC_GSS_KRB5_CRYPTOSYSTEM=y
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
# CONFIG_CIFS_UPCALL is not set
# CONFIG_CIFS_XATTR is not set
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
# CONFIG_CIFS_DFS_UPCALL is not set
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_SMB_SERVER is not set
CONFIG_SMBFS_COMMON=m
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
# CONFIG_NLS_CODEPAGE_775 is not set
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_CODEPAGE_932=y
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=y
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
# CONFIG_NLS_ISO8859_15 is not set
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
CONFIG_NLS_MAC_GREEK=y
CONFIG_NLS_MAC_ICELAND=y
CONFIG_NLS_MAC_INUIT=y
CONFIG_NLS_MAC_ROMANIAN=y
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
CONFIG_UNICODE=y
# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_REQUEST_CACHE=y
# CONFIG_PERSISTENT_KEYRINGS is not set
CONFIG_TRUSTED_KEYS=m
CONFIG_TRUSTED_KEYS_TPM=y
# CONFIG_ENCRYPTED_KEYS is not set
CONFIG_KEY_DH_OPERATIONS=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_FORTIFY_SOURCE=y
# CONFIG_STATIC_USERMODEHELPER is not set
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
# CONFIG_IMA is not set
# CONFIG_EVM is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_INIT_STACK_NONE=y
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
CONFIG_INIT_ON_FREE_DEFAULT_ON=y
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
# CONFIG_CRYPTO_ECDSA is not set
CONFIG_CRYPTO_ECRDSA=m
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
# CONFIG_CRYPTO_ARIA is not set
# CONFIG_CRYPTO_BLOWFISH is not set
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=y
# CONFIG_CRYPTO_CAST5 is not set
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=m
CONFIG_CRYPTO_SM4_GENERIC=m
# CONFIG_CRYPTO_TWOFISH is not set
CONFIG_CRYPTO_TWOFISH_COMMON=m
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_HCTR2 is not set
CONFIG_CRYPTO_KEYWRAP=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_OFB is not set
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=m
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_ESSIV=m
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_GHASH=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_POLY1305 is not set
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_SHA3 is not set
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=m
CONFIG_CRYPTO_STREEBOG=m
# CONFIG_CRYPTO_VMAC is not set
CONFIG_CRYPTO_WP512=y
CONFIG_CRYPTO_XCBC=y
# CONFIG_CRYPTO_XXHASH is not set
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=m
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_ZSTD is not set
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_KDF800108_CTR=y
# end of Random number generation

#
# Userspace interface
#
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y

#
# Accelerated Cryptographic Algorithms for CPU (x86)
#
CONFIG_CRYPTO_AES_NI_INTEL=y
# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
CONFIG_CRYPTO_TWOFISH_586=m
CONFIG_CRYPTO_CRC32C_INTEL=y
CONFIG_CRYPTO_CRC32_PCLMUL=y
# end of Accelerated Cryptographic Algorithms for CPU (x86)

CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_PADLOCK=y
# CONFIG_CRYPTO_DEV_PADLOCK_AES is not set
# CONFIG_CRYPTO_DEV_PADLOCK_SHA is not set
CONFIG_CRYPTO_DEV_GEODE=y
# CONFIG_CRYPTO_DEV_HIFN_795X is not set
CONFIG_CRYPTO_DEV_ATMEL_I2C=y
CONFIG_CRYPTO_DEV_ATMEL_ECC=y
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
CONFIG_CRYPTO_DEV_CCP=y
CONFIG_CRYPTO_DEV_QAT=y
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
CONFIG_CRYPTO_DEV_QAT_C62X=y
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
CONFIG_CRYPTO_DEV_QAT_C62XVF=m
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=m
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
CONFIG_SYSTEM_BLACKLIST_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
CONFIG_SYSTEM_REVOCATION_LIST=y
CONFIG_SYSTEM_REVOCATION_KEYS=""
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=y
CONFIG_PRIME_NUMBERS=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_GF128MUL=m
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
# CONFIG_CRYPTO_LIB_CURVE25519 is not set
CONFIG_CRYPTO_LIB_DES=m
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
# CONFIG_CRC64_ROCKSOFT is not set
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
# CONFIG_CRC32_SLICEBY8 is not set
# CONFIG_CRC32_SLICEBY4 is not set
CONFIG_CRC32_SARWATE=y
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC64 is not set
CONFIG_CRC4=y
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=m
CONFIG_CRC8=y
CONFIG_XXHASH=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=m
CONFIG_842_DECOMPRESS=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=m
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
CONFIG_XZ_DEC_POWERPC=y
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
# CONFIG_XZ_DEC_ARMTHUMB is not set
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_MICROLZMA is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_PERCENTAGE=0
# CONFIG_CMA_SIZE_SEL_MBYTES is not set
CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CHECK_SIGNATURE=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=m
CONFIG_FONT_8x16=y
CONFIG_FONT_AUTOSELECT=y
CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_STACKDEPOT_ALWAYS_INIT=y
# end of Library routines

CONFIG_ASN1_ENCODER=m

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_CALLER=y
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DYNAMIC_DEBUG_CORE is not set
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_AS_HAS_NON_CONST_LEB128=y
# CONFIG_DEBUG_INFO_NONE is not set
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=8192
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_READABLE_ASM=y
CONFIG_HEADERS_INSTALL=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_FS_ALLOW_ALL is not set
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
CONFIG_DEBUG_FS_ALLOW_NONE=y
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
CONFIG_UBSAN=y
# CONFIG_UBSAN_TRAP is not set
CONFIG_CC_HAS_UBSAN_BOUNDS=y
CONFIG_UBSAN_BOUNDS=y
CONFIG_UBSAN_ONLY_BOUNDS=y
CONFIG_UBSAN_SHIFT=y
# CONFIG_UBSAN_DIV_ZERO is not set
CONFIG_UBSAN_UNREACHABLE=y
# CONFIG_UBSAN_BOOL is not set
# CONFIG_UBSAN_ENUM is not set
# CONFIG_UBSAN_ALIGNMENT is not set
CONFIG_UBSAN_SANITIZE_ALL=y
# CONFIG_TEST_UBSAN is not set
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
CONFIG_PAGE_OWNER=y
CONFIG_PAGE_POISONING=y
CONFIG_DEBUG_PAGE_REF=y
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000
# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set
# CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN is not set
CONFIG_DEBUG_OBJECTS=y
# CONFIG_DEBUG_OBJECTS_SELFTEST is not set
# CONFIG_DEBUG_OBJECTS_FREE is not set
# CONFIG_DEBUG_OBJECTS_TIMERS is not set
CONFIG_DEBUG_OBJECTS_WORK=y
CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
# CONFIG_SHRINKER_DEBUG is not set
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
CONFIG_DEBUG_VM_IRQSOFF=y
CONFIG_DEBUG_VM=y
# CONFIG_DEBUG_VM_MAPLE_TREE is not set
# CONFIG_DEBUG_VM_RB is not set
# CONFIG_DEBUG_VM_PGFLAGS is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
CONFIG_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_MEMORY_INIT is not set
CONFIG_DEBUG_KMAP_LOCAL=y
CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y
CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP=y
CONFIG_DEBUG_HIGHMEM=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

CONFIG_DEBUG_SHIRQ=y

#
# Debug Oops, Lockups and Hangs
#
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=480
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_WQ_WATCHDOG=y
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

CONFIG_DEBUG_TIMEKEEPING=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_PROVE_LOCKING=y
# CONFIG_PROVE_RAW_LOCK_NESTING is not set
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_LOCKDEP=y
CONFIG_LOCKDEP_BITS=15
CONFIG_LOCKDEP_CHAINS_BITS=16
CONFIG_LOCKDEP_STACK_TRACE_BITS=19
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_LOCK_TORTURE_TEST=m
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

CONFIG_TRACE_IRQFLAGS=y
CONFIG_TRACE_IRQFLAGS_NMI=y
# CONFIG_NMI_CHECK_CPU is not set
# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
CONFIG_DEBUG_PLIST=y
CONFIG_DEBUG_SG=y
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

CONFIG_DEBUG_CREDENTIALS=y

#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
# CONFIG_PROVE_RCU_LIST is not set
CONFIG_TORTURE_TEST=m
CONFIG_RCU_SCALE_TEST=m
CONFIG_RCU_TORTURE_TEST=m
CONFIG_RCU_REF_SCALE_TEST=m
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_EQS_DEBUG=y
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
CONFIG_LATENCYTOP=y
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_RETHOOK=y
CONFIG_RETHOOK=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_FENTRY=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
CONFIG_BUILDTIME_MCOUNT_SORT=y
CONFIG_TRACER_MAX_TRACE=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_PREEMPTIRQ_TRACEPOINTS=y
CONFIG_TRACING=y
CONFIG_GLOBAL_TRACE_BUF_SIZE=1441792
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
CONFIG_FUNCTION_TRACER=y
CONFIG_FUNCTION_GRAPH_TRACER=y
CONFIG_DYNAMIC_FTRACE=y
CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
# CONFIG_FPROBE is not set
# CONFIG_FUNCTION_PROFILER is not set
CONFIG_STACK_TRACER=y
CONFIG_IRQSOFF_TRACER=y
# CONFIG_SCHED_TRACER is not set
CONFIG_HWLAT_TRACER=y
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
CONFIG_MMIOTRACE=y
# CONFIG_FTRACE_SYSCALLS is not set
CONFIG_TRACER_SNAPSHOT=y
CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
CONFIG_TRACE_BRANCH_PROFILING=y
# CONFIG_BRANCH_PROFILE_NONE is not set
CONFIG_PROFILE_ANNOTATED_BRANCHES=y
# CONFIG_BRANCH_TRACER is not set
CONFIG_KPROBE_EVENTS=y
# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
# CONFIG_UPROBE_EVENTS is not set
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
CONFIG_FTRACE_MCOUNT_RECORD=y
CONFIG_FTRACE_MCOUNT_USE_CC=y
CONFIG_TRACING_MAP=y
CONFIG_SYNTH_EVENTS=y
# CONFIG_USER_EVENTS is not set
CONFIG_HIST_TRIGGERS=y
CONFIG_TRACE_EVENT_INJECT=y
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
CONFIG_TRACE_EVAL_MAP_FILE=y
# CONFIG_FTRACE_RECORD_RECURSION is not set
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_MMIOTRACE_TEST is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_SYNTH_EVENT_GEN_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_HIST_TRIGGERS_DEBUG is not set
# CONFIG_RV is not set
# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
# CONFIG_SAMPLES is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set

#
# x86 Debugging
#
CONFIG_EARLY_PRINTK_USB=y
CONFIG_X86_VERBOSE_BOOTUP=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_DBGP=y
CONFIG_EARLY_PRINTK_USB_XDBC=y
CONFIG_DEBUG_TLBFLUSH=y
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
# CONFIG_X86_DECODER_SELFTEST is not set
# CONFIG_IO_DELAY_0X80 is not set
CONFIG_IO_DELAY_0XED=y
# CONFIG_IO_DELAY_UDELAY is not set
# CONFIG_IO_DELAY_NONE is not set
CONFIG_DEBUG_BOOT_PARAMS=y
# CONFIG_CPA_DEBUG is not set
# CONFIG_DEBUG_ENTRY is not set
# CONFIG_DEBUG_NMI_SELFTEST is not set
CONFIG_X86_DEBUG_FPU=y
CONFIG_PUNIT_ATOM_DEBUG=m
CONFIG_UNWINDER_FRAME_POINTER=y
# end of x86 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
CONFIG_NOTIFIER_ERROR_INJECTION=y
# CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT is not set
# CONFIG_NETDEV_NOTIFIER_ERROR_INJECT is not set
CONFIG_FUNCTION_ERROR_INJECTION=y
CONFIG_FAULT_INJECTION=y
# CONFIG_FAILSLAB is not set
CONFIG_FAIL_PAGE_ALLOC=y
# CONFIG_FAULT_INJECTION_USERCOPY is not set
CONFIG_FAIL_FUTEX=y
# CONFIG_FAULT_INJECTION_DEBUG_FS is not set
# CONFIG_FAULT_INJECTION_CONFIGFS is not set
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
  2023-05-18  7:53   ` kernel test robot
  2023-05-18  9:28   ` kernel test robot
@ 2023-05-18 10:44   ` Andrzej Hajda
  2023-05-22 19:10     ` Matt Roper
  2 siblings, 1 reply; 21+ messages in thread
From: Andrzej Hajda @ 2023-05-18 10:44 UTC (permalink / raw)
  To: Matt Roper, intel-gfx; +Cc: intel-xe

On 18.05.2023 05:18, Matt Roper wrote:
> For platforms with GMD_ID support (i.e., everything MTL and beyond),
> identification of the display IP present should be based on the contents
> of the GMD_ID register rather than a PCI devid match.
> 
> Note that since GMD_ID readout requires access to the PCI BAR, a slight
> change to the driver init sequence is needed --- pci_enable_device() is
> now called before i915_driver_create().
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   .../drm/i915/display/intel_display_device.c   | 64 +++++++++++++++++--
>   .../drm/i915/display/intel_display_device.h   |  5 +-
>   drivers/gpu/drm/i915/i915_driver.c            | 10 +--
>   drivers/gpu/drm/i915/intel_device_info.c      | 13 ++--
>   4 files changed, 78 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 78fa522aaf0b..813a2a494082 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -6,7 +6,10 @@
>   #include <drm/i915_pciids.h>
>   #include <drm/drm_color_mgmt.h>
>   #include <linux/mod_devicetable.h>
> +#include <linux/pci.h>
>   
> +#include "i915_drv.h"
> +#include "i915_reg.h"
>   #include "intel_display_device.h"
>   #include "intel_display_power.h"
>   #include "intel_display_reg_defs.h"
> @@ -674,18 +677,69 @@ static const struct pci_device_id intel_display_ids[] = {
>   	INTEL_RPLP_IDS(&xe_lpd_display),
>   	INTEL_DG2_IDS(&xe_hpd_display),
>   
> -	/* FIXME: Replace this with a GMD_ID lookup */
> -	INTEL_MTL_IDS(&xe_lpdp_display),
> +	/*
> +	 * Do not add any GMD_ID-based platforms to this list.  They will
> +	 * be probed automatically based on the IP version reported by
> +	 * the hardware.
> +	 */
>   };
>   
> +struct {
> +	u16 ver;
> +	u16 rel;
> +	const struct intel_display_device_info *display;
> +} gmdid_display_map[] = {
> +	{ 14,  0, &xe_lpdp_display },
> +};
> +
> +static const struct intel_display_device_info *
> +probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	void __iomem *addr;
> +	u32 val;
> +	int i;
> +
> +	addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
> +	if (!addr) {
> +		drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
> +		return NULL;
> +	}
> +
> +	val = ioread32(addr);
> +	pci_iounmap(pdev, addr);
> +
> +	if (val == 0)
> +		/* Platform doesn't have display */
> +		return NULL;
> +
> +	*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> +	*rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> +	*step = REG_FIELD_GET(GMD_ID_STEP, val);
> +
> +	for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
> +		if (*ver == gmdid_display_map[i].ver &&
> +		    *rel == gmdid_display_map[i].rel)
> +			return gmdid_display_map[i].display;
> +
> +	drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
> +		*ver, *rel);
> +	return NULL;
> +}
> +
>   const struct intel_display_device_info *
> -intel_display_device_probe(u16 pci_devid)
> +intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
> +			   u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
>   {
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>   	int i;
>   
> +	if (has_gmdid)
> +		return probe_gmdid_display(i915, gmdid_ver, gmdid_rel, gmdid_step);
> +
>   	for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> -		if (intel_display_ids[i].device == pci_devid)
> -			return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
> +		if (intel_display_ids[i].device == pdev->device)
> +			return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;
>   	}
>   
>   	return NULL;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 0a60ebfaff80..9a344ee36d8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -80,7 +80,10 @@ struct intel_display_device_info {
>   	} color;
>   };
>   
> +struct drm_i915_private;
> +
>   const struct intel_display_device_info *
> -intel_display_device_probe(u16 pci_devid);
> +intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
> +			   u16 *ver, u16 *rel, u16 *step);
>   
>   #endif
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 522733a89946..d02c602e9a0b 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -754,14 +754,16 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>   	struct drm_i915_private *i915;
>   	int ret;
>   
> -	i915 = i915_driver_create(pdev, ent);
> -	if (IS_ERR(i915))
> -		return PTR_ERR(i915);
> -
>   	ret = pci_enable_device(pdev);
>   	if (ret)
>   		goto out_fini;
>   
> +	i915 = i915_driver_create(pdev, ent);
> +	if (IS_ERR(i915)) {
> +		ret = PTR_ERR(i915);
> +		goto out_pci_disable;
> +	}
> +
>   	ret = i915_driver_early_probe(i915);
>   	if (ret < 0)
>   		goto out_pci_disable;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 9d0b54ba50c1..5f38ff8caac0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -345,7 +345,6 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
>   static void intel_ipver_early_init(struct drm_i915_private *i915)
>   {
>   	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
> -	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
>   
>   	if (!HAS_GMD_ID(i915)) {
>   		drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
> @@ -366,8 +365,6 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
>   		RUNTIME_INFO(i915)->graphics.ip.ver = 12;
>   		RUNTIME_INFO(i915)->graphics.ip.rel = 70;
>   	}
> -	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> -		    (struct intel_ip_version *)&display_runtime->ip);
>   	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
>   		    &runtime->media.ip);
>   }
> @@ -575,6 +572,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
>   	struct intel_device_info *info;
>   	struct intel_runtime_info *runtime;
>   	struct intel_display_runtime_info *display_runtime;
> +	u16 ver, rel, step;
>   
>   	/* Setup the write-once "constant" device info */
>   	info = mkwrite_device_info(i915);
> @@ -585,11 +583,18 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
>   	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
>   
>   	/* Probe display support */
> -	info->display = intel_display_device_probe(device_id);
> +	info->display = intel_display_device_probe(i915, info->has_gmd_id,
> +						   &ver, &rel, &step);
>   	if (info->display) {
>   		display_runtime = DISPLAY_RUNTIME_INFO(i915);
>   		memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
>   		       sizeof(*display_runtime));
> +
> +		if (info->has_gmd_id) {
> +			display_runtime->ip.ver = ver;
> +			display_runtime->ip.rel = rel;
> +			display_runtime->ip.step = step;
> +		}
>   	} else {
>   		info->display = &no_display;
>   	}


Why not embed display stuff into some intel_display_info_create(i915) ?
It could be one tiny step further in separating display from i915.
It could also allow write ver, rel, step directly into runtime instead 
of passing them via pointer to local vars and copying.

Regards
Andrzej

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code
  2023-05-18 10:44   ` Andrzej Hajda
@ 2023-05-22 19:10     ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-05-22 19:10 UTC (permalink / raw)
  To: Andrzej Hajda; +Cc: intel-gfx, intel-xe

On Thu, May 18, 2023 at 12:44:04PM +0200, Andrzej Hajda wrote:
> On 18.05.2023 05:18, Matt Roper wrote:
> > For platforms with GMD_ID support (i.e., everything MTL and beyond),
> > identification of the display IP present should be based on the contents
> > of the GMD_ID register rather than a PCI devid match.
> > 
> > Note that since GMD_ID readout requires access to the PCI BAR, a slight
> > change to the driver init sequence is needed --- pci_enable_device() is
> > now called before i915_driver_create().
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >   .../drm/i915/display/intel_display_device.c   | 64 +++++++++++++++++--
> >   .../drm/i915/display/intel_display_device.h   |  5 +-
> >   drivers/gpu/drm/i915/i915_driver.c            | 10 +--
> >   drivers/gpu/drm/i915/intel_device_info.c      | 13 ++--
> >   4 files changed, 78 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> > index 78fa522aaf0b..813a2a494082 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> > @@ -6,7 +6,10 @@
> >   #include <drm/i915_pciids.h>
> >   #include <drm/drm_color_mgmt.h>
> >   #include <linux/mod_devicetable.h>
> > +#include <linux/pci.h>
> > +#include "i915_drv.h"
> > +#include "i915_reg.h"
> >   #include "intel_display_device.h"
> >   #include "intel_display_power.h"
> >   #include "intel_display_reg_defs.h"
> > @@ -674,18 +677,69 @@ static const struct pci_device_id intel_display_ids[] = {
> >   	INTEL_RPLP_IDS(&xe_lpd_display),
> >   	INTEL_DG2_IDS(&xe_hpd_display),
> > -	/* FIXME: Replace this with a GMD_ID lookup */
> > -	INTEL_MTL_IDS(&xe_lpdp_display),
> > +	/*
> > +	 * Do not add any GMD_ID-based platforms to this list.  They will
> > +	 * be probed automatically based on the IP version reported by
> > +	 * the hardware.
> > +	 */
> >   };
> > +struct {
> > +	u16 ver;
> > +	u16 rel;
> > +	const struct intel_display_device_info *display;
> > +} gmdid_display_map[] = {
> > +	{ 14,  0, &xe_lpdp_display },
> > +};
> > +
> > +static const struct intel_display_device_info *
> > +probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step)
> > +{
> > +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > +	void __iomem *addr;
> > +	u32 val;
> > +	int i;
> > +
> > +	addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
> > +	if (!addr) {
> > +		drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
> > +		return NULL;
> > +	}
> > +
> > +	val = ioread32(addr);
> > +	pci_iounmap(pdev, addr);
> > +
> > +	if (val == 0)
> > +		/* Platform doesn't have display */
> > +		return NULL;
> > +
> > +	*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> > +	*rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> > +	*step = REG_FIELD_GET(GMD_ID_STEP, val);
> > +
> > +	for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
> > +		if (*ver == gmdid_display_map[i].ver &&
> > +		    *rel == gmdid_display_map[i].rel)
> > +			return gmdid_display_map[i].display;
> > +
> > +	drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
> > +		*ver, *rel);
> > +	return NULL;
> > +}
> > +
> >   const struct intel_display_device_info *
> > -intel_display_device_probe(u16 pci_devid)
> > +intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
> > +			   u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
> >   {
> > +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >   	int i;
> > +	if (has_gmdid)
> > +		return probe_gmdid_display(i915, gmdid_ver, gmdid_rel, gmdid_step);
> > +
> >   	for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> > -		if (intel_display_ids[i].device == pci_devid)
> > -			return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
> > +		if (intel_display_ids[i].device == pdev->device)
> > +			return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;
> >   	}
> >   	return NULL;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 0a60ebfaff80..9a344ee36d8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -80,7 +80,10 @@ struct intel_display_device_info {
> >   	} color;
> >   };
> > +struct drm_i915_private;
> > +
> >   const struct intel_display_device_info *
> > -intel_display_device_probe(u16 pci_devid);
> > +intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
> > +			   u16 *ver, u16 *rel, u16 *step);
> >   #endif
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > index 522733a89946..d02c602e9a0b 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -754,14 +754,16 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> >   	struct drm_i915_private *i915;
> >   	int ret;
> > -	i915 = i915_driver_create(pdev, ent);
> > -	if (IS_ERR(i915))
> > -		return PTR_ERR(i915);
> > -
> >   	ret = pci_enable_device(pdev);
> >   	if (ret)
> >   		goto out_fini;
> > +	i915 = i915_driver_create(pdev, ent);
> > +	if (IS_ERR(i915)) {
> > +		ret = PTR_ERR(i915);
> > +		goto out_pci_disable;
> > +	}
> > +
> >   	ret = i915_driver_early_probe(i915);
> >   	if (ret < 0)
> >   		goto out_pci_disable;
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index 9d0b54ba50c1..5f38ff8caac0 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -345,7 +345,6 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
> >   static void intel_ipver_early_init(struct drm_i915_private *i915)
> >   {
> >   	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
> > -	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
> >   	if (!HAS_GMD_ID(i915)) {
> >   		drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
> > @@ -366,8 +365,6 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
> >   		RUNTIME_INFO(i915)->graphics.ip.ver = 12;
> >   		RUNTIME_INFO(i915)->graphics.ip.rel = 70;
> >   	}
> > -	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> > -		    (struct intel_ip_version *)&display_runtime->ip);
> >   	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
> >   		    &runtime->media.ip);
> >   }
> > @@ -575,6 +572,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> >   	struct intel_device_info *info;
> >   	struct intel_runtime_info *runtime;
> >   	struct intel_display_runtime_info *display_runtime;
> > +	u16 ver, rel, step;
> >   	/* Setup the write-once "constant" device info */
> >   	info = mkwrite_device_info(i915);
> > @@ -585,11 +583,18 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> >   	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
> >   	/* Probe display support */
> > -	info->display = intel_display_device_probe(device_id);
> > +	info->display = intel_display_device_probe(i915, info->has_gmd_id,
> > +						   &ver, &rel, &step);
> >   	if (info->display) {
> >   		display_runtime = DISPLAY_RUNTIME_INFO(i915);
> >   		memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime,
> >   		       sizeof(*display_runtime));
> > +
> > +		if (info->has_gmd_id) {
> > +			display_runtime->ip.ver = ver;
> > +			display_runtime->ip.rel = rel;
> > +			display_runtime->ip.step = step;
> > +		}
> >   	} else {
> >   		info->display = &no_display;
> >   	}
> 
> 
> Why not embed display stuff into some intel_display_info_create(i915) ?
> It could be one tiny step further in separating display from i915.
> It could also allow write ver, rel, step directly into runtime instead of
> passing them via pointer to local vars and copying.

There might definitely be some further refactoring in the future, but at
least as things stand now, the device info (including the default values
for the runtime-modified items) is a driver-wide read-only constant
structure.  We always need to copy the __runtime (for device info) and
__runtime_defaults (for display device info) into a per-device structure
before updating it.  If we didn't do that, probing one device would find
up changing a shared structure that other devices are trying to use,
which would be bad (e.g., if you had two DG2 cards plugged into the same
system that had different fusing).


Matt

> 
> Regards
> Andrzej

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Move display identification/probing under display/
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
                   ` (4 preceding siblings ...)
  2023-05-18  3:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
@ 2023-05-18  4:34 ` Patchwork
  2023-05-18  4:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-05-18  4:34 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: i915: Move display identification/probing under display/
URL   : https://patchwork.freedesktop.org/series/117931/
State : warning

== Summary ==

Error: dim checkpatch failed
9c8f732467ae drm/i915/display: Move display device info to header under display/
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:14: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#14: 
new file mode 100644

-:31: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop
#31: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13:
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+	/* Keep in alphabetical order */ \
+	func(cursor_needs_physical); \
+	func(has_cdclk_crawl); \
+	func(has_cdclk_squash); \
+	func(has_ddi); \
+	func(has_dp_mst); \
+	func(has_dsb); \
+	func(has_fpga_dbg); \
+	func(has_gmch); \
+	func(has_hotplug); \
+	func(has_hti); \
+	func(has_ipc); \
+	func(has_overlay); \
+	func(has_psr); \
+	func(has_psr_hw_tracking); \
+	func(overlay_needs_physical); \
+	func(supports_tv);

-:31: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'func' - possible side-effects?
#31: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13:
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+	/* Keep in alphabetical order */ \
+	func(cursor_needs_physical); \
+	func(has_cdclk_crawl); \
+	func(has_cdclk_squash); \
+	func(has_ddi); \
+	func(has_dp_mst); \
+	func(has_dsb); \
+	func(has_fpga_dbg); \
+	func(has_gmch); \
+	func(has_hotplug); \
+	func(has_hti); \
+	func(has_ipc); \
+	func(has_overlay); \
+	func(has_psr); \
+	func(has_psr_hw_tracking); \
+	func(overlay_needs_physical); \
+	func(supports_tv);

-:31: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#31: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13:
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+	/* Keep in alphabetical order */ \
+	func(cursor_needs_physical); \
+	func(has_cdclk_crawl); \
+	func(has_cdclk_squash); \
+	func(has_ddi); \
+	func(has_dp_mst); \
+	func(has_dsb); \
+	func(has_fpga_dbg); \
+	func(has_gmch); \
+	func(has_hotplug); \
+	func(has_hti); \
+	func(has_ipc); \
+	func(has_overlay); \
+	func(has_psr); \
+	func(has_psr_hw_tracking); \
+	func(overlay_needs_physical); \
+	func(supports_tv);

total: 1 errors, 2 warnings, 1 checks, 127 lines checked
133ee53cfbb9 drm/i915: Convert INTEL_INFO()->display to a pointer
-:225: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#225: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:39:
+#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display->pipe_offsets[(pipe)] - \

-:226: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#226: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:40:
+					      INTEL_INFO(dev_priv)->display->pipe_offsets[PIPE_A] + \

-:230: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#230: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:42:
+#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display->trans_offsets[(tran)] - \

-:231: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#231: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:43:
+					      INTEL_INFO(dev_priv)->display->trans_offsets[TRANSCODER_A] + \

-:235: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#235: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:45:
+#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display->cursor_offsets[(pipe)] - \

-:236: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#236: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:46:
+					      INTEL_INFO(dev_priv)->display->cursor_offsets[PIPE_A] + \

-:1192: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#1192: FILE: drivers/gpu/drm/i915/i915_pci.c:844:
+	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \

-:1724: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#1724: FILE: drivers/gpu/drm/i915/intel_device_info.c:141:
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))

total: 0 errors, 7 warnings, 1 checks, 1602 lines checked
49bdae529172 drm/i915/display: Move display runtime info to display structure
-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#60: FILE: drivers/gpu/drm/i915/display/intel_display.h:108:
+#define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')

-:78: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#78: FILE: drivers/gpu/drm/i915/display/intel_display.h:232:
+		for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))

-:186: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns
#186: FILE: drivers/gpu/drm/i915/i915_drv.h:208:
+	struct intel_display_runtime_info __display_runtime; /* Access with DISPLAY_RUNTIME_INFO() */

-:223: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#223: FILE: drivers/gpu/drm/i915/i915_drv.h:836:
+#define HAS_TRANSCODER(i915, trans)	 ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)

-:706: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#706: FILE: drivers/gpu/drm/i915/i915_pci.c:1114:
+	.__runtime.has_dsc = 1, \

total: 0 errors, 4 warnings, 1 checks, 1017 lines checked
2fdf97b92a44 drm/i915/display: Make display responsible for probing its own IP
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

-:439: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#439: FILE: drivers/gpu/drm/i915/display/intel_display_device.c:400:
+	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \

-:529: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#529: FILE: drivers/gpu/drm/i915/display/intel_display_device.c:490:
+	.__runtime.has_dsc = 1, \

total: 0 errors, 3 warnings, 0 checks, 1854 lines checked
1c665df223ac drm/i915/display: Handle GMD_ID identification in display code
-:103: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#103: FILE: drivers/gpu/drm/i915/display/intel_display_device.c:742:
+			return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;

total: 0 errors, 1 warnings, 0 checks, 156 lines checked



^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Move display identification/probing under display/
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
                   ` (5 preceding siblings ...)
  2023-05-18  4:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Move display identification/probing under display/ Patchwork
@ 2023-05-18  4:34 ` Patchwork
  2023-05-18  4:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2023-05-18 15:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  8 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-05-18  4:34 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: i915: Move display identification/probing under display/
URL   : https://patchwork.freedesktop.org/series/117931/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: Move display identification/probing under display/
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
                   ` (6 preceding siblings ...)
  2023-05-18  4:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-05-18  4:44 ` Patchwork
  2023-05-18 15:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  8 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-05-18  4:44 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 6075 bytes --]

== Series Details ==

Series: i915: Move display identification/probing under display/
URL   : https://patchwork.freedesktop.org/series/117931/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13162 -> Patchwork_117931v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/index.html

Participating hosts (38 -> 36)
------------------------------

  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_117931v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@hangcheck:
    - bat-adls-5:         [PASS][1] -> [DMESG-WARN][2] ([i915#5591])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-adls-5/igt@i915_selftest@live@hangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-adls-5/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-2:         [PASS][3] -> [DMESG-WARN][4] ([i915#6367])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-rpls-2/igt@i915_selftest@live@slpc.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
    - bat-rpls-1:         NOTRUN -> [DMESG-WARN][5] ([i915#6367])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rpls-1/igt@i915_selftest@live@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-rpls-1:         NOTRUN -> [ABORT][6] ([i915#6687] / [i915#7978])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - bat-dg2-11:         NOTRUN -> [SKIP][7] ([i915#7828])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-dg2-11/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@read-crc:
    - bat-dg2-11:         NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-dg2-11/igt@kms_pipe_crc_basic@read-crc.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [DMESG-FAIL][9] ([i915#5334]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_lrc:
    - bat-dg2-11:         [INCOMPLETE][11] ([i915#7609] / [i915#7913]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@reset:
    - bat-rpls-1:         [ABORT][13] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-rpls-1/igt@i915_selftest@live@reset.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rpls-1/igt@i915_selftest@live@reset.html

  
#### Warnings ####

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rplp-1:         [SKIP][15] ([i915#3555] / [i915#4579]) -> [ABORT][16] ([i915#4579] / [i915#8260])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
  [i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
  [i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384


Build changes
-------------

  * Linux: CI_DRM_13162 -> Patchwork_117931v1

  CI-20190529: 20190529
  CI_DRM_13162: a3c32d9f10512cce402635651340a8adff36e6ce @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7294: e1ab60dc90fc49f6b2ec1b37f14b021e59455e73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_117931v1: a3c32d9f10512cce402635651340a8adff36e6ce @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

eed93600b504 drm/i915/display: Handle GMD_ID identification in display code
ab6d7cf504d9 drm/i915/display: Make display responsible for probing its own IP
003ed3b971a6 drm/i915/display: Move display runtime info to display structure
779e87f8d1d5 drm/i915: Convert INTEL_INFO()->display to a pointer
38c01f5eccbd drm/i915/display: Move display device info to header under display/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/index.html

[-- Attachment #2: Type: text/html, Size: 6997 bytes --]

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Move display identification/probing under display/
  2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
                   ` (7 preceding siblings ...)
  2023-05-18  4:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-05-18 15:39 ` Patchwork
  8 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-05-18 15:39 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 11812 bytes --]

== Series Details ==

Series: i915: Move display identification/probing under display/
URL   : https://patchwork.freedesktop.org/series/117931/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13162_full -> Patchwork_117931v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (7 -> 8)
------------------------------

  Additional (1): shard-rkl0 

Known issues
------------

  Here are the changes found in Patchwork_117931v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_barrier_race@remote-request@rcs0:
    - shard-apl:          [PASS][1] -> [ABORT][2] ([i915#7461] / [i915#8190])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-apl2/igt@gem_barrier_race@remote-request@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-apl3/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_pread@exhaustion:
    - shard-glk:          NOTRUN -> [WARN][5] ([i915#2658])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk4/igt@gem_pread@exhaustion.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-apl:          [PASS][6] -> [ABORT][7] ([i915#5566])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-apl4/igt@gen9_exec_parse@allowed-single.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-apl7/igt@gen9_exec_parse@allowed-single.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk4/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-glk:          NOTRUN -> [SKIP][9] ([fdo#109271]) +41 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk4/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-snb:          NOTRUN -> [SKIP][10] ([fdo#109271]) +13 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-snb7/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][11] ([i915#7862]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk4/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4579]) +9 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-snb4/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-1.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-glk:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#658])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk4/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  
#### Possible fixes ####

  * igt@gem_barrier_race@remote-request@rcs0:
    - shard-glk:          [ABORT][15] ([i915#7461] / [i915#8211]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-glk3/igt@gem_barrier_race@remote-request@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk4/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_exec_endless@dispatch@vecs0:
    - {shard-tglu}:       [TIMEOUT][17] ([i915#3778]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-tglu-4/igt@gem_exec_endless@dispatch@vecs0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-tglu-6/igt@gem_exec_endless@dispatch@vecs0.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - {shard-dg1}:        [TIMEOUT][19] ([i915#5493]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - {shard-rkl}:        [SKIP][21] ([i915#1937] / [i915#4579]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-rkl-4/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
    - {shard-dg1}:        [FAIL][23] ([i915#3591]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - {shard-rkl}:        [SKIP][25] ([i915#1397]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-rkl-2/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@i915_suspend@basic-s3-without-i915:
    - {shard-rkl}:        [FAIL][27] ([fdo#103375]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-rkl-7/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [FAIL][29] ([i915#2346]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [FAIL][31] ([i915#2346]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][33] ([i915#79]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][35] ([i915#2122]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html

  * igt@perf_pmu@idle@rcs0:
    - {shard-dg1}:        [FAIL][37] ([i915#4349]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/shard-dg1-14/igt@perf_pmu@idle@rcs0.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/shard-dg1-16/igt@perf_pmu@idle@rcs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2876]: https://gitlab.freedesktop.org/drm/intel/issues/2876
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6786]: https://gitlab.freedesktop.org/drm/intel/issues/6786
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7862]: https://gitlab.freedesktop.org/drm/intel/issues/7862
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
  [i915#8190]: https://gitlab.freedesktop.org/drm/intel/issues/8190
  [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8311]: https://gitlab.freedesktop.org/drm/intel/issues/8311


Build changes
-------------

  * Linux: CI_DRM_13162 -> Patchwork_117931v1

  CI-20190529: 20190529
  CI_DRM_13162: a3c32d9f10512cce402635651340a8adff36e6ce @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7294: e1ab60dc90fc49f6b2ec1b37f14b021e59455e73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_117931v1: a3c32d9f10512cce402635651340a8adff36e6ce @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/index.html

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^ permalink raw reply	[flat|nested] 21+ messages in thread

end of thread, other threads:[~2023-05-22 19:10 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-05-18  3:17 [Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/ Matt Roper
2023-05-18  3:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header " Matt Roper
2023-05-18  5:19   ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
2023-05-18  6:18   ` [Intel-gfx] " Andrzej Hajda
2023-05-18  3:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
2023-05-18  5:24   ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
2023-05-18  6:44   ` [Intel-gfx] " Andrzej Hajda
2023-05-18  3:18 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Move display runtime info to display structure Matt Roper
2023-05-18  7:56   ` Andrzej Hajda
2023-05-22 16:41     ` Matt Roper
2023-05-18  3:18 ` [Intel-gfx] [PATCH 4/5] drm/i915/display: Make display responsible for probing its own IP Matt Roper
2023-05-18 10:01   ` Andrzej Hajda
2023-05-18  3:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
2023-05-18  7:53   ` kernel test robot
2023-05-18  9:28   ` kernel test robot
2023-05-18 10:44   ` Andrzej Hajda
2023-05-22 19:10     ` Matt Roper
2023-05-18  4:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Move display identification/probing under display/ Patchwork
2023-05-18  4:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-18  4:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-05-18 15:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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