[Intel-gfx] [PATCH v3 0/6] Panel replay phase1 implementation

[Intel-gfx] [PATCH v3 0/6] Panel replay phase1 implementation

[Animesh Manna]

Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.

These patches are basic enablement patches added on top of
existing psr framework to enable full-screen live active frame
update mode of panel replay. Panel replay also can be enabled
in selective update mode which will be enabled in a incremental
approach.

As per current design panel replay priority is higher than psr.
intel_dp->psr.pr_enabled flag indicate panel replay is enabled.
intel_dp->psr.pr_enabled + intel_dp->psr.psr2_enabled indicates
panel replay is enabled in selective update mode.
intel_dp->psr.pr_enabled + intel_dp->psr.psr2_enabled +
intel_psr.selective_fetch enabled indicates panel replay is
enabled in selective update mode with selective fetch.
PSR replated flags remain same like before.

Note: The patches are not tested due to unavailability of monitor.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (5):
  drm/panelreplay: dpcd register definition for panelreplay
  drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
  drm/i915/panelreplay: Initializaton and compute config for panel
    replay
  drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
  drm/i915/panelreplay: enable/disable panel replay

Jouni Högander (1):
  drm/i915/psr: Move psr specific dpcd init into own function

 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   9 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  44 ++++-
 drivers/gpu/drm/i915/display/intel_psr.c      | 158 +++++++++++++-----
 include/drm/display/drm_dp.h                  |  11 ++
 5 files changed, 168 insertions(+), 55 deletions(-)

-- 
2.29.0

[Intel-gfx] [PATCH v3 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Animesh Manna]

DPCD register definition added to check and enable panel replay
capability of the sink.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 include/drm/display/drm_dp.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 02f2ac4dd2df..c48696266d23 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -543,6 +543,10 @@
 /* DFP Capability Extension */
 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
 
+#define DP_PANEL_REPLAY_CAP                 0x0b0
+# define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
+# define DP_PR_SELECTIVE_UPDATE_SUPPORT     (1 << 1)
+
 /* Link Configuration */
 #define	DP_LINK_BW_SET		            0x100
 # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
@@ -716,6 +720,13 @@
 #define DP_BRANCH_DEVICE_CTRL		    0x1a1
 # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
 
+#define PANEL_REPLAY_CONFIG                 0x1b0
+# define DP_PANEL_REPLAY_ENABLE             (1 << 0)
+# define DP_PR_UNRECOVERABLE_ERROR          (1 << 3)
+# define DP_PR_RFB_STORAGE_ERROR            (1 << 4)
+# define DP_PR_ACTIVE_FRAME_CRC_ERROR       (1 << 5)
+# define DP_PR_SELECTIVE_UPDATE_ENABLE      (1 << 6)
+
 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.29.0

Re: [Intel-gfx] [PATCH v3 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Hogander, Jouni]

On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> DPCD register definition added to check and enable panel replay
> capability of the sink.

I think this patch shoud go to dri-devel@lists.freedesktop.org as well.

BR,

Jouni Högander

> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  include/drm/display/drm_dp.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h
> b/include/drm/display/drm_dp.h
> index 02f2ac4dd2df..c48696266d23 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -543,6 +543,10 @@
>  /* DFP Capability Extension */
>  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT    0x0a3   /* 2.0 */
>  
> +#define DP_PANEL_REPLAY_CAP                 0x0b0
> +# define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
> +# define DP_PR_SELECTIVE_UPDATE_SUPPORT     (1 << 1)
> +
>  /* Link Configuration */
>  #define        DP_LINK_BW_SET                      0x100
>  # define DP_LINK_RATE_TABLE                0x00    /* eDP 1.4 */
> @@ -716,6 +720,13 @@
>  #define DP_BRANCH_DEVICE_CTRL              0x1a1
>  # define DP_BRANCH_DEVICE_IRQ_HPD          (1 << 0)
>  
> +#define PANEL_REPLAY_CONFIG                 0x1b0
> +# define DP_PANEL_REPLAY_ENABLE             (1 << 0)
> +# define DP_PR_UNRECOVERABLE_ERROR          (1 << 3)
> +# define DP_PR_RFB_STORAGE_ERROR            (1 << 4)
> +# define DP_PR_ACTIVE_FRAME_CRC_ERROR       (1 << 5)
> +# define DP_PR_SELECTIVE_UPDATE_ENABLE      (1 << 6)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET                    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2

Re: [Intel-gfx] [PATCH v3 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Manna, Animesh]

Hi,


> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, July 31, 2023 11:50 AM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: Re: [PATCH v3 1/6] drm/panelreplay: dpcd register definition for
> panelreplay
> 
> On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> > DPCD register definition added to check and enable panel replay
> > capability of the sink.
> 
> I think this patch shoud go to dri-devel@lists.freedesktop.org as well.
> 

Sure, will add in next version review.

Regards,
Animesh

> BR,
> 
> Jouni Högander
> 
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  include/drm/display/drm_dp.h | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/include/drm/display/drm_dp.h
> > b/include/drm/display/drm_dp.h index 02f2ac4dd2df..c48696266d23
> 100644
> > --- a/include/drm/display/drm_dp.h
> > +++ b/include/drm/display/drm_dp.h
> > @@ -543,6 +543,10 @@
> >  /* DFP Capability Extension */
> >  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT    0x0a3   /* 2.0 */
> >
> > +#define DP_PANEL_REPLAY_CAP                 0x0b0 # define
> > +DP_PANEL_REPLAY_SUPPORT            (1 << 0) # define
> > +DP_PR_SELECTIVE_UPDATE_SUPPORT     (1 << 1)
> > +
> >  /* Link Configuration */
> >  #define        DP_LINK_BW_SET                      0x100
> >  # define DP_LINK_RATE_TABLE                0x00    /* eDP 1.4 */ @@
> > -716,6 +720,13 @@
> >  #define DP_BRANCH_DEVICE_CTRL              0x1a1
> >  # define DP_BRANCH_DEVICE_IRQ_HPD          (1 << 0)
> >
> > +#define PANEL_REPLAY_CONFIG                 0x1b0 # define
> > +DP_PANEL_REPLAY_ENABLE             (1 << 0) # define
> > +DP_PR_UNRECOVERABLE_ERROR          (1 << 3) # define
> > +DP_PR_RFB_STORAGE_ERROR            (1 << 4) # define
> > +DP_PR_ACTIVE_FRAME_CRC_ERROR       (1 << 5) # define
> > +DP_PR_SELECTIVE_UPDATE_ENABLE      (1 << 6)
> > +
> >  #define DP_PAYLOAD_ALLOCATE_SET                    0x1c0
> >  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
> >  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2

[Intel-gfx] [PATCH v3 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro

[Animesh Manna]

Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY()
macro to check for panel replay capability.

v1: Initial version.
v2: DISPLAY_VER() removed as HAS_DP20() is having platform check. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 3324bd453ca7..53bc8f972a26 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -60,6 +60,7 @@ struct drm_printer;
 #define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)
 #define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)
 #define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)
+#define HAS_PANEL_REPLAY(dev_priv)	(HAS_DP20(dev_priv))
 #define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)
 #define HAS_SAGV(i915)			(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
-- 
2.29.0

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro

[Hogander, Jouni]

On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> Platforms having Display 13 and above will support panel
> replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY()
> macro to check for panel replay capability.
> 
> v1: Initial version.
> v2: DISPLAY_VER() removed as HAS_DP20() is having platform check.
> [Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 3324bd453ca7..53bc8f972a26 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -60,6 +60,7 @@ struct drm_printer;
>  #define HAS_MSO(i915)                  (DISPLAY_VER(i915) >= 12)
>  #define HAS_OVERLAY(i915)              (DISPLAY_INFO(i915)-
> >has_overlay)
>  #define HAS_PSR(i915)                  (DISPLAY_INFO(i915)->has_psr)
> +#define HAS_PANEL_REPLAY(dev_priv)     (HAS_DP20(dev_priv))

I'm beginning to think this macro is not needed at all. DP PR is part
of DP20 specification -> you can use HAS_DP20 directly?

BR,

Jouni Högander

>  #define HAS_PSR_HW_TRACKING(i915)      (DISPLAY_INFO(i915)-
> >has_psr_hw_tracking)
>  #define HAS_PSR2_SEL_FETCH(i915)       (DISPLAY_VER(i915) >= 12)
>  #define HAS_SAGV(i915)                 (DISPLAY_VER(i915) >= 9 &&
> !IS_LP(i915))

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, July 31, 2023 11:57 AM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: Re: [PATCH v3 2/6] drm/i915/panelreplay: Added
> HAS_PANEL_REPLAY() macro
> 
> On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> > Platforms having Display 13 and above will support panel replay
> > feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY() macro to check
> > for panel replay capability.
> >
> > v1: Initial version.
> > v2: DISPLAY_VER() removed as HAS_DP20() is having platform check.
> > [Jouni]
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 3324bd453ca7..53bc8f972a26 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -60,6 +60,7 @@ struct drm_printer;
> >  #define HAS_MSO(i915)                  (DISPLAY_VER(i915) >= 12)
> >  #define HAS_OVERLAY(i915)              (DISPLAY_INFO(i915)-
> > >has_overlay)
> >  #define HAS_PSR(i915)                  (DISPLAY_INFO(i915)->has_psr)
> > +#define HAS_PANEL_REPLAY(dev_priv)     (HAS_DP20(dev_priv))
> 
> I'm beginning to think this macro is not needed at all. DP PR is part of DP20
> specification -> you can use HAS_DP20 directly?

Yes, I tried to follow how things are done for PSR. We may need a feature flag to enable/disable from source side.
Please let me know your view on this.

Regards,
Animesh

> 
> BR,
> 
> Jouni Högander
> 
> >  #define HAS_PSR_HW_TRACKING(i915)      (DISPLAY_INFO(i915)-
> > >has_psr_hw_tracking)
> >  #define HAS_PSR2_SEL_FETCH(i915)       (DISPLAY_VER(i915) >= 12)
> >  #define HAS_SAGV(i915)                 (DISPLAY_VER(i915) >= 9 &&
> > !IS_LP(i915))

[Intel-gfx] [PATCH v3 3/6] drm/i915/psr: Move psr specific dpcd init into own function

[Animesh Manna]

From: Jouni Högander <jouni.hogander@intel.com>

This patch is preparing adding panel replay specific dpcd init.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 39 +++++++++++++-----------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 04ab034a8d57..9fbcb4b93f11 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -472,27 +472,22 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	intel_dp->psr.su_y_granularity = y;
 }
 
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp)
 {
-	struct drm_i915_private *dev_priv =
+	struct drm_i915_private *i915 =
 		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 
-	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
-			 sizeof(intel_dp->psr_dpcd));
-
-	if (!intel_dp->psr_dpcd[0])
-		return;
-	drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
+	drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n",
 		    intel_dp->psr_dpcd[0]);
 
 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "PSR support not currently available for this panel\n");
 		return;
 	}
 
 	if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "Panel lacks power state control, PSR cannot be enabled\n");
 		return;
 	}
@@ -501,7 +496,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	intel_dp->psr.sink_sync_latency =
 		intel_dp_get_sink_sync_latency(intel_dp);
 
-	if (DISPLAY_VER(dev_priv) >= 9 &&
+	if (DISPLAY_VER(i915) >= 9 &&
 	    (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 		bool y_req = intel_dp->psr_dpcd[1] &
 			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
@@ -519,14 +514,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 		 * GTC first.
 		 */
 		intel_dp->psr.sink_psr2_support = y_req && alpm;
-		drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
+		drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",
 			    intel_dp->psr.sink_psr2_support ? "" : "not ");
+	}
+}
 
-		if (intel_dp->psr.sink_psr2_support) {
-			intel_dp->psr.colorimetry_support =
-				intel_dp_get_colorimetry_status(intel_dp);
-			intel_dp_get_su_granularity(intel_dp);
-		}
+void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+{
+	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
+			 sizeof(intel_dp->psr_dpcd));
+
+	if (intel_dp->psr_dpcd[0])
+		_psr_init_dpcd(intel_dp);
+	/* TODO: Add PR case here */
+
+	if (intel_dp->psr.sink_psr2_support) {
+		intel_dp->psr.colorimetry_support =
+			intel_dp_get_colorimetry_status(intel_dp);
+		intel_dp_get_su_granularity(intel_dp);
 	}
 }
 
-- 
2.29.0

[Intel-gfx] [PATCH v3 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Animesh Manna]

Modify existing PSR implementation to enable panel replay feature of DP 2.0
which is similar to PSR feature of EDP panel. There is different DPCD
address to check panel capability compare to PSR and vsc sdp header
is different.

v1: Initial version.
v2:
- Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check. [Jouni]
- Code restructured around intel_panel_replay_init
and renamed to intel_panel_replay_init_dpcd. [Jouni]
- Remove the initial code modification around has_psr2 flag. [Jouni]
- Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
enable in intel_psr_post_plane_update. [Jouni]
v3:
- Initialize both psr and panel-replay. [Jouni]
- Initialize both panel replay and psr if detected. [Jouni]
- Refactoring psr function by introducing _psr_compute_config(). [Jouni]
- Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
- Enable panel replay dpcd initialization in a separate patch. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  8 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 44 ++++++++--
 drivers/gpu/drm/i915/display/intel_psr.c      | 88 +++++++++++++------
 3 files changed, 104 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5c..1ff7e6c03b44 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1202,6 +1202,7 @@ struct intel_crtc_state {
 	bool has_psr2;
 	bool enable_psr2_sel_fetch;
 	bool req_psr2_sdp_prior_scanline;
+	bool has_pr;
 	bool wm_level_disabled;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
@@ -1693,6 +1694,8 @@ struct intel_psr {
 	bool irq_aux_error;
 	u16 su_w_granularity;
 	u16 su_y_granularity;
+	bool source_panel_replay_support;
+	bool sink_panel_replay_support;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
@@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp)
 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
 			   (intel_dp)->psr.source_support)
 
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+			  (intel_dp)->psr.source_panel_replay_support)
+
 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
 {
 	if (!intel_encoder_is_dp(encoder))
 		return false;
 
-	return CAN_PSR(enc_to_intel_dp(encoder));
+	return CAN_PSR(enc_to_intel_dp(encoder)) || CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
 }
 
 static inline struct intel_digital_port *
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 03675620e3ea..0ba231ee6e34 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1946,12 +1946,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	/*
-	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
-	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-	 * Colorimetry Format indication.
-	 */
-	vsc->revision = 0x5;
+	if (crtc_state->has_pr) {
+		/*
+		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+		 * Encoding/Colorimetry Format indication.
+		 */
+		vsc->revision = 0x7;
+	} else {
+		/*
+		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+		 * Colorimetry Format indication.
+		 */
+		vsc->revision = 0x5;
+	}
+
 	vsc->length = 0x13;
 
 	/* DP 1.4a spec, Table 2-120 */
@@ -2060,6 +2070,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
 			vsc->revision = 0x4;
 			vsc->length = 0xe;
 		}
+	} else if (crtc_state->has_pr) {
+		if (intel_dp->psr.colorimetry_support &&
+		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+			/* [Panel Replay with colorimetry info] */
+			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+							 vsc);
+		} else {
+			/*
+			 * [Panel Replay without colorimetry info]
+			 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+			 * VSC SDP supporting 3D stereo + Panel Replay.
+			 */
+			vsc->revision = 0x6;
+			vsc->length = 0x10;
+		}
 	} else {
 		/*
 		 * [PSR1]
@@ -3354,10 +3379,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
 	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
 
 	/*
-	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
-	 * per DP 1.4a spec.
+	 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
+	 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
+	 * Encoding/Colorimetry Format as per DP 2.0 spec.
 	 */
-	if (vsc->revision != 0x5)
+	if (vsc->revision != 0x5 || vsc->revision != 0x7)
 		goto out;
 
 	/* VSC SDP Payload for DB16 through DB18 */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9fbcb4b93f11..7508e6c967e2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -472,6 +472,27 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	intel_dp->psr.su_y_granularity = y;
 }
 
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	u8 pr_dpcd = 0;
+
+	if (!HAS_PANEL_REPLAY(dev_priv))
+		return;
+
+	drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
+
+	if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Panel replay is not supported by panel\n");
+		return;
+	}
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "Panel replay is supported by panel\n");
+	intel_dp->psr.sink_panel_replay_support = true;
+}
+
 static void _psr_init_dpcd(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 =
@@ -521,12 +542,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
 
 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 {
+	_panel_replay_init_dpcd(intel_dp);
+
 	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 			 sizeof(intel_dp->psr_dpcd));
 
 	if (intel_dp->psr_dpcd[0])
 		_psr_init_dpcd(intel_dp);
-	/* TODO: Add PR case here */
 
 	if (intel_dp->psr.sink_psr2_support) {
 		intel_dp->psr.colorimetry_support =
@@ -1207,13 +1229,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	return false;
 }
 
-void intel_psr_compute_config(struct intel_dp *intel_dp,
-			      struct intel_crtc_state *crtc_state,
-			      struct drm_connector_state *conn_state)
+static bool _psr_compute_config(struct intel_dp *intel_dp,
+				struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int psr_setup_time;
 
 	/*
@@ -1221,10 +1241,36 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	 * So if VRR is enabled, do not enable PSR.
 	 */
 	if (crtc_state->vrr.enable)
-		return;
+		return false;
 
 	if (!CAN_PSR(intel_dp))
-		return;
+		return false;
+
+	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+	if (psr_setup_time < 0) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
+			    intel_dp->psr_dpcd[1]);
+		return false;
+	}
+
+	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
+	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "PSR condition failed: PSR setup time (%d us) too long\n",
+			    psr_setup_time);
+		return false;
+	}
+
+	return true;
+}
+
+void intel_psr_compute_config(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
 	if (!psr_global_enabled(intel_dp)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
@@ -1234,7 +1280,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->psr.sink_not_reliable) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR sink implementation is not reliable\n");
-		return;
 	}
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -1243,23 +1288,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 		return;
 	}
 
-	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
-	if (psr_setup_time < 0) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
-			    intel_dp->psr_dpcd[1]);
-		return;
-	}
-
-	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
-	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "PSR condition failed: PSR setup time (%d us) too long\n",
-			    psr_setup_time);
-		return;
-	}
+	if (CAN_PANEL_REPLAY(intel_dp))
+		crtc_state->has_pr = true;
+	else
+		crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state);
 
-	crtc_state->has_psr = true;
 	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
@@ -2699,7 +2732,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	if (!HAS_PSR(dev_priv))
+	if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
 		return;
 
 	/*
@@ -2719,6 +2752,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
 
 	intel_dp->psr.source_support = true;
 
+	if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp))
+		intel_dp->psr.source_panel_replay_support = true;
+
 	/* Set link_standby x link_off defaults */
 	if (DISPLAY_VER(dev_priv) < 12)
 		/* For new platforms up to TGL let's respect VBT back again */
-- 
2.29.0

Re: [Intel-gfx] [PATCH v3 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[kernel test robot]

Hi Animesh,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230728-205902
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230728124609.2911830-5-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v3 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: x86_64-randconfig-x001-20230728 (https://download.01.org/0day-ci/archive/20230728/202307282318.EVEl6EsL-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce: (https://download.01.org/0day-ci/archive/20230728/202307282318.EVEl6EsL-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202307282318.EVEl6EsL-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_dp.c:3386:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
           if (vsc->revision != 0x5 || vsc->revision != 0x7)
               ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
   1 warning generated.


vim +3386 drivers/gpu/drm/i915/display/intel_dp.c

  3361	
  3362	static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
  3363					     struct dp_sdp *sdp, size_t size)
  3364	{
  3365		size_t length = sizeof(struct dp_sdp);
  3366	
  3367		if (size < length)
  3368			return -ENOSPC;
  3369	
  3370		memset(sdp, 0, size);
  3371	
  3372		/*
  3373		 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
  3374		 * VSC SDP Header Bytes
  3375		 */
  3376		sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
  3377		sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
  3378		sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
  3379		sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
  3380	
  3381		/*
  3382		 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
  3383		 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
  3384		 * Encoding/Colorimetry Format as per DP 2.0 spec.
  3385		 */
> 3386		if (vsc->revision != 0x5 || vsc->revision != 0x7)
  3387			goto out;
  3388	
  3389		/* VSC SDP Payload for DB16 through DB18 */
  3390		/* Pixel Encoding and Colorimetry Formats  */
  3391		sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
  3392		sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
  3393	
  3394		switch (vsc->bpc) {
  3395		case 6:
  3396			/* 6bpc: 0x0 */
  3397			break;
  3398		case 8:
  3399			sdp->db[17] = 0x1; /* DB17[3:0] */
  3400			break;
  3401		case 10:
  3402			sdp->db[17] = 0x2;
  3403			break;
  3404		case 12:
  3405			sdp->db[17] = 0x3;
  3406			break;
  3407		case 16:
  3408			sdp->db[17] = 0x4;
  3409			break;
  3410		default:
  3411			MISSING_CASE(vsc->bpc);
  3412			break;
  3413		}
  3414		/* Dynamic Range and Component Bit Depth */
  3415		if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
  3416			sdp->db[17] |= 0x80;  /* DB17[7] */
  3417	
  3418		/* Content Type */
  3419		sdp->db[18] = vsc->content_type & 0x7;
  3420	
  3421	out:
  3422		return length;
  3423	}
  3424	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [Intel-gfx] [PATCH v3 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Hogander, Jouni]

On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> Modify existing PSR implementation to enable panel replay feature of
> DP 2.0
> which is similar to PSR feature of EDP panel. There is different DPCD
> address to check panel capability compare to PSR and vsc sdp header
> is different.
> 
> v1: Initial version.
> v2:
> - Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check.
> [Jouni]
> - Code restructured around intel_panel_replay_init
> and renamed to intel_panel_replay_init_dpcd. [Jouni]
> - Remove the initial code modification around has_psr2 flag. [Jouni]
> - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
> enable in intel_psr_post_plane_update. [Jouni]
> v3:
> - Initialize both psr and panel-replay. [Jouni]
> - Initialize both panel replay and psr if detected. [Jouni]
> - Refactoring psr function by introducing _psr_compute_config().
> [Jouni]
> - Add check for !is_edp while deriving source_panel_replay_support.
> [Jouni]
> - Enable panel replay dpcd initialization in a separate patch.
> [Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  8 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 44 ++++++++--
>  drivers/gpu/drm/i915/display/intel_psr.c      | 88 +++++++++++++----
> --
>  3 files changed, 104 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 731f2ec04d5c..1ff7e6c03b44 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1202,6 +1202,7 @@ struct intel_crtc_state {
>         bool has_psr2;
>         bool enable_psr2_sel_fetch;
>         bool req_psr2_sdp_prior_scanline;
> +       bool has_pr;
>         bool wm_level_disabled;
>         u32 dc3co_exitline;
>         u16 su_y_granularity;
> @@ -1693,6 +1694,8 @@ struct intel_psr {
>         bool irq_aux_error;
>         u16 su_w_granularity;
>         u16 su_y_granularity;
> +       bool source_panel_replay_support;
> +       bool sink_panel_replay_support;
>         u32 dc3co_exitline;
>         u32 dc3co_exit_delay;
>         struct delayed_work dc3co_work;
> @@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp)
>  #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
>                            (intel_dp)->psr.source_support)
>  
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> +                         (intel_dp)-
> >psr.source_panel_replay_support)
> +
>  static inline bool intel_encoder_can_psr(struct intel_encoder
> *encoder)
>  {
>         if (!intel_encoder_is_dp(encoder))
>                 return false;
>  
> -       return CAN_PSR(enc_to_intel_dp(encoder));
> +       return CAN_PSR(enc_to_intel_dp(encoder)) ||
> CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
>  }
>  
>  static inline struct intel_digital_port *
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 03675620e3ea..0ba231ee6e34 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1946,12 +1946,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>         struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> >uapi.crtc);
>         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -       /*
> -        * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> -        * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -        * Colorimetry Format indication.
> -        */
> -       vsc->revision = 0x5;
> +       if (crtc_state->has_pr) {
> +               /*
> +                * Prepare VSC Header for SU as per DP 2.0 spec,
> Table 2-223
> +                * VSC SDP supporting 3D stereo, Panel Replay, and
> Pixel
> +                * Encoding/Colorimetry Format indication.
> +                */
> +               vsc->revision = 0x7;
> +       } else {
> +               /*
> +                * Prepare VSC Header for SU as per DP 1.4 spec,
> Table 2-118
> +                * VSC SDP supporting 3D stereo, PSR2, and Pixel
> Encoding/
> +                * Colorimetry Format indication.
> +                */
> +               vsc->revision = 0x5;
> +       }
> +
>         vsc->length = 0x13;
>  
>         /* DP 1.4a spec, Table 2-120 */
> @@ -2060,6 +2070,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
>                         vsc->revision = 0x4;
>                         vsc->length = 0xe;
>                 }
> +       } else if (crtc_state->has_pr) {
> +               if (intel_dp->psr.colorimetry_support &&
> +                   intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +                       /* [Panel Replay with colorimetry info] */
> +                       intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> +                                                        vsc);
> +               } else {
> +                       /*
> +                        * [Panel Replay without colorimetry info]
> +                        * Prepare VSC Header for SU as per DP 2.0
> spec, Table 2-223
> +                        * VSC SDP supporting 3D stereo + Panel
> Replay.
> +                        */
> +                       vsc->revision = 0x6;
> +                       vsc->length = 0x10;
> +               }
>         } else {
>                 /*
>                  * [PSR1]
> @@ -3354,10 +3379,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const
> struct drm_dp_vsc_sdp *vsc,
>         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
> Bytes */
>  
>         /*
> -        * Only revision 0x5 supports Pixel Encoding/Colorimetry
> Format as
> -        * per DP 1.4a spec.
> +        * Other than revision 0x5 which supports Pixel
> Encoding/Colorimetry
> +        * Format as per DP 1.4a spec, revision 0x7 also supports
> Pixel
> +        * Encoding/Colorimetry Format as per DP 2.0 spec.
>          */
> -       if (vsc->revision != 0x5)
> +       if (vsc->revision != 0x5 || vsc->revision != 0x7)
>                 goto out;
>  
>         /* VSC SDP Payload for DB16 through DB18 */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9fbcb4b93f11..7508e6c967e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -472,6 +472,27 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
>         intel_dp->psr.su_y_granularity = y;
>  }
>  
> +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> +{
> +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +       u8 pr_dpcd = 0;
> +
> +       if (!HAS_PANEL_REPLAY(dev_priv))
> +               return;
> +
> +       drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> +
> +       if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> +               drm_dbg_kms(&dev_priv->drm,
> +                           "Panel replay is not supported by
> panel\n");
> +               return;
> +       }
> +
> +       drm_dbg_kms(&dev_priv->drm,
> +                   "Panel replay is supported by panel\n");
> +       intel_dp->psr.sink_panel_replay_support = true;
> +}
> +
>  static void _psr_init_dpcd(struct intel_dp *intel_dp)
>  {
>         struct drm_i915_private *i915 =
> @@ -521,12 +542,13 @@ static void _psr_init_dpcd(struct intel_dp
> *intel_dp)
>  
>  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  {
> +       _panel_replay_init_dpcd(intel_dp);
> +
>         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
>                          sizeof(intel_dp->psr_dpcd));
>  
>         if (intel_dp->psr_dpcd[0])
>                 _psr_init_dpcd(intel_dp);
> -       /* TODO: Add PR case here */
>  
>         if (intel_dp->psr.sink_psr2_support) {
>                 intel_dp->psr.colorimetry_support =
> @@ -1207,13 +1229,11 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
>         return false;
>  }
>  
> -void intel_psr_compute_config(struct intel_dp *intel_dp,
> -                             struct intel_crtc_state *crtc_state,
> -                             struct drm_connector_state *conn_state)
> +static bool _psr_compute_config(struct intel_dp *intel_dp,
> +                               struct intel_crtc_state *crtc_state)
>  {
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -       const struct drm_display_mode *adjusted_mode =
> -               &crtc_state->hw.adjusted_mode;
> +       const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>         int psr_setup_time;
>  
>         /*
> @@ -1221,10 +1241,36 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>          * So if VRR is enabled, do not enable PSR.
>          */
>         if (crtc_state->vrr.enable)
> -               return;
> +               return false;
>  
>         if (!CAN_PSR(intel_dp))
> -               return;
> +               return false;
> +
> +       psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> +       if (psr_setup_time < 0) {
> +               drm_dbg_kms(&dev_priv->drm,
> +                           "PSR condition failed: Invalid PSR setup
> time (0x%02x)\n",
> +                           intel_dp->psr_dpcd[1]);
> +               return false;
> +       }
> +
> +       if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> +           adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay
> - 1) {
> +               drm_dbg_kms(&dev_priv->drm,
> +                           "PSR condition failed: PSR setup time (%d
> us) too long\n",
> +                           psr_setup_time);
> +               return false;
> +       }
> +
> +       return true;
> +}
> +
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> +                             struct intel_crtc_state *crtc_state,
> +                             struct drm_connector_state *conn_state)
> +{
> +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +       const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>  
>         if (!psr_global_enabled(intel_dp)) {
>                 drm_dbg_kms(&dev_priv->drm, "PSR disabled by
> flag\n");
> @@ -1234,7 +1280,6 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>         if (intel_dp->psr.sink_not_reliable) {
>                 drm_dbg_kms(&dev_priv->drm,
>                             "PSR sink implementation is not
> reliable\n");
> -               return;
>         }
>  
>         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -1243,23 +1288,11 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>                 return;
>         }
>  
> -       psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> -       if (psr_setup_time < 0) {
> -               drm_dbg_kms(&dev_priv->drm,
> -                           "PSR condition failed: Invalid PSR setup
> time (0x%02x)\n",
> -                           intel_dp->psr_dpcd[1]);
> -               return;
> -       }
> -
> -       if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> -           adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay
> - 1) {
> -               drm_dbg_kms(&dev_priv->drm,
> -                           "PSR condition failed: PSR setup time (%d
> us) too long\n",
> -                           psr_setup_time);
> -               return;
> -       }
> +       if (CAN_PANEL_REPLAY(intel_dp))
> +               crtc_state->has_pr = true;
> +       else
> +               crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
>  
> -       crtc_state->has_psr = true;
>         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> crtc_state);
>  
>         crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> @@ -2699,7 +2732,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
>         struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -       if (!HAS_PSR(dev_priv))
> +       if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
>                 return;
>  
>         /*
> @@ -2719,6 +2752,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
>  
>         intel_dp->psr.source_support = true;
>  
> +       if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp))
> +               intel_dp->psr.source_panel_replay_support = true;

I don't think it's correct to have both intel_dp->psr.source_support
and intel_dp->psr.source_panel_replay_support set. E.g.:

	if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp))
		intel_dp->psr.source_panel_replay_support = true;
	else
		intel_dp->psr.source_support = true;

BR,

Jouni Högander

>  
> +       if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp))
> +               intel_dp->psr.source_panel_replay_support = true;
> +
>         /* Set link_standby x link_off defaults */
>         if (DISPLAY_VER(dev_priv) < 12)
>                 /* For new platforms up to TGL let's respect VBT back
> again */

Re: [Intel-gfx] [PATCH v3 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Hogander, Jouni]

On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> Modify existing PSR implementation to enable panel replay feature of
> DP 2.0
> which is similar to PSR feature of EDP panel. There is different DPCD
> address to check panel capability compare to PSR and vsc sdp header
> is different.
> 
> v1: Initial version.
> v2:
> - Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check.
> [Jouni]
> - Code restructured around intel_panel_replay_init
> and renamed to intel_panel_replay_init_dpcd. [Jouni]
> - Remove the initial code modification around has_psr2 flag. [Jouni]
> - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
> enable in intel_psr_post_plane_update. [Jouni]
> v3:
> - Initialize both psr and panel-replay. [Jouni]
> - Initialize both panel replay and psr if detected. [Jouni]
> - Refactoring psr function by introducing _psr_compute_config().
> [Jouni]
> - Add check for !is_edp while deriving source_panel_replay_support.
> [Jouni]
> - Enable panel replay dpcd initialization in a separate patch.
> [Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  8 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 44 ++++++++--
>  drivers/gpu/drm/i915/display/intel_psr.c      | 88 +++++++++++++----
> --
>  3 files changed, 104 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 731f2ec04d5c..1ff7e6c03b44 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1202,6 +1202,7 @@ struct intel_crtc_state {
>         bool has_psr2;
>         bool enable_psr2_sel_fetch;
>         bool req_psr2_sdp_prior_scanline;
> +       bool has_pr;
>         bool wm_level_disabled;
>         u32 dc3co_exitline;
>         u16 su_y_granularity;
> @@ -1693,6 +1694,8 @@ struct intel_psr {
>         bool irq_aux_error;
>         u16 su_w_granularity;
>         u16 su_y_granularity;
> +       bool source_panel_replay_support;
> +       bool sink_panel_replay_support;
>         u32 dc3co_exitline;
>         u32 dc3co_exit_delay;
>         struct delayed_work dc3co_work;
> @@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp)
>  #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
>                            (intel_dp)->psr.source_support)
>  
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> +                         (intel_dp)-
> >psr.source_panel_replay_support)
> +
>  static inline bool intel_encoder_can_psr(struct intel_encoder
> *encoder)
>  {
>         if (!intel_encoder_is_dp(encoder))
>                 return false;
>  
> -       return CAN_PSR(enc_to_intel_dp(encoder));
> +       return CAN_PSR(enc_to_intel_dp(encoder)) ||
> CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
>  }
>  
>  static inline struct intel_digital_port *
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 03675620e3ea..0ba231ee6e34 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1946,12 +1946,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>         struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> >uapi.crtc);
>         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -       /*
> -        * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> -        * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -        * Colorimetry Format indication.
> -        */
> -       vsc->revision = 0x5;
> +       if (crtc_state->has_pr) {
> +               /*
> +                * Prepare VSC Header for SU as per DP 2.0 spec,
> Table 2-223
> +                * VSC SDP supporting 3D stereo, Panel Replay, and
> Pixel
> +                * Encoding/Colorimetry Format indication.
> +                */
> +               vsc->revision = 0x7;
> +       } else {
> +               /*
> +                * Prepare VSC Header for SU as per DP 1.4 spec,
> Table 2-118
> +                * VSC SDP supporting 3D stereo, PSR2, and Pixel
> Encoding/
> +                * Colorimetry Format indication.
> +                */
> +               vsc->revision = 0x5;
> +       }
> +
>         vsc->length = 0x13;
>  
>         /* DP 1.4a spec, Table 2-120 */
> @@ -2060,6 +2070,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
>                         vsc->revision = 0x4;
>                         vsc->length = 0xe;
>                 }
> +       } else if (crtc_state->has_pr) {
> +               if (intel_dp->psr.colorimetry_support &&
> +                   intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +                       /* [Panel Replay with colorimetry info] */
> +                       intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> +                                                        vsc);
> +               } else {
> +                       /*
> +                        * [Panel Replay without colorimetry info]
> +                        * Prepare VSC Header for SU as per DP 2.0
> spec, Table 2-223
> +                        * VSC SDP supporting 3D stereo + Panel
> Replay.
> +                        */
> +                       vsc->revision = 0x6;
> +                       vsc->length = 0x10;
> +               }
>         } else {
>                 /*
>                  * [PSR1]
> @@ -3354,10 +3379,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const
> struct drm_dp_vsc_sdp *vsc,
>         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
> Bytes */
>  
>         /*
> -        * Only revision 0x5 supports Pixel Encoding/Colorimetry
> Format as
> -        * per DP 1.4a spec.
> +        * Other than revision 0x5 which supports Pixel
> Encoding/Colorimetry
> +        * Format as per DP 1.4a spec, revision 0x7 also supports
> Pixel
> +        * Encoding/Colorimetry Format as per DP 2.0 spec.
>          */
> -       if (vsc->revision != 0x5)
> +       if (vsc->revision != 0x5 || vsc->revision != 0x7)
>                 goto out;
>  
>         /* VSC SDP Payload for DB16 through DB18 */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9fbcb4b93f11..7508e6c967e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -472,6 +472,27 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
>         intel_dp->psr.su_y_granularity = y;
>  }
>  
> +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> +{
> +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +       u8 pr_dpcd = 0;
> +
> +       if (!HAS_PANEL_REPLAY(dev_priv))
> +               return;

This check is not needed. It is ok to check sink capabilities regardles
of if it's supported by the source.

BR,

Jouni Högander

> +
> +       drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> +
> +       if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> +               drm_dbg_kms(&dev_priv->drm,
> +                           "Panel replay is not supported by
> panel\n");
> +               return;
> +       }
> +
> +       drm_dbg_kms(&dev_priv->drm,
> +                   "Panel replay is supported by panel\n");
> +       intel_dp->psr.sink_panel_replay_support = true;
> +}
> +
>  static void _psr_init_dpcd(struct intel_dp *intel_dp)
>  {
>         struct drm_i915_private *i915 =
> @@ -521,12 +542,13 @@ static void _psr_init_dpcd(struct intel_dp
> *intel_dp)
>  
>  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  {
> +       _panel_replay_init_dpcd(intel_dp);
> +
>         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
>                          sizeof(intel_dp->psr_dpcd));
>  
>         if (intel_dp->psr_dpcd[0])
>                 _psr_init_dpcd(intel_dp);
> -       /* TODO: Add PR case here */
>  
>         if (intel_dp->psr.sink_psr2_support) {
>                 intel_dp->psr.colorimetry_support =
> @@ -1207,13 +1229,11 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
>         return false;
>  }
>  
> -void intel_psr_compute_config(struct intel_dp *intel_dp,
> -                             struct intel_crtc_state *crtc_state,
> -                             struct drm_connector_state *conn_state)
> +static bool _psr_compute_config(struct intel_dp *intel_dp,
> +                               struct intel_crtc_state *crtc_state)
>  {
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -       const struct drm_display_mode *adjusted_mode =
> -               &crtc_state->hw.adjusted_mode;
> +       const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>         int psr_setup_time;
>  
>         /*
> @@ -1221,10 +1241,36 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>          * So if VRR is enabled, do not enable PSR.
>          */
>         if (crtc_state->vrr.enable)
> -               return;
> +               return false;
>  
>         if (!CAN_PSR(intel_dp))
> -               return;
> +               return false;
> +
> +       psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> +       if (psr_setup_time < 0) {
> +               drm_dbg_kms(&dev_priv->drm,
> +                           "PSR condition failed: Invalid PSR setup
> time (0x%02x)\n",
> +                           intel_dp->psr_dpcd[1]);
> +               return false;
> +       }
> +
> +       if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> +           adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay
> - 1) {
> +               drm_dbg_kms(&dev_priv->drm,
> +                           "PSR condition failed: PSR setup time (%d
> us) too long\n",
> +                           psr_setup_time);
> +               return false;
> +       }
> +
> +       return true;
> +}
> +
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> +                             struct intel_crtc_state *crtc_state,
> +                             struct drm_connector_state *conn_state)
> +{
> +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +       const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>  
>         if (!psr_global_enabled(intel_dp)) {
>                 drm_dbg_kms(&dev_priv->drm, "PSR disabled by
> flag\n");
> @@ -1234,7 +1280,6 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>         if (intel_dp->psr.sink_not_reliable) {
>                 drm_dbg_kms(&dev_priv->drm,
>                             "PSR sink implementation is not
> reliable\n");
> -               return;
>         }
>  
>         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -1243,23 +1288,11 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>                 return;
>         }
>  
> -       psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> -       if (psr_setup_time < 0) {
> -               drm_dbg_kms(&dev_priv->drm,
> -                           "PSR condition failed: Invalid PSR setup
> time (0x%02x)\n",
> -                           intel_dp->psr_dpcd[1]);
> -               return;
> -       }
> -
> -       if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> -           adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay
> - 1) {
> -               drm_dbg_kms(&dev_priv->drm,
> -                           "PSR condition failed: PSR setup time (%d
> us) too long\n",
> -                           psr_setup_time);
> -               return;
> -       }
> +       if (CAN_PANEL_REPLAY(intel_dp))
> +               crtc_state->has_pr = true;
> +       else
> +               crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
>  
> -       crtc_state->has_psr = true;
>         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> crtc_state);
>  
>         crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> @@ -2699,7 +2732,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
>         struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -       if (!HAS_PSR(dev_priv))
> +       if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
>                 return;
>  
>         /*
> @@ -2719,6 +2752,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
>  
>         intel_dp->psr.source_support = true;
>  
> +       if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp))
> +               intel_dp->psr.source_panel_replay_support = true;
> +
>         /* Set link_standby x link_off defaults */
>         if (DISPLAY_VER(dev_priv) < 12)
>                 /* For new platforms up to TGL let's respect VBT back
> again */

[Intel-gfx] [PATCH v3 5/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP

[Animesh Manna]

Due to similarity panel replay dpcd initialization got added in psr
function which is specific for edp panel. This patch enables panel
replay initialization for dp connector.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7508e6c967e2..f6b00abe92d4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2735,6 +2735,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
 	if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
 		return;
 
+	if (!intel_dp_is_edp(intel_dp))
+		intel_psr_init_dpcd(intel_dp);
+
 	/*
 	 * HSW spec explicitly says PSR is tied to port A.
 	 * BDW+ platforms have a instance of PSR registers per transcoder but
-- 
2.29.0

[Intel-gfx] [PATCH v3 6/6] drm/i915/panelreplay: enable/disable panel replay

[Animesh Manna]

TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.

Bspec: 1407940617

v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]

v3: cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]

Note: Initial plan is to enable panel replay in  full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 32 ++++++++++++++++---
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1ff7e6c03b44..41fbd49393f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1696,6 +1696,7 @@ struct intel_psr {
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
+	bool pr_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f6b00abe92d4..244fb336f6bc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -599,8 +599,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 dpcd_val = DP_PSR_ENABLE;
 
-	/* Enable ALPM at sink for psr2 */
+	if (intel_dp->psr.pr_enabled) {
+		drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+				   DP_PANEL_REPLAY_ENABLE);
+		return;
+	}
+
 	if (intel_dp->psr.psr2_enabled) {
+		/* Enable ALPM at sink for psr2 */
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 				   DP_ALPM_ENABLE |
 				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -750,6 +756,18 @@ static int psr2_block_count(struct intel_dp *intel_dp)
 	return psr2_block_count_lines(intel_dp) / 4;
 }
 
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (intel_dp->psr.psr2_sel_fetch_enabled)
+		intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+			     0, ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+		     TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1361,8 +1379,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&intel_dp->psr.lock);
 
-	/* psr1 and psr2 are mutually exclusive.*/
-	if (intel_dp->psr.psr2_enabled)
+	/* psr1, psr2 and panel-replay are mutually exclusive.*/
+	if (intel_dp->psr.pr_enabled)
+		dg2_activate_panel_replay(intel_dp);
+	else if (intel_dp->psr.psr2_enabled)
 		hsw_activate_psr2(intel_dp);
 	else
 		hsw_activate_psr1(intel_dp);
@@ -1541,6 +1561,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
 
 	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+	intel_dp->psr.pr_enabled = crtc_state->has_pr;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
@@ -1586,7 +1607,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		return;
 	}
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.pr_enabled) {
+		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+	} else if (intel_dp->psr.psr2_enabled) {
 		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
 
 		val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
-- 
2.29.0

Re: [Intel-gfx] [PATCH v3 6/6] drm/i915/panelreplay: enable/disable panel replay

[Hogander, Jouni]

On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> TRANS_DP2_CTL register is programmed to enable panel replay from
> source
> and sink is enabled through panel replay dpcd configuration address.
> 
> Bspec: 1407940617
> 
> v1: Initial version.
> v2:
> - Use pr_* flags instead psr_* flags. [Jouni]
> - Remove intel_dp_is_edp check as edp1.5 also has panel replay.
> [Jouni]
> 
> v3: cover letter updated and selective fetch condition check is added
> before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
> 
> Note: Initial plan is to enable panel replay in  full-screen live
> active
> frame update mode. In a incremental approach panel replay will be
> enabled
> in selctive update mode if there is any gap in curent implementation.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 32 ++++++++++++++++-
> --
>  2 files changed, 29 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1ff7e6c03b44..41fbd49393f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1696,6 +1696,7 @@ struct intel_psr {
>         u16 su_y_granularity;
>         bool source_panel_replay_support;
>         bool sink_panel_replay_support;
> +       bool pr_enabled;
>         u32 dc3co_exitline;
>         u32 dc3co_exit_delay;
>         struct delayed_work dc3co_work;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index f6b00abe92d4..244fb336f6bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -599,8 +599,14 @@ static void intel_psr_enable_sink(struct
> intel_dp *intel_dp)
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>         u8 dpcd_val = DP_PSR_ENABLE;
>  
> -       /* Enable ALPM at sink for psr2 */
> +       if (intel_dp->psr.pr_enabled) {
> +               drm_dp_dpcd_writeb(&intel_dp->aux,
> PANEL_REPLAY_CONFIG,
> +                                  DP_PANEL_REPLAY_ENABLE);
> +               return;
> +       }
> +
>         if (intel_dp->psr.psr2_enabled) {
> +               /* Enable ALPM at sink for psr2 */
>                 drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
>                                    DP_ALPM_ENABLE |
>                                   
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> @@ -750,6 +756,18 @@ static int psr2_block_count(struct intel_dp
> *intel_dp)
>         return psr2_block_count_lines(intel_dp) / 4;
>  }
>  
> +static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
> +{
> +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +       if (intel_dp->psr.psr2_sel_fetch_enabled)
> +               intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder),
> +                            0,
> ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);

This is definitely not right thing to do here. It will be taken care by
intel_psr2_program_trans_man_trk_ctl when we enable selective update
for panel replay.

BR,

Jouni Högander

> +
> +       intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp-
> >psr.transcoder), 0,
> +                    TRANS_DP2_PANEL_REPLAY_ENABLE);
> +}
> +
>  static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  {
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1361,8 +1379,10 @@ static void intel_psr_activate(struct intel_dp
> *intel_dp)
>  
>         lockdep_assert_held(&intel_dp->psr.lock);
>  
> -       /* psr1 and psr2 are mutually exclusive.*/
> -       if (intel_dp->psr.psr2_enabled)
> +       /* psr1, psr2 and panel-replay are mutually exclusive.*/
> +       if (intel_dp->psr.pr_enabled)
> +               dg2_activate_panel_replay(intel_dp);
> +       else if (intel_dp->psr.psr2_enabled)
>                 hsw_activate_psr2(intel_dp);
>         else
>                 hsw_activate_psr1(intel_dp);
> @@ -1541,6 +1561,7 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
>         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
>  
>         intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> +       intel_dp->psr.pr_enabled = crtc_state->has_pr;
>         intel_dp->psr.busy_frontbuffer_bits = 0;
>         intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> >pipe;
>         intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> @@ -1586,7 +1607,10 @@ static void intel_psr_exit(struct intel_dp
> *intel_dp)
>                 return;
>         }
>  
> -       if (intel_dp->psr.psr2_enabled) {
> +       if (intel_dp->psr.pr_enabled) {
> +               intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp-
> >psr.transcoder),
> +                            TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> +       } else if (intel_dp->psr.psr2_enabled) {
>                 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
>  
>                 val = intel_de_rmw(dev_priv,
> EDP_PSR2_CTL(cpu_transcoder),

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation (rev5)

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation (rev5)
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

Error: dim checkpatch failed
445e87b0b6b4 drm/panelreplay: dpcd register definition for panelreplay
81963673fe7c drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
d9b9bdca76bf drm/i915/psr: Move psr specific dpcd init into own function
-:55: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED'
#55: FILE: drivers/gpu/drm/i915/display/intel_psr.c:499:
+	if (DISPLAY_VER(i915) >= 9 &&
 	    (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {

total: 0 errors, 0 warnings, 1 checks, 70 lines checked
d7981359cc4e drm/i915/panelreplay: Initializaton and compute config for panel replay
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#17: 
- Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check. [Jouni]

-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1989:
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+			  (intel_dp)->psr.source_panel_replay_support)

total: 0 errors, 1 warnings, 1 checks, 240 lines checked
53b797e67556 drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
7c40fcb0136b drm/i915/panelreplay: enable/disable panel replay

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev5)

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation (rev5)
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Panel replay phase1 implementation (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7209 bytes --]

== Series Details ==

Series: Panel replay phase1 implementation (rev5)
URL   : https://patchwork.freedesktop.org/series/94470/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13436 -> Patchwork_94470v5
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/index.html

Participating hosts (42 -> 41)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_94470v5 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@load:
    - bat-mtlp-8:         [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/bat-mtlp-8/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/bat-mtlp-8/igt@i915_module_load@load.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [PASS][3] -> [ABORT][4] ([i915#7911] / [i915#7913])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-glk-j4005:       [PASS][5] -> [DMESG-FAIL][6] ([i915#5334])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
    - bat-mtlp-6:         [PASS][7] -> [DMESG-FAIL][8] ([i915#8497])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/bat-mtlp-6/igt@i915_selftest@live@requests.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/bat-mtlp-6/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-1:         [PASS][9] -> [DMESG-WARN][10] ([i915#6367])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/bat-rpls-1/igt@i915_selftest@live@slpc.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/bat-rpls-1/igt@i915_selftest@live@slpc.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - fi-apl-guc:         NOTRUN -> [SKIP][11] ([fdo#109271])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/fi-apl-guc/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - bat-adlp-9:         [FAIL][12] ([i915#7940]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/bat-adlp-9/igt@i915_pm_rpm@basic-pci-d3-state.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/bat-adlp-9/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - fi-apl-guc:         [DMESG-FAIL][14] ([i915#8585]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
    - fi-kbl-7567u:       [FAIL][16] ([i915#7940]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gt_mocs:
    - bat-mtlp-8:         [DMESG-FAIL][18] ([i915#7059]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@requests:
    - bat-mtlp-8:         [DMESG-FAIL][20] ([i915#8497]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/bat-mtlp-8/igt@i915_selftest@live@requests.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/bat-mtlp-8/igt@i915_selftest@live@requests.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-cfl-guc:         [FAIL][22] ([i915#7940]) -> [FAIL][23] ([i915#7691])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/fi-cfl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/fi-cfl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-rplp-1:         [ABORT][24] ([i915#8712]) -> [ABORT][25] ([i915#8442] / [i915#8668] / [i915#8712])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/486
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
  [i915#8585]: https://gitlab.freedesktop.org/drm/intel/issues/8585
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712
  [i915#8879]: https://gitlab.freedesktop.org/drm/intel/issues/8879


Build changes
-------------

  * Linux: CI_DRM_13436 -> Patchwork_94470v5

  CI-20190529: 20190529
  CI_DRM_13436: 0727bfdb8be472a249839720d845b1c45b8ed611 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7408: 93482edd02839f9eb6ceffca9418d03f570f34f3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_94470v5: 0727bfdb8be472a249839720d845b1c45b8ed611 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

dcb5c001c4a3 drm/i915/panelreplay: enable/disable panel replay
483a5bcc0946 drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
cd518c251871 drm/i915/panelreplay: Initializaton and compute config for panel replay
14e256d7bbc4 drm/i915/psr: Move psr specific dpcd init into own function
c0b594ded01b drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
cef78ffc0c27 drm/panelreplay: dpcd register definition for panelreplay

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/index.html

[-- Attachment #2: Type: text/html, Size: 8286 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Panel replay phase1 implementation (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 42560 bytes --]

== Series Details ==

Series: Panel replay phase1 implementation (rev5)
URL   : https://patchwork.freedesktop.org/series/94470/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13436_full -> Patchwork_94470v5_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_94470v5_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_fdinfo@busy-hang@bcs0:
    - shard-dg1:          NOTRUN -> [SKIP][1] ([i915#8414]) +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-16/igt@drm_fdinfo@busy-hang@bcs0.html

  * igt@drm_fdinfo@busy-hang@rcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][2] ([i915#8414]) +6 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@drm_fdinfo@busy-hang@rcs0.html

  * igt@gem_barrier_race@remote-request@rcs0:
    - shard-apl:          [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211] / [i915#8234])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-apl7/igt@gem_barrier_race@remote-request@rcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl4/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_basic@multigpu-create-close:
    - shard-mtlp:         NOTRUN -> [SKIP][5] ([i915#7697])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed.html

  * igt@gem_eio@reset-stress:
    - shard-dg1:          [PASS][7] -> [FAIL][8] ([i915#5784])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg1-18/igt@gem_eio@reset-stress.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-18/igt@gem_eio@reset-stress.html

  * igt@gem_exec_await@wide-contexts:
    - shard-dg2:          [PASS][9] -> [TIMEOUT][10] ([i915#5892])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-1/igt@gem_exec_await@wide-contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-1/igt@gem_exec_await@wide-contexts.html

  * igt@gem_exec_endless@dispatch@bcs0:
    - shard-dg2:          [PASS][11] -> [TIMEOUT][12] ([i915#3778] / [i915#7016] / [i915#7921])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-1/igt@gem_exec_endless@dispatch@bcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-5/igt@gem_exec_endless@dispatch@bcs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-rkl:          [PASS][13] -> [FAIL][14] ([i915#2846])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#2846])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-glk2/igt@gem_exec_fair@basic-deadline.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-glk7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         [PASS][19] -> [FAIL][20] ([i915#2842])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-tglu-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-rkl:          [PASS][21] -> [FAIL][22] ([i915#2842]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-2/igt@gem_exec_fair@basic-pace@bcs0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-7/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fence@submit67:
    - shard-mtlp:         NOTRUN -> [SKIP][23] ([i915#4812])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@gem_exec_fence@submit67.html

  * igt@gem_exec_reloc@basic-concurrent0:
    - shard-mtlp:         NOTRUN -> [SKIP][24] ([i915#3281]) +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@gem_exec_reloc@basic-concurrent0.html

  * igt@gem_exec_reloc@basic-gtt-active:
    - shard-dg1:          NOTRUN -> [SKIP][25] ([i915#3281])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-16/igt@gem_exec_reloc@basic-gtt-active.html

  * igt@gem_mmap_wc@bad-size:
    - shard-mtlp:         NOTRUN -> [SKIP][26] ([i915#4083]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@gem_mmap_wc@bad-size.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-mtlp:         NOTRUN -> [SKIP][27] ([i915#3282])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_pread@exhaustion:
    - shard-snb:          NOTRUN -> [WARN][28] ([i915#2658])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-snb6/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-dg1:          NOTRUN -> [SKIP][29] ([i915#4270])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-15/igt@gem_pxp@create-protected-buffer.html
    - shard-tglu:         NOTRUN -> [SKIP][30] ([i915#4270])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-3/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_spin_batch@legacy@vebox:
    - shard-apl:          [PASS][31] -> [FAIL][32] ([i915#2898])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-apl6/igt@gem_spin_batch@legacy@vebox.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl3/igt@gem_spin_batch@legacy@vebox.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-mtlp:         NOTRUN -> [SKIP][33] ([i915#3297])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [PASS][34] -> [ABORT][35] ([i915#5566])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-apl6/igt@gen9_exec_parse@allowed-all.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl1/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-mtlp:         NOTRUN -> [SKIP][36] ([i915#2856])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@i915_module_load@load:
    - shard-snb:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#6227])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-snb6/igt@i915_module_load@load.html

  * igt@i915_module_load@reload-no-display:
    - shard-dg2:          [PASS][38] -> [ABORT][39] ([i915#7461])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-1/igt@i915_module_load@reload-no-display.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-1/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - shard-dg2:          [PASS][40] -> [SKIP][41] ([i915#1937])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-10/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-dg1:          [PASS][42] -> [FAIL][43] ([i915#3591])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [PASS][44] -> [SKIP][45] ([i915#1397])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp:
    - shard-dg2:          [PASS][46] -> [SKIP][47] ([i915#1397])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-7/igt@i915_pm_rpm@modeset-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-tglu:         [PASS][48] -> [FAIL][49] ([i915#7940])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-tglu-6/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-3/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-snb:          NOTRUN -> [DMESG-WARN][50] ([i915#8841]) +4 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-snb6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@i915_suspend@sysfs-reader:
    - shard-dg2:          [PASS][51] -> [FAIL][52] ([fdo#103375])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-1/igt@i915_suspend@sysfs-reader.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-5/igt@i915_suspend@sysfs-reader.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][53] -> [FAIL][54] ([i915#2521])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-glk3/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-glk4/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html

  * igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][55] ([i915#8247]) +3 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-6/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][56] ([i915#4538] / [i915#5286])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-15/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
    - shard-tglu:         NOTRUN -> [SKIP][57] ([fdo#111615] / [i915#5286])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-3/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-mtlp:         [PASS][58] -> [FAIL][59] ([i915#3743]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][60] -> [FAIL][61] ([i915#5138])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][62] ([fdo#111614]) +1 similar issue
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][63] ([i915#3638])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-15/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
    - shard-tglu:         NOTRUN -> [SKIP][64] ([fdo#111614])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-3/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][65] ([fdo#111615])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][66] ([i915#3689] / [i915#5354] / [i915#6095])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-15/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html
    - shard-tglu:         NOTRUN -> [SKIP][67] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-3/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][68] ([i915#3886] / [i915#6095])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#3886])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl7/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271]) +20 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl7/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][71] ([i915#6095]) +4 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs.html

  * igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#4087]) +3 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-5/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][73] ([i915#3359])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-3/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
    - shard-mtlp:         NOTRUN -> [SKIP][74] ([i915#3359])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-2/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
    - shard-dg1:          NOTRUN -> [SKIP][75] ([i915#3359])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-15/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][76] ([fdo#111767] / [i915#3546])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-mtlp:         NOTRUN -> [SKIP][77] ([i915#3546])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-apl:          [PASS][78] -> [FAIL][79] ([i915#2346])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [PASS][80] -> [FAIL][81] ([i915#2346])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
    - shard-glk:          [PASS][82] -> [FAIL][83] ([i915#2122])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#8381])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][85] ([i915#2672]) +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([i915#8810])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-dg2:          [PASS][87] -> [FAIL][88] ([i915#6880])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
    - shard-tglu:         NOTRUN -> [SKIP][89] ([fdo#109280])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
    - shard-mtlp:         NOTRUN -> [SKIP][90] ([i915#1825]) +4 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
    - shard-dg1:          NOTRUN -> [SKIP][91] ([fdo#111825])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [PASS][92] -> [ABORT][93] ([i915#180])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][94] ([i915#8708])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][95] ([i915#8708])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_plane_lowres@tiling-x@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][96] ([i915#3582]) +3 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@kms_plane_lowres@tiling-x@pipe-c-edp-1.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][97] ([i915#8292])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [FAIL][98] ([i915#8292])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-13/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][99] ([i915#5176]) +1 similar issue
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][100] ([i915#5176]) +15 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][101] ([i915#5176]) +3 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-d-edp-1.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#5176]) +3 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-5/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][103] ([fdo#109271]) +277 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-snb4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][104] ([i915#5235]) +3 similar issues
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-3/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#5235]) +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][106] ([i915#5235]) +19 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-14/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-mtlp:         NOTRUN -> [SKIP][107] ([i915#4235]) +1 similar issue
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg1:          NOTRUN -> [SKIP][108] ([fdo#111615] / [i915#5289])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@sysfs_heartbeat_interval@nopreempt@ccs0:
    - shard-mtlp:         [PASS][109] -> [FAIL][110] ([i915#6015])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-mtlp-2/igt@sysfs_heartbeat_interval@nopreempt@ccs0.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@sysfs_heartbeat_interval@nopreempt@ccs0.html

  * igt@v3d/v3d_submit_cl@valid-multisync-submission:
    - shard-mtlp:         NOTRUN -> [SKIP][111] ([i915#2575])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@v3d/v3d_submit_cl@valid-multisync-submission.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-rkl:          [FAIL][112] ([i915#6268]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-6/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_eio@hibernate:
    - shard-dg1:          [ABORT][114] ([i915#4391] / [i915#7975] / [i915#8213]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg1-14/igt@gem_eio@hibernate.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-15/igt@gem_eio@hibernate.html
    - shard-tglu:         [ABORT][116] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-tglu-10/igt@gem_eio@hibernate.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-3/igt@gem_eio@hibernate.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-rkl:          [FAIL][118] ([i915#2842]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-6/igt@gem_exec_fair@basic-none@vcs0.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-2/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][120] ([i915#2842]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@i915_pipe_stress@stress-xrgb8888-untiled:
    - shard-mtlp:         [FAIL][122] ([i915#8691]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-mtlp-7/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
    - shard-dg1:          [FAIL][124] ([i915#3591]) -> [PASS][125] +1 similar issue
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          [SKIP][126] ([i915#1397]) -> [PASS][127] +1 similar issue
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-8/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-10/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
    - shard-rkl:          [SKIP][128] ([i915#1397]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-dg1:          [SKIP][130] ([i915#1397]) -> [PASS][131] +2 similar issues
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-16/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@system-suspend-devices:
    - shard-tglu:         [FAIL][132] ([i915#7940]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-tglu-2/igt@i915_pm_rpm@system-suspend-devices.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-8/igt@i915_pm_rpm@system-suspend-devices.html

  * igt@i915_pm_rps@reset:
    - shard-tglu:         [INCOMPLETE][134] ([i915#8320]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-tglu-5/igt@i915_pm_rps@reset.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-5/igt@i915_pm_rps@reset.html

  * igt@i915_selftest@live@requests:
    - shard-mtlp:         [DMESG-FAIL][136] ([i915#8497]) -> [PASS][137]
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-mtlp-8/igt@i915_selftest@live@requests.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-2/igt@i915_selftest@live@requests.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
    - shard-mtlp:         [FAIL][138] ([i915#2521]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-mtlp-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [ABORT][140] ([i915#180]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
    - shard-dg2:          [FAIL][142] ([fdo#103375]) -> [PASS][143] +3 similar issues
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-5/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-1/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-linear:
    - shard-dg2:          [FAIL][144] ([i915#6880]) -> [PASS][145] +2 similar issues
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html

  * igt@sysfs_heartbeat_interval@mixed@vecs0:
    - shard-glk:          [FAIL][146] ([i915#1731]) -> [PASS][147]
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-glk7/igt@sysfs_heartbeat_interval@mixed@vecs0.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-glk6/igt@sysfs_heartbeat_interval@mixed@vecs0.html

  * igt@sysfs_heartbeat_interval@nopreempt@vcs0:
    - shard-mtlp:         [FAIL][148] ([i915#6015]) -> [PASS][149] +1 similar issue
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-mtlp-2/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-3/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html

  
#### Warnings ####

  * igt@gem_exec_whisper@basic-contexts-priority-all:
    - shard-mtlp:         [ABORT][150] ([i915#7392] / [i915#8131]) -> [TIMEOUT][151] ([i915#7392])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-mtlp-7/igt@gem_exec_whisper@basic-contexts-priority-all.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-mtlp-8/igt@gem_exec_whisper@basic-contexts-priority-all.html

  * igt@i915_pm_rc6_residency@rc6-idle@bcs0:
    - shard-tglu:         [FAIL][152] ([i915#2681] / [i915#3591]) -> [WARN][153] ([i915#2681])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-tglu:         [WARN][154] ([i915#2681]) -> [FAIL][155] ([i915#2681] / [i915#3591])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@kms_content_protection@mei_interface:
    - shard-dg1:          [SKIP][156] ([fdo#109300]) -> [SKIP][157] ([i915#7116])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg1-13/igt@kms_content_protection@mei_interface.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-14/igt@kms_content_protection@mei_interface.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-snb:          [DMESG-WARN][158] ([i915#8841]) -> [DMESG-FAIL][159] ([fdo#103375])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-snb2/igt@kms_fbcon_fbt@fbc-suspend.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-snb7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][160] ([i915#3955]) -> [SKIP][161] ([fdo#110189] / [i915#3955])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][162] ([fdo#109285]) -> [SKIP][163] ([fdo#109285] / [i915#4098])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][164] ([i915#4816]) -> [SKIP][165] ([i915#4070] / [i915#4816])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_psr@cursor_plane_move:
    - shard-dg1:          [SKIP][166] ([i915#1072] / [i915#4078]) -> [SKIP][167] ([i915#1072])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13436/shard-dg1-13/igt@kms_psr@cursor_plane_move.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/shard-dg1-14/igt@kms_psr@cursor_plane_move.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
  [i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#7016]: https://gitlab.freedesktop.org/drm/intel/issues/7016
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7921]: https://gitlab.freedesktop.org/drm/intel/issues/7921
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131
  [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8320]: https://gitlab.freedesktop.org/drm/intel/issues/8320
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925


Build changes
-------------

  * Linux: CI_DRM_13436 -> Patchwork_94470v5

  CI-20190529: 20190529
  CI_DRM_13436: 0727bfdb8be472a249839720d845b1c45b8ed611 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7408: 93482edd02839f9eb6ceffca9418d03f570f34f3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_94470v5: 0727bfdb8be472a249839720d845b1c45b8ed611 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v5/index.html

[-- Attachment #2: Type: text/html, Size: 49611 bytes --]

Re: [Intel-gfx] [PATCH v3 0/6] Panel replay phase1 implementation

[Hogander, Jouni]

On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> > Panel Replay is a power saving feature for DP 2.0 monitor and
> > similar
> > to PSR on EDP.
> > 
> > These patches are basic enablement patches added on top of
> > existing psr framework to enable full-screen live active frame
> > update mode of panel replay. Panel replay also can be enabled
> > in selective update mode which will be enabled in a incremental
> > approach.
> > 
> > As per current design panel replay priority is higher than psr.
> > intel_dp->psr.pr_enabled flag indicate panel replay is enabled.
> > intel_dp->psr.pr_enabled + intel_dp->psr.psr2_enabled indicates
> > panel replay is enabled in selective update mode.
> > intel_dp->psr.pr_enabled + intel_dp->psr.psr2_enabled +
> > intel_psr.selective_fetch enabled indicates panel replay is
> > enabled in selective update mode with selective fetch.
> > PSR replated flags remain same like before.
> > 
> > Note: The patches are not tested due to unavailability of monitor.

Couple of generic comment concerning the whole set:

I see both PR and PANEL_REPLAY being used in your patches. I would
choose either PR or PANEL_REPLAY . Same thought on SU and
SELECTIVE_UDATE. As PANEL_SELF_REFRESH is PSR I don't see why PR should
be PANEL_REPLAY. Also SU is widely already used in psr definitions I
would use it for panel replay definitions as well.

BR,

Jouni Högander

> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > 
> > Animesh Manna (5):
> >   drm/panelreplay: dpcd register definition for panelreplay
> >   drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
> >   drm/i915/panelreplay: Initializaton and compute config for panel
> >     replay
> >   drm/i915/panelreplay: Enable panel replay dpcd initialization for
> > > DP
> >   drm/i915/panelreplay: enable/disable panel replay
> > 
> > Jouni Högander (1):
> >   drm/i915/psr: Move psr specific dpcd init into own function
> > 
> >  .../drm/i915/display/intel_display_device.h   |   1 +
> >  .../drm/i915/display/intel_display_types.h    |   9 +-
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  44 ++++-
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 158 >
> > +++++++++++++-----
> >  include/drm/display/drm_dp.h                  |  11 ++
> >  5 files changed, 168 insertions(+), 55 deletions(-)
> > 

Re: [Intel-gfx] [PATCH v3 0/6] Panel replay phase1 implementation

[Manna, Animesh]

Hi,

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, July 31, 2023 11:43 AM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: Re: [PATCH v3 0/6] Panel replay phase1 implementation
> 
> On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote:
> > > Panel Replay is a power saving feature for DP 2.0 monitor and
> > > similar to PSR on EDP.
> > >
> > > These patches are basic enablement patches added on top of existing
> > > psr framework to enable full-screen live active frame update mode of
> > > panel replay. Panel replay also can be enabled in selective update
> > > mode which will be enabled in a incremental approach.
> > >
> > > As per current design panel replay priority is higher than psr.
> > > intel_dp->psr.pr_enabled flag indicate panel replay is enabled.
> > > intel_dp->psr.pr_enabled + intel_dp->psr.psr2_enabled indicates
> > > panel replay is enabled in selective update mode.
> > > intel_dp->psr.pr_enabled + intel_dp->psr.psr2_enabled +
> > > intel_psr.selective_fetch enabled indicates panel replay is enabled
> > > in selective update mode with selective fetch.
> > > PSR replated flags remain same like before.
> > >
> > > Note: The patches are not tested due to unavailability of monitor.
> 
> Couple of generic comment concerning the whole set:
> 
> I see both PR and PANEL_REPLAY being used in your patches. I would choose
> either PR or PANEL_REPLAY . Same thought on SU and SELECTIVE_UDATE. As
> PANEL_SELF_REFRESH is PSR I don't see why PR should be PANEL_REPLAY.
> Also SU is widely already used in psr definitions I would use it for panel
> replay definitions as well.

Sure, instead of pr will add panel_replay, Jani also suggested sometime back.
I am not adding selective update related flag. If needed, we can have a separate patch.

Regards,
Animesh

> 
> BR,
> 
> Jouni Högander
> 
> > > Cc: Jouni Högander <jouni.hogander@intel.com>
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > >
> > > Animesh Manna (5):
> > >   drm/panelreplay: dpcd register definition for panelreplay
> > >   drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
> > >   drm/i915/panelreplay: Initializaton and compute config for panel
> > >     replay
> > >   drm/i915/panelreplay: Enable panel replay dpcd initialization for
> > > > DP
> > >   drm/i915/panelreplay: enable/disable panel replay
> > >
> > > Jouni Högander (1):
> > >   drm/i915/psr: Move psr specific dpcd init into own function
> > >
> > >  .../drm/i915/display/intel_display_device.h   |   1 +
> > >  .../drm/i915/display/intel_display_types.h    |   9 +-
> > >  drivers/gpu/drm/i915/display/intel_dp.c       |  44 ++++-
> > >  drivers/gpu/drm/i915/display/intel_psr.c      | 158 >
> > > +++++++++++++-----
> > >  include/drm/display/drm_dp.h                  |  11 ++
> > >  5 files changed, 168 insertions(+), 55 deletions(-)
> > >
>