* [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:34 ` Manasi Navare
2023-09-11 17:42 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
` (21 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Do the PSR unlock after the vblank evade critcal section is
fully over, not before.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 182c6dd64f47..5caa928e5ce9 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -646,10 +646,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
ktime_t end_vbl_time = ktime_get();
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- intel_psr_unlock(new_crtc_state);
-
if (new_crtc_state->do_async_flip)
- return;
+ goto out;
trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
@@ -709,7 +707,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
local_irq_enable();
if (intel_vgpu_active(dev_priv))
- return;
+ goto out;
if (crtc->debug.start_vbl_count &&
crtc->debug.start_vbl_count != end_vbl_count) {
@@ -724,4 +722,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
}
dbg_vblank_evade(crtc, end_vbl_time);
+
+out:
+ intel_psr_unlock(new_crtc_state);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section
2023-09-01 13:04 ` [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
@ 2023-09-07 18:34 ` Manasi Navare
2023-09-11 17:42 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:34 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Looks good to me,
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 1, 2023 at 6:04 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Do the PSR unlock after the vblank evade critcal section is
> fully over, not before.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 182c6dd64f47..5caa928e5ce9 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -646,10 +646,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> ktime_t end_vbl_time = ktime_get();
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - intel_psr_unlock(new_crtc_state);
> -
> if (new_crtc_state->do_async_flip)
> - return;
> + goto out;
>
> trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
>
> @@ -709,7 +707,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> local_irq_enable();
>
> if (intel_vgpu_active(dev_priv))
> - return;
> + goto out;
>
> if (crtc->debug.start_vbl_count &&
> crtc->debug.start_vbl_count != end_vbl_count) {
> @@ -724,4 +722,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> }
>
> dbg_vblank_evade(crtc, end_vbl_time);
> +
> +out:
> + intel_psr_unlock(new_crtc_state);
> }
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section
2023-09-01 13:04 ` [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
2023-09-07 18:34 ` Manasi Navare
@ 2023-09-11 17:42 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-11 17:42 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:34
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the
> pipe update critical section
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Do the PSR unlock after the vblank evade critcal section is fully over, not
> before.
Typo *critical
Other changes looks good to me.
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 182c6dd64f47..5caa928e5ce9 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -646,10 +646,8 @@ void intel_pipe_update_end(struct intel_crtc_state
> *new_crtc_state)
> ktime_t end_vbl_time = ktime_get();
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - intel_psr_unlock(new_crtc_state);
> -
> if (new_crtc_state->do_async_flip)
> - return;
> + goto out;
>
> trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
>
> @@ -709,7 +707,7 @@ void intel_pipe_update_end(struct intel_crtc_state
> *new_crtc_state)
> local_irq_enable();
>
> if (intel_vgpu_active(dev_priv))
> - return;
> + goto out;
>
> if (crtc->debug.start_vbl_count &&
> crtc->debug.start_vbl_count != end_vbl_count) { @@ -724,4 +722,7
> @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> }
>
> dbg_vblank_evade(crtc, end_vbl_time);
> +
> +out:
> + intel_psr_unlock(new_crtc_state);
> }
> --
> 2.41.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
2023-09-01 13:04 ` [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:36 ` Manasi Navare
2023-09-11 17:53 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 03/12] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Ville Syrjala
` (20 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We'll need to also look at the old crtc state in
intel_pipe_update_start() so change the calling convention to
just plumb in the full atomic state instead.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 18 ++++++++++++------
drivers/gpu/drm/i915/display/intel_crtc.h | 6 ++++--
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
3 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 5caa928e5ce9..461949b48411 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -470,7 +470,8 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
/**
* intel_pipe_update_start() - start update of a set of display registers
- * @new_crtc_state: the new crtc state
+ * @state: the atomic state
+ * @crtc: the crtc
*
* Mark the start of an update to pipe registers that should be updated
* atomically regarding vblank. If the next vblank will happens within
@@ -480,10 +481,12 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
* until a subsequent call to intel_pipe_update_end(). That is done to
* avoid random delays.
*/
-void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
+void intel_pipe_update_start(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
long timeout = msecs_to_jiffies_timeout(1);
int scanline, min, max, vblank_start;
@@ -631,15 +634,18 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
/**
* intel_pipe_update_end() - end update of a set of display registers
- * @new_crtc_state: the new crtc state
+ * @state: the atomic state
+ * @crtc: the crtc
*
* Mark the end of an update started with intel_pipe_update_start(). This
* re-enables interrupts and verifies the update was actually completed
* before a vblank.
*/
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
+void intel_pipe_update_end(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
int scanline_end = intel_get_crtc_scanline(crtc);
u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
index 51a4c8df9e65..22d7993d1f0b 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc.h
@@ -36,8 +36,10 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
-void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
+void intel_pipe_update_start(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+void intel_pipe_update_end(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915);
struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f6397462e4c2..cfad967b5684 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6559,7 +6559,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_crtc_planes_update_noarm(state, crtc);
/* Perform vblank evasion around commit operation */
- intel_pipe_update_start(new_crtc_state);
+ intel_pipe_update_start(state, crtc);
commit_pipe_pre_planes(state, crtc);
@@ -6567,7 +6567,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
commit_pipe_post_planes(state, crtc);
- intel_pipe_update_end(new_crtc_state);
+ intel_pipe_update_end(state, crtc);
/*
* We usually enable FIFO underrun interrupts as part of the
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention
2023-09-01 13:04 ` [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
@ 2023-09-07 18:36 ` Manasi Navare
2023-09-11 17:53 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:36 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We'll need to also look at the old crtc state in
> intel_pipe_update_start() so change the calling convention to
> just plumb in the full atomic state instead.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 18 ++++++++++++------
> drivers/gpu/drm/i915/display/intel_crtc.h | 6 ++++--
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 3 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 5caa928e5ce9..461949b48411 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -470,7 +470,8 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
>
> /**
> * intel_pipe_update_start() - start update of a set of display registers
> - * @new_crtc_state: the new crtc state
> + * @state: the atomic state
> + * @crtc: the crtc
> *
> * Mark the start of an update to pipe registers that should be updated
> * atomically regarding vblank. If the next vblank will happens within
> @@ -480,10 +481,12 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
> * until a subsequent call to intel_pipe_update_end(). That is done to
> * avoid random delays.
> */
> -void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
> +void intel_pipe_update_start(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> @@ -631,15 +634,18 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
>
> /**
> * intel_pipe_update_end() - end update of a set of display registers
> - * @new_crtc_state: the new crtc state
> + * @state: the atomic state
> + * @crtc: the crtc
> *
> * Mark the end of an update started with intel_pipe_update_start(). This
> * re-enables interrupts and verifies the update was actually completed
> * before a vblank.
> */
> -void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> +void intel_pipe_update_end(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> enum pipe pipe = crtc->pipe;
> int scanline_end = intel_get_crtc_scanline(crtc);
> u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
> index 51a4c8df9e65..22d7993d1f0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.h
> @@ -36,8 +36,10 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
> void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
> void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
> -void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
> -void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
> +void intel_pipe_update_start(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void intel_pipe_update_end(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
> struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915);
> struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f6397462e4c2..cfad967b5684 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6559,7 +6559,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> intel_crtc_planes_update_noarm(state, crtc);
>
> /* Perform vblank evasion around commit operation */
> - intel_pipe_update_start(new_crtc_state);
> + intel_pipe_update_start(state, crtc);
>
> commit_pipe_pre_planes(state, crtc);
>
> @@ -6567,7 +6567,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> commit_pipe_post_planes(state, crtc);
>
> - intel_pipe_update_end(new_crtc_state);
> + intel_pipe_update_end(state, crtc);
>
> /*
> * We usually enable FIFO underrun interrupts as part of the
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention
2023-09-01 13:04 ` [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
2023-09-07 18:36 ` Manasi Navare
@ 2023-09-11 17:53 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-11 17:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/12] drm/i915: Change
> intel_pipe_update_{start, end}() calling convention
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We'll need to also look at the old crtc state in
> intel_pipe_update_start() so change the calling convention to just plumb in
> the full atomic state instead.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 18 ++++++++++++------
> drivers/gpu/drm/i915/display/intel_crtc.h | 6 ++++--
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 3 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 5caa928e5ce9..461949b48411 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -470,7 +470,8 @@ static int intel_mode_vblank_start(const struct
> drm_display_mode *mode)
>
> /**
> * intel_pipe_update_start() - start update of a set of display registers
> - * @new_crtc_state: the new crtc state
> + * @state: the atomic state
> + * @crtc: the crtc
> *
> * Mark the start of an update to pipe registers that should be updated
> * atomically regarding vblank. If the next vblank will happens within @@ -
> 480,10 +481,12 @@ static int intel_mode_vblank_start(const struct
> drm_display_mode *mode)
> * until a subsequent call to intel_pipe_update_end(). That is done to
> * avoid random delays.
> */
> -void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
> +void intel_pipe_update_start(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct drm_display_mode *adjusted_mode = &new_crtc_state-
> >hw.adjusted_mode;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> @@ -631,15 +634,18 @@ static void dbg_vblank_evade(struct intel_crtc
> *crtc, ktime_t end) {}
>
> /**
> * intel_pipe_update_end() - end update of a set of display registers
> - * @new_crtc_state: the new crtc state
> + * @state: the atomic state
> + * @crtc: the crtc
> *
> * Mark the end of an update started with intel_pipe_update_start(). This
> * re-enables interrupts and verifies the update was actually completed
> * before a vblank.
> */
> -void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> +void intel_pipe_update_end(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> enum pipe pipe = crtc->pipe;
> int scanline_end = intel_get_crtc_scanline(crtc);
> u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h
> b/drivers/gpu/drm/i915/display/intel_crtc.h
> index 51a4c8df9e65..22d7993d1f0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.h
> @@ -36,8 +36,10 @@ void intel_crtc_state_reset(struct intel_crtc_state
> *crtc_state,
> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); void
> intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state); void
> intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); -void
> intel_pipe_update_start(struct intel_crtc_state *new_crtc_state); -void
> intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
> +void intel_pipe_update_start(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void intel_pipe_update_end(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> void intel_wait_for_vblank_workers(struct intel_atomic_state *state); struct
> intel_crtc *intel_first_crtc(struct drm_i915_private *i915); struct intel_crtc
> *intel_crtc_for_pipe(struct drm_i915_private *i915, diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f6397462e4c2..cfad967b5684 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6559,7 +6559,7 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
> intel_crtc_planes_update_noarm(state, crtc);
>
> /* Perform vblank evasion around commit operation */
> - intel_pipe_update_start(new_crtc_state);
> + intel_pipe_update_start(state, crtc);
>
> commit_pipe_pre_planes(state, crtc);
>
> @@ -6567,7 +6567,7 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
>
> commit_pipe_post_planes(state, crtc);
>
> - intel_pipe_update_end(new_crtc_state);
> + intel_pipe_update_end(state, crtc);
Change LGTM.
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>
> /*
> * We usually enable FIFO underrun interrupts as part of the
> --
> 2.41.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 03/12] drm/i915: Extract intel_crtc_vblank_evade_scanlines()
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
2023-09-01 13:04 ` [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
2023-09-01 13:04 ` [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-11 18:18 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets Ville Syrjala
` (19 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the vblank evasion scanline calculations into their own helper
to declutter intel_pipe_update_start() a bit.
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 53 +++++++++++++----------
1 file changed, 31 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 461949b48411..e46a15d59d79 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -468,6 +468,36 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
return vblank_start;
}
+static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ int *min, int *max, int *vblank_start)
+{
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
+
+ if (new_crtc_state->vrr.enable) {
+ if (intel_vrr_is_push_sent(new_crtc_state))
+ *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
+ else
+ *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
+ } else {
+ *vblank_start = intel_mode_vblank_start(adjusted_mode);
+ }
+
+ /* FIXME needs to be calibrated sensibly */
+ *min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+ *max = *vblank_start - 1;
+
+ /*
+ * M/N is double buffered on the transcoder's undelayed vblank,
+ * so with seamless M/N we must evade both vblanks.
+ */
+ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
+ *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
+}
+
/**
* intel_pipe_update_start() - start update of a set of display registers
* @state: the atomic state
@@ -487,7 +517,6 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
long timeout = msecs_to_jiffies_timeout(1);
int scanline, min, max, vblank_start;
wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
@@ -503,27 +532,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
if (intel_crtc_needs_vblank_work(new_crtc_state))
intel_crtc_vblank_work_init(new_crtc_state);
- if (new_crtc_state->vrr.enable) {
- if (intel_vrr_is_push_sent(new_crtc_state))
- vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
- else
- vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
- } else {
- vblank_start = intel_mode_vblank_start(adjusted_mode);
- }
-
- /* FIXME needs to be calibrated sensibly */
- min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
- VBLANK_EVASION_TIME_US);
- max = vblank_start - 1;
-
- /*
- * M/N is double buffered on the transcoder's undelayed vblank,
- * so with seamless M/N we must evade both vblanks.
- */
- if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
- min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
-
+ intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max, &vblank_start);
if (min <= 0 || max <= 0)
goto irq_disable;
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 03/12] drm/i915: Extract intel_crtc_vblank_evade_scanlines()
2023-09-01 13:04 ` [Intel-gfx] [PATCH 03/12] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Ville Syrjala
@ 2023-09-11 18:18 ` Golani, Mitulkumar Ajitkumar
0 siblings, 0 replies; 52+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-11 18:18 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/12] drm/i915: Extract
> intel_crtc_vblank_evade_scanlines()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the vblank evasion scanline calculations into their own helper to
> declutter intel_pipe_update_start() a bit.
>
> Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 53 +++++++++++++----------
> 1 file changed, 31 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 461949b48411..e46a15d59d79 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -468,6 +468,36 @@ static int intel_mode_vblank_start(const struct
> drm_display_mode *mode)
> return vblank_start;
> }
>
> +static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state
> *state,
> + struct intel_crtc *crtc,
> + int *min, int *max, int
> *vblank_start) {
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_display_mode *adjusted_mode =
> +&new_crtc_state->hw.adjusted_mode;
> +
> + if (new_crtc_state->vrr.enable) {
> + if (intel_vrr_is_push_sent(new_crtc_state))
> + *vblank_start =
> intel_vrr_vmin_vblank_start(new_crtc_state);
> + else
> + *vblank_start =
> intel_vrr_vmax_vblank_start(new_crtc_state);
> + } else {
> + *vblank_start = intel_mode_vblank_start(adjusted_mode);
> + }
> +
> + /* FIXME needs to be calibrated sensibly */
> + *min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> +
> VBLANK_EVASION_TIME_US);
> + *max = *vblank_start - 1;
> +
> + /*
> + * M/N is double buffered on the transcoder's undelayed vblank,
> + * so with seamless M/N we must evade both vblanks.
> + */
> + if (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state))
> + *min -= adjusted_mode->crtc_vblank_start -
> +adjusted_mode->crtc_vdisplay; }
> +
> /**
> * intel_pipe_update_start() - start update of a set of display registers
> * @state: the atomic state
> @@ -487,7 +517,6 @@ void intel_pipe_update_start(struct
> intel_atomic_state *state,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - const struct drm_display_mode *adjusted_mode = &new_crtc_state-
> >hw.adjusted_mode;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc-
> >base);
> @@ -503,27 +532,7 @@ void intel_pipe_update_start(struct
> intel_atomic_state *state,
> if (intel_crtc_needs_vblank_work(new_crtc_state))
> intel_crtc_vblank_work_init(new_crtc_state);
>
> - if (new_crtc_state->vrr.enable) {
> - if (intel_vrr_is_push_sent(new_crtc_state))
> - vblank_start =
> intel_vrr_vmin_vblank_start(new_crtc_state);
> - else
> - vblank_start =
> intel_vrr_vmax_vblank_start(new_crtc_state);
> - } else {
> - vblank_start = intel_mode_vblank_start(adjusted_mode);
> - }
> -
> - /* FIXME needs to be calibrated sensibly */
> - min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> -
> VBLANK_EVASION_TIME_US);
> - max = vblank_start - 1;
> -
> - /*
> - * M/N is double buffered on the transcoder's undelayed vblank,
> - * so with seamless M/N we must evade both vblanks.
> - */
> - if (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state))
> - min -= adjusted_mode->crtc_vblank_start - adjusted_mode-
> >crtc_vdisplay;
> -
> + intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max,
> +&vblank_start);
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> if (min <= 0 || max <= 0)
> goto irq_disable;
>
> --
> 2.41.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (2 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 03/12] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:38 ` Manasi Navare
2023-09-11 18:24 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
` (18 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to reconcile seamless M/N updates with VRR we'll
need to defer the fastset VRR enable to happen after the
seamless M/N update (which happens during the vblank evade
critical section). So just push the VRR enable to be the last
thing during the update.
This will also affect the vblank evasion as the transcoder
will now still be running with the old VRR state during
the vblank evasion. So just grab the timings always from the
old crtc state during any non-modeset commit, and also grab
the current state of VRR from the active timings (as we disable
VRR before vblank evasion during fastsets).
This also fixes vblank evasion for seamless M/N updates as
we now properly account for the fact that the M/N update
happens after vblank evasion.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
2 files changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index e46a15d59d79..1992e7060263 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -472,15 +472,31 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
struct intel_crtc *crtc,
int *min, int *max, int *vblank_start)
{
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
+ const struct intel_crtc_state *crtc_state;
+ const struct drm_display_mode *adjusted_mode;
- if (new_crtc_state->vrr.enable) {
- if (intel_vrr_is_push_sent(new_crtc_state))
- *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
+ /*
+ * During fastsets/etc. the transcoder is still
+ * running with the old timings at this point.
+ *
+ * TODO: maybe just use the active timings here?
+ */
+ if (intel_crtc_needs_modeset(new_crtc_state))
+ crtc_state = new_crtc_state;
+ else
+ crtc_state = old_crtc_state;
+
+ adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
+ if (intel_vrr_is_push_sent(crtc_state))
+ *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
else
- *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
+ *vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
} else {
*vblank_start = intel_mode_vblank_start(adjusted_mode);
}
@@ -710,15 +726,6 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
*/
intel_vrr_send_push(new_crtc_state);
- /*
- * Seamless M/N update may need to update frame timings.
- *
- * FIXME Should be synchronized with the start of vblank somehow...
- */
- if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
- intel_crtc_update_active_timings(new_crtc_state,
- new_crtc_state->vrr.enable);
-
local_irq_enable();
if (intel_vgpu_active(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cfad967b5684..632f1f58df9e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) >= 9 &&
!intel_crtc_needs_modeset(new_crtc_state))
skl_detach_scalers(new_crtc_state);
+
+ if (vrr_enabling(old_crtc_state, new_crtc_state))
+ intel_vrr_enable(new_crtc_state);
}
static void intel_enable_crtc(struct intel_atomic_state *state,
@@ -6527,12 +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_dpt_configure(crtc);
}
- if (vrr_enabling(old_crtc_state, new_crtc_state)) {
- intel_vrr_enable(new_crtc_state);
- intel_crtc_update_active_timings(new_crtc_state,
- new_crtc_state->vrr.enable);
- }
-
if (!modeset) {
if (new_crtc_state->preload_luts &&
intel_crtc_needs_color_update(new_crtc_state))
@@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_pipe_update_end(state, crtc);
+ /*
+ * VRR/Seamless M/N update may need to update frame timings.
+ *
+ * FIXME Should be synchronized with the start of vblank somehow...
+ */
+ if (vrr_enabling(old_crtc_state, new_crtc_state) ||
+ (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
+ intel_crtc_update_active_timings(new_crtc_state,
+ new_crtc_state->vrr.enable);
+
/*
* We usually enable FIFO underrun interrupts as part of the
* CRTC enable sequence during modesets. But when we inherit a
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets
2023-09-01 13:04 ` [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets Ville Syrjala
@ 2023-09-07 18:38 ` Manasi Navare
2023-09-11 18:24 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:38 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Looks good to me,
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to reconcile seamless M/N updates with VRR we'll
> need to defer the fastset VRR enable to happen after the
> seamless M/N update (which happens during the vblank evade
> critical section). So just push the VRR enable to be the last
> thing during the update.
>
> This will also affect the vblank evasion as the transcoder
> will now still be running with the old VRR state during
> the vblank evasion. So just grab the timings always from the
> old crtc state during any non-modeset commit, and also grab
> the current state of VRR from the active timings (as we disable
> VRR before vblank evasion during fastsets).
>
> This also fixes vblank evasion for seamless M/N updates as
> we now properly account for the fact that the M/N update
> happens after vblank evasion.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
> drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
> 2 files changed, 36 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index e46a15d59d79..1992e7060263 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -472,15 +472,31 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> int *min, int *max, int *vblank_start)
> {
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> + const struct intel_crtc_state *crtc_state;
> + const struct drm_display_mode *adjusted_mode;
>
> - if (new_crtc_state->vrr.enable) {
> - if (intel_vrr_is_push_sent(new_crtc_state))
> - *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
> + /*
> + * During fastsets/etc. the transcoder is still
> + * running with the old timings at this point.
> + *
> + * TODO: maybe just use the active timings here?
> + */
> + if (intel_crtc_needs_modeset(new_crtc_state))
> + crtc_state = new_crtc_state;
> + else
> + crtc_state = old_crtc_state;
> +
> + adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> + if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> + if (intel_vrr_is_push_sent(crtc_state))
> + *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> else
> - *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
> + *vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
> } else {
> *vblank_start = intel_mode_vblank_start(adjusted_mode);
> }
> @@ -710,15 +726,6 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
> */
> intel_vrr_send_push(new_crtc_state);
>
> - /*
> - * Seamless M/N update may need to update frame timings.
> - *
> - * FIXME Should be synchronized with the start of vblank somehow...
> - */
> - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> - intel_crtc_update_active_timings(new_crtc_state,
> - new_crtc_state->vrr.enable);
> -
> local_irq_enable();
>
> if (intel_vgpu_active(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cfad967b5684..632f1f58df9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> @@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> if (DISPLAY_VER(dev_priv) >= 9 &&
> !intel_crtc_needs_modeset(new_crtc_state))
> skl_detach_scalers(new_crtc_state);
> +
> + if (vrr_enabling(old_crtc_state, new_crtc_state))
> + intel_vrr_enable(new_crtc_state);
> }
>
> static void intel_enable_crtc(struct intel_atomic_state *state,
> @@ -6527,12 +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> intel_dpt_configure(crtc);
> }
>
> - if (vrr_enabling(old_crtc_state, new_crtc_state)) {
> - intel_vrr_enable(new_crtc_state);
> - intel_crtc_update_active_timings(new_crtc_state,
> - new_crtc_state->vrr.enable);
> - }
> -
> if (!modeset) {
> if (new_crtc_state->preload_luts &&
> intel_crtc_needs_color_update(new_crtc_state))
> @@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> intel_pipe_update_end(state, crtc);
>
> + /*
> + * VRR/Seamless M/N update may need to update frame timings.
> + *
> + * FIXME Should be synchronized with the start of vblank somehow...
> + */
> + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> + (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
> + intel_crtc_update_active_timings(new_crtc_state,
> + new_crtc_state->vrr.enable);
> +
> /*
> * We usually enable FIFO underrun interrupts as part of the
> * CRTC enable sequence during modesets. But when we inherit a
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets
2023-09-01 13:04 ` [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets Ville Syrjala
2023-09-07 18:38 ` Manasi Navare
@ 2023-09-11 18:24 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-11 18:24 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to reconcile seamless M/N updates with VRR we'll need to defer the
> fastset VRR enable to happen after the seamless M/N update (which
> happens during the vblank evade critical section). So just push the VRR
> enable to be the last thing during the update.
>
> This will also affect the vblank evasion as the transcoder will now still be
> running with the old VRR state during the vblank evasion. So just grab the
> timings always from the old crtc state during any non-modeset commit, and
> also grab the current state of VRR from the active timings (as we disable VRR
> before vblank evasion during fastsets).
>
> This also fixes vblank evasion for seamless M/N updates as we now properly
> account for the fact that the M/N update happens after vblank evasion.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
> drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
> 2 files changed, 36 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index e46a15d59d79..1992e7060263 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -472,15 +472,31 @@ static void
> intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> int *min, int *max, int
> *vblank_start) {
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - const struct drm_display_mode *adjusted_mode = &new_crtc_state-
> >hw.adjusted_mode;
> + const struct intel_crtc_state *crtc_state;
> + const struct drm_display_mode *adjusted_mode;
>
> - if (new_crtc_state->vrr.enable) {
> - if (intel_vrr_is_push_sent(new_crtc_state))
> - *vblank_start =
> intel_vrr_vmin_vblank_start(new_crtc_state);
> + /*
> + * During fastsets/etc. the transcoder is still
> + * running with the old timings at this point.
> + *
> + * TODO: maybe just use the active timings here?
> + */
> + if (intel_crtc_needs_modeset(new_crtc_state))
> + crtc_state = new_crtc_state;
> + else
> + crtc_state = old_crtc_state;
> +
> + adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> + if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> + if (intel_vrr_is_push_sent(crtc_state))
> + *vblank_start =
> intel_vrr_vmin_vblank_start(crtc_state);
> else
> - *vblank_start =
> intel_vrr_vmax_vblank_start(new_crtc_state);
> + *vblank_start =
> intel_vrr_vmax_vblank_start(crtc_state);
> } else {
> *vblank_start = intel_mode_vblank_start(adjusted_mode);
> }
> @@ -710,15 +726,6 @@ void intel_pipe_update_end(struct
> intel_atomic_state *state,
> */
> intel_vrr_send_push(new_crtc_state);
>
> - /*
> - * Seamless M/N update may need to update frame timings.
> - *
> - * FIXME Should be synchronized with the start of vblank somehow...
> - */
> - if (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state))
> - intel_crtc_update_active_timings(new_crtc_state,
> - new_crtc_state->vrr.enable);
> -
> local_irq_enable();
>
> if (intel_vgpu_active(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index cfad967b5684..632f1f58df9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> @@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
> if (DISPLAY_VER(dev_priv) >= 9 &&
> !intel_crtc_needs_modeset(new_crtc_state))
> skl_detach_scalers(new_crtc_state);
> +
> + if (vrr_enabling(old_crtc_state, new_crtc_state))
> + intel_vrr_enable(new_crtc_state);
> }
>
> static void intel_enable_crtc(struct intel_atomic_state *state, @@ -6527,12
> +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> intel_dpt_configure(crtc);
> }
>
> - if (vrr_enabling(old_crtc_state, new_crtc_state)) {
> - intel_vrr_enable(new_crtc_state);
> - intel_crtc_update_active_timings(new_crtc_state,
> - new_crtc_state->vrr.enable);
> - }
> -
> if (!modeset) {
> if (new_crtc_state->preload_luts &&
> intel_crtc_needs_color_update(new_crtc_state))
> @@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
>
> intel_pipe_update_end(state, crtc);
>
> + /*
> + * VRR/Seamless M/N update may need to update frame timings.
> + *
> + * FIXME Should be synchronized with the start of vblank somehow...
> + */
> + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> + (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state)))
> + intel_crtc_update_active_timings(new_crtc_state,
> + new_crtc_state->vrr.enable);
> +
changes looks good to me.
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> /*
> * We usually enable FIFO underrun interrupts as part of the
> * CRTC enable sequence during modesets. But when we inherit a
> --
> 2.41.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (3 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:39 ` Manasi Navare
2023-09-01 13:04 ` [Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates Ville Syrjala
` (17 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the seamless_m_n flag more like the update_pipe fastset
flag, ie. the flag will only be set if we need to do the seamless
M/N update, and in all other cases the flag is cleared. Also
rename the flag to update_m_n to make it more clear it's similar
to update_pipe.
I believe special casing seamless_m_n like this makes sense
as it also affects eg. vblank evasion. We can potentially avoid
some vblank evasion tricks, simplify some checks, and hopefully
will help with the VRR vs. M/N mess.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++--------
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
5 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 7cf51dd8c056..aaddd8c0cfa0 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
drm_property_blob_get(crtc_state->post_csc_lut);
crtc_state->update_pipe = false;
+ crtc_state->update_m_n = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
crtc_state->update_wm_pre = false;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 1992e7060263..a04076064f02 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -510,7 +510,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
* M/N is double buffered on the transcoder's undelayed vblank,
* so with seamless M/N we must evade both vblanks.
*/
- if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
+ if (new_crtc_state->update_m_n)
*min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 632f1f58df9e..6196ef76390b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(lane_lat_optim_mask);
if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
- if (!fastset || !pipe_config->seamless_m_n)
+ if (!fastset || !pipe_config->update_m_n)
PIPE_CONF_CHECK_M_N(dp_m_n);
} else {
PIPE_CONF_CHECK_M_N(dp_m_n);
@@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- if (!fastset || !pipe_config->seamless_m_n) {
+ if (!fastset || !pipe_config->update_m_n) {
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
}
@@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
crtc_state->uapi.mode_changed = true;
crtc_state->update_pipe = false;
+ crtc_state->update_m_n = false;
ret = drm_atomic_add_affected_connectors(&state->base,
&crtc->base);
@@ -5519,13 +5520,14 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
{
struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
- if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
+ if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
+ else
+ new_crtc_state->uapi.mode_changed = false;
- return;
- }
+ if (intel_crtc_needs_modeset(new_crtc_state))
+ new_crtc_state->update_m_n = false;
- new_crtc_state->uapi.mode_changed = false;
if (!intel_crtc_needs_modeset(new_crtc_state))
new_crtc_state->update_pipe = true;
}
@@ -6240,6 +6242,7 @@ int intel_atomic_check(struct drm_device *dev,
if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
+ new_crtc_state->update_m_n = false;
}
}
@@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device *dev,
if (intel_cpu_transcoders_need_modeset(state, trans)) {
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
+ new_crtc_state->update_m_n = false;
}
}
@@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device *dev,
if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
+ new_crtc_state->update_m_n = false;
}
}
}
@@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
hsw_set_linetime_wm(new_crtc_state);
- if (new_crtc_state->seamless_m_n)
+ if (new_crtc_state->update_m_n)
intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
&new_crtc_state->dp_m_n);
}
@@ -6573,8 +6578,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
*
* FIXME Should be synchronized with the start of vblank somehow...
*/
- if (vrr_enabling(old_crtc_state, new_crtc_state) ||
- (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
+ if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
intel_crtc_update_active_timings(new_crtc_state,
new_crtc_state->vrr.enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c21064794f32..2f35560d7e4e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1083,6 +1083,7 @@ struct intel_crtc_state {
unsigned fb_bits; /* framebuffers to flip */
bool update_pipe; /* can a fast modeset be performed? */
+ bool update_m_n; /* update M/N seamlessly during fastset? */
bool disable_cxsr;
bool update_wm_pre, update_wm_post; /* watermarks are updated */
bool fifo_changed; /* FIFO split is changed */
@@ -1195,7 +1196,6 @@ struct intel_crtc_state {
/* m2_n2 for eDP downclock */
struct intel_link_m_n dp_m2_n2;
bool has_drrs;
- bool seamless_m_n;
/* PSR is supported but might not be enabled due the lack of enabled planes */
bool has_psr;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3faa68989d85..d4c259da3a14 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2536,7 +2536,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
int pixel_clock;
if (has_seamless_m_n(connector))
- pipe_config->seamless_m_n = true;
+ pipe_config->update_m_n = true;
if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour
2023-09-01 13:04 ` [Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
@ 2023-09-07 18:39 ` Manasi Navare
0 siblings, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:39 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Makes sense to rename the flag to update_m_n
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the seamless_m_n flag more like the update_pipe fastset
> flag, ie. the flag will only be set if we need to do the seamless
> M/N update, and in all other cases the flag is cleared. Also
> rename the flag to update_m_n to make it more clear it's similar
> to update_pipe.
>
> I believe special casing seamless_m_n like this makes sense
> as it also affects eg. vblank evasion. We can potentially avoid
> some vblank evasion tricks, simplify some checks, and hopefully
> will help with the VRR vs. M/N mess.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++--------
> .../drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> 5 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 7cf51dd8c056..aaddd8c0cfa0 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> drm_property_blob_get(crtc_state->post_csc_lut);
>
> crtc_state->update_pipe = false;
> + crtc_state->update_m_n = false;
> crtc_state->disable_lp_wm = false;
> crtc_state->disable_cxsr = false;
> crtc_state->update_wm_pre = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 1992e7060263..a04076064f02 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -510,7 +510,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> * M/N is double buffered on the transcoder's undelayed vblank,
> * so with seamless M/N we must evade both vblanks.
> */
> - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> + if (new_crtc_state->update_m_n)
> *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 632f1f58df9e..6196ef76390b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_X(lane_lat_optim_mask);
>
> if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> - if (!fastset || !pipe_config->seamless_m_n)
> + if (!fastset || !pipe_config->update_m_n)
> PIPE_CONF_CHECK_M_N(dp_m_n);
> } else {
> PIPE_CONF_CHECK_M_N(dp_m_n);
> @@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> - if (!fastset || !pipe_config->seamless_m_n) {
> + if (!fastset || !pipe_config->update_m_n) {
> PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> }
> @@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
>
> crtc_state->uapi.mode_changed = true;
> crtc_state->update_pipe = false;
> + crtc_state->update_m_n = false;
>
> ret = drm_atomic_add_affected_connectors(&state->base,
> &crtc->base);
> @@ -5519,13 +5520,14 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> {
> struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
>
> - if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
> + if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
> + else
> + new_crtc_state->uapi.mode_changed = false;
>
> - return;
> - }
> + if (intel_crtc_needs_modeset(new_crtc_state))
> + new_crtc_state->update_m_n = false;
>
> - new_crtc_state->uapi.mode_changed = false;
> if (!intel_crtc_needs_modeset(new_crtc_state))
> new_crtc_state->update_pipe = true;
> }
> @@ -6240,6 +6242,7 @@ int intel_atomic_check(struct drm_device *dev,
> if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> + new_crtc_state->update_m_n = false;
> }
> }
>
> @@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device *dev,
> if (intel_cpu_transcoders_need_modeset(state, trans)) {
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> + new_crtc_state->update_m_n = false;
> }
> }
>
> @@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device *dev,
> if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> + new_crtc_state->update_m_n = false;
> }
> }
> }
> @@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> hsw_set_linetime_wm(new_crtc_state);
>
> - if (new_crtc_state->seamless_m_n)
> + if (new_crtc_state->update_m_n)
> intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
> &new_crtc_state->dp_m_n);
> }
> @@ -6573,8 +6578,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> *
> * FIXME Should be synchronized with the start of vblank somehow...
> */
> - if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> - (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
> + if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
> intel_crtc_update_active_timings(new_crtc_state,
> new_crtc_state->vrr.enable);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c21064794f32..2f35560d7e4e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1083,6 +1083,7 @@ struct intel_crtc_state {
>
> unsigned fb_bits; /* framebuffers to flip */
> bool update_pipe; /* can a fast modeset be performed? */
> + bool update_m_n; /* update M/N seamlessly during fastset? */
> bool disable_cxsr;
> bool update_wm_pre, update_wm_post; /* watermarks are updated */
> bool fifo_changed; /* FIFO split is changed */
> @@ -1195,7 +1196,6 @@ struct intel_crtc_state {
> /* m2_n2 for eDP downclock */
> struct intel_link_m_n dp_m2_n2;
> bool has_drrs;
> - bool seamless_m_n;
>
> /* PSR is supported but might not be enabled due the lack of enabled planes */
> bool has_psr;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3faa68989d85..d4c259da3a14 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2536,7 +2536,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
> int pixel_clock;
>
> if (has_seamless_m_n(connector))
> - pipe_config->seamless_m_n = true;
> + pipe_config->update_m_n = true;
>
> if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
> if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (4 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:40 ` Manasi Navare
2023-09-01 13:04 ` [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range() Ville Syrjala
` (16 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Don't perform a seamless M/N update if the values aren't actually
changing. This avoids doing extra shenanigans during vblank evasion
needlessly.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6196ef76390b..c20eaf0e7a91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5525,7 +5525,9 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
else
new_crtc_state->uapi.mode_changed = false;
- if (intel_crtc_needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state) ||
+ intel_compare_link_m_n(&old_crtc_state->dp_m_n,
+ &new_crtc_state->dp_m_n))
new_crtc_state->update_m_n = false;
if (!intel_crtc_needs_modeset(new_crtc_state))
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates
2023-09-01 13:04 ` [Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates Ville Syrjala
@ 2023-09-07 18:40 ` Manasi Navare
0 siblings, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:40 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Don't perform a seamless M/N update if the values aren't actually
> changing. This avoids doing extra shenanigans during vblank evasion
> needlessly.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6196ef76390b..c20eaf0e7a91 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5525,7 +5525,9 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> else
> new_crtc_state->uapi.mode_changed = false;
>
> - if (intel_crtc_needs_modeset(new_crtc_state))
> + if (intel_crtc_needs_modeset(new_crtc_state) ||
> + intel_compare_link_m_n(&old_crtc_state->dp_m_n,
> + &new_crtc_state->dp_m_n))
> new_crtc_state->update_m_n = false;
>
> if (!intel_crtc_needs_modeset(new_crtc_state))
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (5 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:43 ` Manasi Navare
2023-09-15 5:38 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range Ville Syrjala
` (15 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move is_in_vrr_range() into intel_vrr.c in anticipation of
more users, and rename it accordingly.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_panel.c | 17 ++++-------------
drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 9232a305b1e6..086cb8dbe22c 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -59,15 +59,6 @@ intel_panel_preferred_fixed_mode(struct intel_connector *connector)
struct drm_display_mode, head);
}
-static bool is_in_vrr_range(struct intel_connector *connector, int vrefresh)
-{
- const struct drm_display_info *info = &connector->base.display_info;
-
- return intel_vrr_is_capable(connector) &&
- vrefresh >= info->monitor_range.min_vfreq &&
- vrefresh <= info->monitor_range.max_vfreq;
-}
-
static bool is_best_fixed_mode(struct intel_connector *connector,
int vrefresh, int fixed_mode_vrefresh,
const struct drm_display_mode *best_mode)
@@ -81,8 +72,8 @@ static bool is_best_fixed_mode(struct intel_connector *connector,
* vrefresh, which we can then reduce to match the requested
* vrefresh by extending the vblank length.
*/
- if (is_in_vrr_range(connector, vrefresh) &&
- is_in_vrr_range(connector, fixed_mode_vrefresh) &&
+ if (intel_vrr_is_in_range(connector, vrefresh) &&
+ intel_vrr_is_in_range(connector, fixed_mode_vrefresh) &&
fixed_mode_vrefresh < vrefresh)
return false;
@@ -224,8 +215,8 @@ int intel_panel_compute_config(struct intel_connector *connector,
* Assume that we shouldn't muck about with the
* timings if they don't land in the VRR range.
*/
- is_vrr = is_in_vrr_range(connector, vrefresh) &&
- is_in_vrr_range(connector, fixed_mode_vrefresh);
+ is_vrr = intel_vrr_is_in_range(connector, vrefresh) &&
+ intel_vrr_is_in_range(connector, fixed_mode_vrefresh);
if (!is_vrr) {
/*
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 88e4759b538b..6ef782538337 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -42,6 +42,15 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
}
+bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh)
+{
+ const struct drm_display_info *info = &connector->base.display_info;
+
+ return intel_vrr_is_capable(connector) &&
+ vrefresh >= info->monitor_range.min_vfreq &&
+ vrefresh <= info->monitor_range.max_vfreq;
+}
+
void
intel_vrr_check_modeset(struct intel_atomic_state *state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index de16960c4929..89937858200d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -14,6 +14,7 @@ struct intel_connector;
struct intel_crtc_state;
bool intel_vrr_is_capable(struct intel_connector *connector);
+bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh);
void intel_vrr_check_modeset(struct intel_atomic_state *state);
void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()
2023-09-01 13:04 ` [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range() Ville Syrjala
@ 2023-09-07 18:43 ` Manasi Navare
2023-09-15 5:38 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:43 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move is_in_vrr_range() into intel_vrr.c in anticipation of
> more users, and rename it accordingly.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_panel.c | 17 ++++-------------
> drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
> 3 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index 9232a305b1e6..086cb8dbe22c 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -59,15 +59,6 @@ intel_panel_preferred_fixed_mode(struct intel_connector *connector)
> struct drm_display_mode, head);
> }
>
> -static bool is_in_vrr_range(struct intel_connector *connector, int vrefresh)
> -{
> - const struct drm_display_info *info = &connector->base.display_info;
> -
> - return intel_vrr_is_capable(connector) &&
> - vrefresh >= info->monitor_range.min_vfreq &&
> - vrefresh <= info->monitor_range.max_vfreq;
> -}
> -
> static bool is_best_fixed_mode(struct intel_connector *connector,
> int vrefresh, int fixed_mode_vrefresh,
> const struct drm_display_mode *best_mode)
> @@ -81,8 +72,8 @@ static bool is_best_fixed_mode(struct intel_connector *connector,
> * vrefresh, which we can then reduce to match the requested
> * vrefresh by extending the vblank length.
> */
> - if (is_in_vrr_range(connector, vrefresh) &&
> - is_in_vrr_range(connector, fixed_mode_vrefresh) &&
> + if (intel_vrr_is_in_range(connector, vrefresh) &&
> + intel_vrr_is_in_range(connector, fixed_mode_vrefresh) &&
> fixed_mode_vrefresh < vrefresh)
> return false;
>
> @@ -224,8 +215,8 @@ int intel_panel_compute_config(struct intel_connector *connector,
> * Assume that we shouldn't muck about with the
> * timings if they don't land in the VRR range.
> */
> - is_vrr = is_in_vrr_range(connector, vrefresh) &&
> - is_in_vrr_range(connector, fixed_mode_vrefresh);
> + is_vrr = intel_vrr_is_in_range(connector, vrefresh) &&
> + intel_vrr_is_in_range(connector, fixed_mode_vrefresh);
>
> if (!is_vrr) {
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 88e4759b538b..6ef782538337 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -42,6 +42,15 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
> info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
> }
>
> +bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh)
> +{
> + const struct drm_display_info *info = &connector->base.display_info;
> +
> + return intel_vrr_is_capable(connector) &&
> + vrefresh >= info->monitor_range.min_vfreq &&
> + vrefresh <= info->monitor_range.max_vfreq;
> +}
> +
> void
> intel_vrr_check_modeset(struct intel_atomic_state *state)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index de16960c4929..89937858200d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -14,6 +14,7 @@ struct intel_connector;
> struct intel_crtc_state;
>
> bool intel_vrr_is_capable(struct intel_connector *connector);
> +bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh);
> void intel_vrr_check_modeset(struct intel_atomic_state *state);
> void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()
2023-09-01 13:04 ` [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range() Ville Syrjala
2023-09-07 18:43 ` Manasi Navare
@ 2023-09-15 5:38 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-15 5:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move is_in_vrr_range() into intel_vrr.c in anticipation of more users, and
> rename it accordingly.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_panel.c | 17 ++++-------------
> drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
> 3 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
> b/drivers/gpu/drm/i915/display/intel_panel.c
> index 9232a305b1e6..086cb8dbe22c 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -59,15 +59,6 @@ intel_panel_preferred_fixed_mode(struct
> intel_connector *connector)
> struct drm_display_mode, head);
> }
>
> -static bool is_in_vrr_range(struct intel_connector *connector, int vrefresh) -{
> - const struct drm_display_info *info = &connector-
> >base.display_info;
> -
> - return intel_vrr_is_capable(connector) &&
> - vrefresh >= info->monitor_range.min_vfreq &&
> - vrefresh <= info->monitor_range.max_vfreq;
> -}
> -
> static bool is_best_fixed_mode(struct intel_connector *connector,
> int vrefresh, int fixed_mode_vrefresh,
> const struct drm_display_mode *best_mode)
> @@ -81,8 +72,8 @@ static bool is_best_fixed_mode(struct intel_connector
> *connector,
> * vrefresh, which we can then reduce to match the requested
> * vrefresh by extending the vblank length.
> */
> - if (is_in_vrr_range(connector, vrefresh) &&
> - is_in_vrr_range(connector, fixed_mode_vrefresh) &&
> + if (intel_vrr_is_in_range(connector, vrefresh) &&
> + intel_vrr_is_in_range(connector, fixed_mode_vrefresh) &&
> fixed_mode_vrefresh < vrefresh)
> return false;
>
> @@ -224,8 +215,8 @@ int intel_panel_compute_config(struct
> intel_connector *connector,
> * Assume that we shouldn't muck about with the
> * timings if they don't land in the VRR range.
> */
> - is_vrr = is_in_vrr_range(connector, vrefresh) &&
> - is_in_vrr_range(connector, fixed_mode_vrefresh);
> + is_vrr = intel_vrr_is_in_range(connector, vrefresh) &&
> + intel_vrr_is_in_range(connector, fixed_mode_vrefresh);
>
> if (!is_vrr) {
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 88e4759b538b..6ef782538337 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -42,6 +42,15 @@ bool intel_vrr_is_capable(struct intel_connector
> *connector)
> info->monitor_range.max_vfreq - info-
> >monitor_range.min_vfreq > 10; }
>
> +bool intel_vrr_is_in_range(struct intel_connector *connector, int
> +vrefresh) {
> + const struct drm_display_info *info = &connector-
> >base.display_info;
> +
> + return intel_vrr_is_capable(connector) &&
> + vrefresh >= info->monitor_range.min_vfreq &&
> + vrefresh <= info->monitor_range.max_vfreq; }
> +
Changes LGTM
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Regards,
Mitul
> void
> intel_vrr_check_modeset(struct intel_atomic_state *state) { diff --git
> a/drivers/gpu/drm/i915/display/intel_vrr.h
> b/drivers/gpu/drm/i915/display/intel_vrr.h
> index de16960c4929..89937858200d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -14,6 +14,7 @@ struct intel_connector; struct intel_crtc_state;
>
> bool intel_vrr_is_capable(struct intel_connector *connector);
> +bool intel_vrr_is_in_range(struct intel_connector *connector, int
> +vrefresh);
> void intel_vrr_check_modeset(struct intel_atomic_state *state); void
> intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> --
> 2.41.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (6 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range() Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:44 ` Manasi Navare
2023-09-15 5:39 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes Ville Syrjala
` (14 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's assume there are some crazy displays where the high
end of the VRR range ends up being lower than the refresh
rate as determined by the actual timings. In that case
when we toggle VRR on/off we would step outside the VRR
range when toggling VRR on/off. Let's just make sure that
never happens by not using VRR in such cases. If the user
really wants VRR they should then select the timings to
land within the VRR range.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6ef782538337..12731ad725a8 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -117,10 +117,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
const struct drm_display_info *info = &connector->base.display_info;
int vmin, vmax;
- if (!intel_vrr_is_capable(connector))
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
return;
- if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+ if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
return;
vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range
2023-09-01 13:04 ` [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range Ville Syrjala
@ 2023-09-07 18:44 ` Manasi Navare
2023-09-15 5:39 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:44 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's assume there are some crazy displays where the high
> end of the VRR range ends up being lower than the refresh
> rate as determined by the actual timings. In that case
> when we toggle VRR on/off we would step outside the VRR
> range when toggling VRR on/off. Let's just make sure that
> never happens by not using VRR in such cases. If the user
> really wants VRR they should then select the timings to
> land within the VRR range.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 6ef782538337..12731ad725a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -117,10 +117,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> const struct drm_display_info *info = &connector->base.display_info;
> int vmin, vmax;
>
> - if (!intel_vrr_is_capable(connector))
> + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> return;
>
> - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> + if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
> return;
>
> vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range
2023-09-01 13:04 ` [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range Ville Syrjala
2023-09-07 18:44 ` Manasi Navare
@ 2023-09-15 5:39 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-15 5:39 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are
> within the VRR range
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's assume there are some crazy displays where the high end of the VRR
> range ends up being lower than the refresh rate as determined by the actual
> timings. In that case when we toggle VRR on/off we would step outside the
> VRR range when toggling VRR on/off. Let's just make sure that never happens
> by not using VRR in such cases. If the user really wants VRR they should then
> select the timings to land within the VRR range.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 6ef782538337..12731ad725a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -117,10 +117,10 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> const struct drm_display_info *info = &connector-
> >base.display_info;
> int vmin, vmax;
>
> - if (!intel_vrr_is_capable(connector))
> + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> return;
>
> - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> + if (!intel_vrr_is_in_range(connector,
> +drm_mode_vrefresh(adjusted_mode)))
Changes LGTM
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Regards,
Mitul
> return;
>
> vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> --
> 2.41.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (7 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:49 ` Manasi Navare
2023-09-11 17:46 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 10/12] drm/i915: Update VRR parameters in fastset Ville Syrjala
` (13 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make life less confusing by making sure VRR is disabled whenever
we do any drastic changes to the display timings, such as seamless
M/N changes.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c20eaf0e7a91..cbbee303cd00 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -916,13 +916,15 @@ static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- return is_enabling(vrr.enable, old_crtc_state, new_crtc_state);
+ return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
+ (new_crtc_state->vrr.enable && new_crtc_state->update_m_n);
}
static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- return is_disabling(vrr.enable, old_crtc_state, new_crtc_state);
+ return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
+ (old_crtc_state->vrr.enable && new_crtc_state->update_m_n);
}
#undef is_disabling
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes
2023-09-01 13:04 ` [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes Ville Syrjala
@ 2023-09-07 18:49 ` Manasi Navare
2023-09-08 5:53 ` Ville Syrjälä
2023-09-11 17:46 ` Golani, Mitulkumar Ajitkumar
1 sibling, 1 reply; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:49 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Hi Ville,
Since we are always disabling when update_m_n, that means if in gaming
mode if VRR enable is requested by userspace, it cannot
be enabled if update_m_n or dual refresh mode is enabled and say we
have downclocked from 120Hz - 60Hz?
Doesnt this contradict the purpose of this series to try and do VRR
update params in fastset because we want VRR range to be
correctly reflected when in dual refresh mode when we downclock from
120-60hz in gaming use case with VRR?
Am I missing something here?
Regards
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make life less confusing by making sure VRR is disabled whenever
> we do any drastic changes to the display timings, such as seamless
> M/N changes.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c20eaf0e7a91..cbbee303cd00 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -916,13 +916,15 @@ static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
> static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - return is_enabling(vrr.enable, old_crtc_state, new_crtc_state);
> + return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> + (new_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> }
>
> static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - return is_disabling(vrr.enable, old_crtc_state, new_crtc_state);
> + return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> + (old_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> }
>
> #undef is_disabling
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes
2023-09-07 18:49 ` Manasi Navare
@ 2023-09-08 5:53 ` Ville Syrjälä
2023-09-08 23:29 ` Manasi Navare
0 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjälä @ 2023-09-08 5:53 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Sep 07, 2023 at 11:49:10AM -0700, Manasi Navare wrote:
> Hi Ville,
>
> Since we are always disabling when update_m_n, that means if in gaming
> mode if VRR enable is requested by userspace, it cannot
> be enabled if update_m_n or dual refresh mode is enabled and say we
> have downclocked from 120Hz - 60Hz?
No, it just means if you have VRR already enabled and want to do
a M/N change VRR gets temporarily disabled and re-enabled during
the commit.
>
> Doesnt this contradict the purpose of this series to try and do VRR
> update params in fastset because we want VRR range to be
> correctly reflected when in dual refresh mode when we downclock from
> 120-60hz in gaming use case with VRR?
>
> Am I missing something here?
>
> Regards
> Manasi
>
> On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Make life less confusing by making sure VRR is disabled whenever
> > we do any drastic changes to the display timings, such as seamless
> > M/N changes.
> >
> > Cc: Manasi Navare <navaremanasi@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index c20eaf0e7a91..cbbee303cd00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -916,13 +916,15 @@ static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
> > static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> > const struct intel_crtc_state *new_crtc_state)
> > {
> > - return is_enabling(vrr.enable, old_crtc_state, new_crtc_state);
> > + return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > + (new_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> > }
> >
> > static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> > const struct intel_crtc_state *new_crtc_state)
> > {
> > - return is_disabling(vrr.enable, old_crtc_state, new_crtc_state);
> > + return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > + (old_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> > }
> >
> > #undef is_disabling
> > --
> > 2.41.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes
2023-09-08 5:53 ` Ville Syrjälä
@ 2023-09-08 23:29 ` Manasi Navare
0 siblings, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-08 23:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Sep 7, 2023 at 10:54 PM Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
>
> On Thu, Sep 07, 2023 at 11:49:10AM -0700, Manasi Navare wrote:
> > Hi Ville,
> >
> > Since we are always disabling when update_m_n, that means if in gaming
> > mode if VRR enable is requested by userspace, it cannot
> > be enabled if update_m_n or dual refresh mode is enabled and say we
> > have downclocked from 120Hz - 60Hz?
>
> No, it just means if you have VRR already enabled and want to do
> a M/N change VRR gets temporarily disabled and re-enabled during
> the commit.
Okay sounds good.
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
>
> >
> > Doesnt this contradict the purpose of this series to try and do VRR
> > update params in fastset because we want VRR range to be
> > correctly reflected when in dual refresh mode when we downclock from
> > 120-60hz in gaming use case with VRR?
> >
> > Am I missing something here?
> >
> > Regards
> > Manasi
> >
> > On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
> > <ville.syrjala@linux.intel.com> wrote:
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Make life less confusing by making sure VRR is disabled whenever
> > > we do any drastic changes to the display timings, such as seamless
> > > M/N changes.
> > >
> > > Cc: Manasi Navare <navaremanasi@chromium.org>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
> > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index c20eaf0e7a91..cbbee303cd00 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -916,13 +916,15 @@ static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
> > > static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> > > const struct intel_crtc_state *new_crtc_state)
> > > {
> > > - return is_enabling(vrr.enable, old_crtc_state, new_crtc_state);
> > > + return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > > + (new_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> > > }
> > >
> > > static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> > > const struct intel_crtc_state *new_crtc_state)
> > > {
> > > - return is_disabling(vrr.enable, old_crtc_state, new_crtc_state);
> > > + return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > > + (old_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> > > }
> > >
> > > #undef is_disabling
> > > --
> > > 2.41.0
> > >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes
2023-09-01 13:04 ` [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes Ville Syrjala
2023-09-07 18:49 ` Manasi Navare
@ 2023-09-11 17:46 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-11 17:46 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless
> M/N changes
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make life less confusing by making sure VRR is disabled whenever we do any
> drastic changes to the display timings, such as seamless M/N changes.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c20eaf0e7a91..cbbee303cd00 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -916,13 +916,15 @@ static bool planes_disabling(const struct
> intel_crtc_state *old_crtc_state, static bool vrr_enabling(const struct
> intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state) {
> - return is_enabling(vrr.enable, old_crtc_state, new_crtc_state);
> + return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> + (new_crtc_state->vrr.enable && new_crtc_state-
> >update_m_n);
> }
>
> static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state) {
> - return is_disabling(vrr.enable, old_crtc_state, new_crtc_state);
> + return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> + (old_crtc_state->vrr.enable && new_crtc_state-
> >update_m_n);
> }
It seems when VRR is already enabled and during seamless M/N changes, disabled VRR and
enabled back again.
Change LGTM.
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>
> #undef is_disabling
> --
> 2.41.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 10/12] drm/i915: Update VRR parameters in fastset
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (8 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-14 17:05 ` Sean Paul
2023-09-01 13:04 ` [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary Ville Syrjala
` (12 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We should be able to change any of the VRR parameters
during fastsets as long as we toggle VRR off at the start
and then back on at the end. The transcoder will be running
in non-VRR mode during the transition.
Co-developed-by: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +++++++++++++++-----
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cbbee303cd00..f0bb5c70ebfc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -913,18 +913,32 @@ static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
return is_disabling(active_planes, old_crtc_state, new_crtc_state);
}
+static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
+ old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
+ old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
+ old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
+ old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
- (new_crtc_state->vrr.enable && new_crtc_state->update_m_n);
+ (new_crtc_state->vrr.enable &&
+ (new_crtc_state->update_m_n ||
+ vrr_params_changed(old_crtc_state, new_crtc_state)));
}
static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
- (old_crtc_state->vrr.enable && new_crtc_state->update_m_n);
+ (old_crtc_state->vrr.enable &&
+ (new_crtc_state->update_m_n ||
+ vrr_params_changed(old_crtc_state, new_crtc_state)));
}
#undef is_disabling
@@ -5342,13 +5356,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(splitter.link_count);
PIPE_CONF_CHECK_I(splitter.pixel_overlap);
- if (!fastset)
+ if (!fastset) {
PIPE_CONF_CHECK_BOOL(vrr.enable);
- PIPE_CONF_CHECK_I(vrr.vmin);
- PIPE_CONF_CHECK_I(vrr.vmax);
- PIPE_CONF_CHECK_I(vrr.flipline);
- PIPE_CONF_CHECK_I(vrr.pipeline_full);
- PIPE_CONF_CHECK_I(vrr.guardband);
+ PIPE_CONF_CHECK_I(vrr.vmin);
+ PIPE_CONF_CHECK_I(vrr.vmax);
+ PIPE_CONF_CHECK_I(vrr.flipline);
+ PIPE_CONF_CHECK_I(vrr.pipeline_full);
+ PIPE_CONF_CHECK_I(vrr.guardband);
+ }
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
@@ -6554,6 +6569,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
if (DISPLAY_VER(i915) >= 11 &&
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
+
+ if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ intel_vrr_set_transcoder_timings(new_crtc_state);
}
intel_fbc_update(state, crtc);
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 10/12] drm/i915: Update VRR parameters in fastset
2023-09-01 13:04 ` [Intel-gfx] [PATCH 10/12] drm/i915: Update VRR parameters in fastset Ville Syrjala
@ 2023-09-14 17:05 ` Sean Paul
0 siblings, 0 replies; 52+ messages in thread
From: Sean Paul @ 2023-09-14 17:05 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Sep 1, 2023 at 9:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We should be able to change any of the VRR parameters
> during fastsets as long as we toggle VRR off at the start
> and then back on at the end. The transcoder will be running
> in non-VRR mode during the transition.
>
> Co-developed-by: Manasi Navare <navaremanasi@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> Signed-off-by: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 34 +++++++++++++++-----
> 1 file changed, 26 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cbbee303cd00..f0bb5c70ebfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -913,18 +913,32 @@ static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
> return is_disabling(active_planes, old_crtc_state, new_crtc_state);
> }
>
> +static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
> + const struct intel_crtc_state *new_crtc_state)
> +{
> + return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
> + old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
> + old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
> + old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
> + old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
> +}
> +
> static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> - (new_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> + (new_crtc_state->vrr.enable &&
> + (new_crtc_state->update_m_n ||
> + vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> - (old_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> + (old_crtc_state->vrr.enable &&
> + (new_crtc_state->update_m_n ||
> + vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> #undef is_disabling
> @@ -5342,13 +5356,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(splitter.link_count);
> PIPE_CONF_CHECK_I(splitter.pixel_overlap);
>
> - if (!fastset)
> + if (!fastset) {
> PIPE_CONF_CHECK_BOOL(vrr.enable);
> - PIPE_CONF_CHECK_I(vrr.vmin);
> - PIPE_CONF_CHECK_I(vrr.vmax);
> - PIPE_CONF_CHECK_I(vrr.flipline);
> - PIPE_CONF_CHECK_I(vrr.pipeline_full);
> - PIPE_CONF_CHECK_I(vrr.guardband);
> + PIPE_CONF_CHECK_I(vrr.vmin);
> + PIPE_CONF_CHECK_I(vrr.vmax);
> + PIPE_CONF_CHECK_I(vrr.flipline);
> + PIPE_CONF_CHECK_I(vrr.pipeline_full);
> + PIPE_CONF_CHECK_I(vrr.guardband);
> + }
>
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> @@ -6554,6 +6569,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> if (DISPLAY_VER(i915) >= 11 &&
> intel_crtc_needs_fastset(new_crtc_state))
> icl_set_pipe_chicken(new_crtc_state);
> +
> + if (vrr_params_changed(old_crtc_state, new_crtc_state))
> + intel_vrr_set_transcoder_timings(new_crtc_state);
> }
>
> intel_fbc_update(state, crtc);
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (9 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 10/12] drm/i915: Update VRR parameters in fastset Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-07 18:49 ` Manasi Navare
2023-09-15 8:34 ` Golani, Mitulkumar Ajitkumar
2023-09-01 13:04 ` [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+ Ville Syrjala
` (11 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Whenever we change the actual transcoder timings (clock via
seamless M/N, full modeset, (or soon) vtotal via LRR) we
want the timing generator to be in non-VRR during the commit.
Warn if we forgot to turn VRR off prior to vblank evasion.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index a04076064f02..a39e31c1ca85 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -493,6 +493,10 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
adjusted_mode = &crtc_state->hw.adjusted_mode;
if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
+ /* timing changes should happen with VRR disabled */
+ drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
+ new_crtc_state->update_m_n);
+
if (intel_vrr_is_push_sent(crtc_state))
*vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
else
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary
2023-09-01 13:04 ` [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary Ville Syrjala
@ 2023-09-07 18:49 ` Manasi Navare
2023-09-15 8:34 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-07 18:49 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Whenever we change the actual transcoder timings (clock via
> seamless M/N, full modeset, (or soon) vtotal via LRR) we
> want the timing generator to be in non-VRR during the commit.
> Warn if we forgot to turn VRR off prior to vblank evasion.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index a04076064f02..a39e31c1ca85 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -493,6 +493,10 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> adjusted_mode = &crtc_state->hw.adjusted_mode;
>
> if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> + /* timing changes should happen with VRR disabled */
> + drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
> + new_crtc_state->update_m_n);
> +
> if (intel_vrr_is_push_sent(crtc_state))
> *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> else
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary
2023-09-01 13:04 ` [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary Ville Syrjala
2023-09-07 18:49 ` Manasi Navare
@ 2023-09-15 8:34 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 52+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-15 8:34 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during
> vblank evasion if necessary
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Whenever we change the actual transcoder timings (clock via seamless M/N,
> full modeset, (or soon) vtotal via LRR) we want the timing generator to be in
> non-VRR during the commit.
> Warn if we forgot to turn VRR off prior to vblank evasion.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index a04076064f02..a39e31c1ca85 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -493,6 +493,10 @@ static void intel_crtc_vblank_evade_scanlines(struct
> intel_atomic_state *state,
> adjusted_mode = &crtc_state->hw.adjusted_mode;
>
> if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> + /* timing changes should happen with VRR disabled */
> + drm_WARN_ON(state->base.dev,
> intel_crtc_needs_modeset(new_crtc_state) ||
> + new_crtc_state->update_m_n);
> +
Changes LGTM
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Regards,
Mitul
> if (intel_vrr_is_push_sent(crtc_state))
> *vblank_start =
> intel_vrr_vmin_vblank_start(crtc_state);
> else
> --
> 2.41.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (10 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary Ville Syrjala
@ 2023-09-01 13:04 ` Ville Syrjala
2023-09-14 23:21 ` Manasi Navare
2023-09-15 10:38 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-09-01 16:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff Patchwork
` (10 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2023-09-01 13:04 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Implement low refresh rate (LRR) where we change the vblank
length by hand as requested, but otherwise keep the timing
generator running in non-VRR mode (ie. fixed refresh rate).
The panel itself must support VRR for this to work, and
only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
we need to make the switch properly. The double buffer
latching happens at the start of transcoders undelayed
vblank. The other thing that we change is
TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
that in DP mode. But I decided to keep writing it anyway
just to avoid more special cases in readout/state check.
v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
the hardware
v3: Reconcile with VRR fastset
Adjust update_lrr flag behaviour
Make sure timings stay within VRR range
TODO: Hook LRR into the automatic DRRS downclocking stuff?
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
drivers/gpu/drm/i915/display/intel_display.c | 60 +++++++++++++++++--
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 3 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
7 files changed, 71 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index aaddd8c0cfa0..5d18145da279 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->update_pipe = false;
crtc_state->update_m_n = false;
+ crtc_state->update_lrr = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
crtc_state->update_wm_pre = false;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index a39e31c1ca85..22e85fe7e8aa 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
/* timing changes should happen with VRR disabled */
drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
- new_crtc_state->update_m_n);
+ new_crtc_state->update_m_n || new_crtc_state->update_lrr);
if (intel_vrr_is_push_sent(crtc_state))
*vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
@@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
*max = *vblank_start - 1;
/*
- * M/N is double buffered on the transcoder's undelayed vblank,
- * so with seamless M/N we must evade both vblanks.
+ * M/N and TRANS_VTOTAL are double buffered on the transcoder's
+ * undelayed vblank, so with seamless M/N and LRR we must evade
+ * both vblanks.
*/
- if (new_crtc_state->update_m_n)
+ if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
*min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f0bb5c70ebfc..74cca5af8b4e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
{
return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
(new_crtc_state->vrr.enable &&
- (new_crtc_state->update_m_n ||
+ (new_crtc_state->update_m_n || new_crtc_state->update_m_n ||
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
@@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
{
return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
(old_crtc_state->vrr.enable &&
- (new_crtc_state->update_m_n ||
+ (new_crtc_state->update_m_n || new_crtc_state->update_m_n ||
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
@@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
VTOTAL(crtc_vtotal - 1));
}
+static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
+
+ crtc_vdisplay = adjusted_mode->crtc_vdisplay;
+ crtc_vtotal = adjusted_mode->crtc_vtotal;
+ crtc_vblank_start = adjusted_mode->crtc_vblank_start;
+ crtc_vblank_end = adjusted_mode->crtc_vblank_end;
+
+ drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
+
+ /*
+ * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
+ * But let's write it anyway to keep the state checker happy.
+ */
+ intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+ VBLANK_START(crtc_vblank_start - 1) |
+ VBLANK_END(crtc_vblank_end - 1));
+ /*
+ * The double buffer latch point for TRANS_VTOTAL
+ * is the transcoder's undelayed vblank.
+ */
+ intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+ VACTIVE(crtc_vdisplay - 1) |
+ VTOTAL(crtc_vtotal - 1));
+}
+
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
- PIPE_CONF_CHECK_I(name.crtc_vtotal); \
PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
- PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+ if (!fastset || !pipe_config->update_lrr) { \
+ PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+ PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+ } \
} while (0)
#define PIPE_CONF_CHECK_RECT(name) do { \
@@ -5420,6 +5453,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
crtc_state->uapi.mode_changed = true;
crtc_state->update_pipe = false;
crtc_state->update_m_n = false;
+ crtc_state->update_lrr = false;
ret = drm_atomic_add_affected_connectors(&state->base,
&crtc->base);
@@ -5537,6 +5571,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
{
struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
+ /* only allow LRR when the timings stay within the VRR range */
+ if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
+ new_crtc_state->update_lrr = false;
+
if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
else
@@ -5547,6 +5585,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
&new_crtc_state->dp_m_n))
new_crtc_state->update_m_n = false;
+ if (intel_crtc_needs_modeset(new_crtc_state) ||
+ (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
+ old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
+ new_crtc_state->update_lrr = false;
+
if (!intel_crtc_needs_modeset(new_crtc_state))
new_crtc_state->update_pipe = true;
}
@@ -6262,6 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
new_crtc_state->update_m_n = false;
+ new_crtc_state->update_lrr = false;
}
}
@@ -6275,6 +6319,7 @@ int intel_atomic_check(struct drm_device *dev,
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
new_crtc_state->update_m_n = false;
+ new_crtc_state->update_lrr = false;
}
}
@@ -6283,6 +6328,7 @@ int intel_atomic_check(struct drm_device *dev,
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
new_crtc_state->update_m_n = false;
+ new_crtc_state->update_lrr = false;
}
}
}
@@ -6464,6 +6510,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
if (new_crtc_state->update_m_n)
intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
&new_crtc_state->dp_m_n);
+
+ if (new_crtc_state->update_lrr)
+ intel_set_transcoder_timings_lrr(new_crtc_state);
}
static void commit_pipe_pre_planes(struct intel_atomic_state *state,
@@ -6600,7 +6649,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
*
* FIXME Should be synchronized with the start of vblank somehow...
*/
- if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
+ if (vrr_enabling(old_crtc_state, new_crtc_state) ||
+ new_crtc_state->update_m_n || new_crtc_state->update_lrr)
intel_crtc_update_active_timings(new_crtc_state,
new_crtc_state->vrr.enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 8198401aa5be..ee77750af82b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -56,6 +56,7 @@ struct drm_printer;
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
#define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
+#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2f35560d7e4e..536c642eb562 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1084,6 +1084,7 @@ struct intel_crtc_state {
unsigned fb_bits; /* framebuffers to flip */
bool update_pipe; /* can a fast modeset be performed? */
bool update_m_n; /* update M/N seamlessly during fastset? */
+ bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
bool disable_cxsr;
bool update_wm_pre, update_wm_post; /* watermarks are updated */
bool fifo_changed; /* FIFO split is changed */
@@ -1383,7 +1384,7 @@ struct intel_crtc_state {
/* Variable Refresh Rate state */
struct {
- bool enable;
+ bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
} vrr;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 12731ad725a8..5d905f932cb4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -120,9 +120,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
return;
- if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
+ crtc_state->vrr.in_range =
+ intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
+ if (!crtc_state->vrr.in_range)
return;
+ if (HAS_LRR(i915))
+ crtc_state->update_lrr = true;
+
vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
vmax = adjusted_mode->crtc_clock * 1000 /
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00e4d569ba9..26cc03832f73 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5628,6 +5628,7 @@ enum skl_power_gate {
#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
+#define DOUBLE_BUFFER_VACTIVE REG_BIT(8) /* tgl+ */
#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+
2023-09-01 13:04 ` [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+ Ville Syrjala
@ 2023-09-14 23:21 ` Manasi Navare
2023-09-15 10:23 ` Ville Syrjälä
2023-09-15 10:38 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
1 sibling, 1 reply; 52+ messages in thread
From: Manasi Navare @ 2023-09-14 23:21 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Implement low refresh rate (LRR) where we change the vblank
> length by hand as requested, but otherwise keep the timing
> generator running in non-VRR mode (ie. fixed refresh rate).
>
> The panel itself must support VRR for this to work, and
> only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
> we need to make the switch properly. The double buffer
> latching happens at the start of transcoders undelayed
> vblank. The other thing that we change is
> TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
> that in DP mode. But I decided to keep writing it anyway
> just to avoid more special cases in readout/state check.
>
> v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
> the hardware
> v3: Reconcile with VRR fastset
> Adjust update_lrr flag behaviour
> Make sure timings stay within VRR range
>
> TODO: Hook LRR into the automatic DRRS downclocking stuff?
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
> drivers/gpu/drm/i915/display/intel_display.c | 60 +++++++++++++++++--
> .../drm/i915/display/intel_display_device.h | 1 +
> .../drm/i915/display/intel_display_types.h | 3 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 7 files changed, 71 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index aaddd8c0cfa0..5d18145da279 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>
> crtc_state->update_pipe = false;
> crtc_state->update_m_n = false;
> + crtc_state->update_lrr = false;
> crtc_state->disable_lp_wm = false;
> crtc_state->disable_cxsr = false;
> crtc_state->update_wm_pre = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index a39e31c1ca85..22e85fe7e8aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> /* timing changes should happen with VRR disabled */
> drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
> - new_crtc_state->update_m_n);
> + new_crtc_state->update_m_n || new_crtc_state->update_lrr);
>
> if (intel_vrr_is_push_sent(crtc_state))
> *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> @@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> *max = *vblank_start - 1;
>
> /*
> - * M/N is double buffered on the transcoder's undelayed vblank,
> - * so with seamless M/N we must evade both vblanks.
> + * M/N and TRANS_VTOTAL are double buffered on the transcoder's
> + * undelayed vblank, so with seamless M/N and LRR we must evade
> + * both vblanks.
> */
> - if (new_crtc_state->update_m_n)
> + if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f0bb5c70ebfc..74cca5af8b4e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> {
> return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> (new_crtc_state->vrr.enable &&
> - (new_crtc_state->update_m_n ||
> + (new_crtc_state->update_m_n || new_crtc_state->update_m_n ||
Did you mean to add new_crtc_state->update_lrr in the condition for
vrr_enabling ?
> vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> @@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> {
> return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> (old_crtc_state->vrr.enable &&
> - (new_crtc_state->update_m_n ||
> + (new_crtc_state->update_m_n || new_crtc_state->update_m_n ||
> vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> @@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> VTOTAL(crtc_vtotal - 1));
> }
>
> +static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> +
> + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> + crtc_vtotal = adjusted_mode->crtc_vtotal;
> + crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> + crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> +
> + drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
> +
> + /*
> + * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
> + * But let's write it anyway to keep the state checker happy.
> + */
> + intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> + VBLANK_START(crtc_vblank_start - 1) |
> + VBLANK_END(crtc_vblank_end - 1));
> + /*
> + * The double buffer latch point for TRANS_VTOTAL
> + * is the transcoder's undelayed vblank.
> + */
> + intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> + VACTIVE(crtc_vdisplay - 1) |
> + VTOTAL(crtc_vtotal - 1));
> +}
> +
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> - PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> - PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> + if (!fastset || !pipe_config->update_lrr) { \
> + PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> + PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> + } \
> } while (0)
>
> #define PIPE_CONF_CHECK_RECT(name) do { \
> @@ -5420,6 +5453,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> crtc_state->uapi.mode_changed = true;
> crtc_state->update_pipe = false;
> crtc_state->update_m_n = false;
> + crtc_state->update_lrr = false;
>
> ret = drm_atomic_add_affected_connectors(&state->base,
> &crtc->base);
> @@ -5537,6 +5571,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> {
> struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
>
> + /* only allow LRR when the timings stay within the VRR range */
> + if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
> + new_crtc_state->update_lrr = false;
> +
> if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
> else
> @@ -5547,6 +5585,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> &new_crtc_state->dp_m_n))
> new_crtc_state->update_m_n = false;
>
> + if (intel_crtc_needs_modeset(new_crtc_state) ||
> + (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> + old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
> + new_crtc_state->update_lrr = false;
> +
> if (!intel_crtc_needs_modeset(new_crtc_state))
> new_crtc_state->update_pipe = true;
> }
> @@ -6262,6 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> new_crtc_state->update_m_n = false;
> + new_crtc_state->update_lrr = false;
> }
> }
>
> @@ -6275,6 +6319,7 @@ int intel_atomic_check(struct drm_device *dev,
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> new_crtc_state->update_m_n = false;
> + new_crtc_state->update_lrr = false;
> }
> }
>
> @@ -6283,6 +6328,7 @@ int intel_atomic_check(struct drm_device *dev,
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> new_crtc_state->update_m_n = false;
> + new_crtc_state->update_lrr = false;
> }
> }
> }
> @@ -6464,6 +6510,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> if (new_crtc_state->update_m_n)
> intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
> &new_crtc_state->dp_m_n);
> +
> + if (new_crtc_state->update_lrr)
> + intel_set_transcoder_timings_lrr(new_crtc_state);
> }
>
> static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> @@ -6600,7 +6649,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> *
> * FIXME Should be synchronized with the start of vblank somehow...
> */
> - if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
> + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> + new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> intel_crtc_update_active_timings(new_crtc_state,
> new_crtc_state->vrr.enable);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 8198401aa5be..ee77750af82b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -56,6 +56,7 @@ struct drm_printer;
> #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
> +#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
> #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
> #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
> #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2f35560d7e4e..536c642eb562 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1084,6 +1084,7 @@ struct intel_crtc_state {
> unsigned fb_bits; /* framebuffers to flip */
> bool update_pipe; /* can a fast modeset be performed? */
> bool update_m_n; /* update M/N seamlessly during fastset? */
> + bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
> bool disable_cxsr;
> bool update_wm_pre, update_wm_post; /* watermarks are updated */
> bool fifo_changed; /* FIFO split is changed */
> @@ -1383,7 +1384,7 @@ struct intel_crtc_state {
>
> /* Variable Refresh Rate state */
> struct {
> - bool enable;
> + bool enable, in_range;
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> } vrr;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 12731ad725a8..5d905f932cb4 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -120,9 +120,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> return;
>
> - if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
> + crtc_state->vrr.in_range =
> + intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
> + if (!crtc_state->vrr.in_range)
> return;
>
> + if (HAS_LRR(i915))
> + crtc_state->update_lrr = true;
> +
> vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
> vmax = adjusted_mode->crtc_clock * 1000 /
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e00e4d569ba9..26cc03832f73 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5628,6 +5628,7 @@ enum skl_power_gate {
> #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
> #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
> #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
> +#define DOUBLE_BUFFER_VACTIVE REG_BIT(8) /* tgl+ */
This reg bit is not used anywhere in this patch.
Regards
Manasi
> #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
> #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
> #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+
2023-09-14 23:21 ` Manasi Navare
@ 2023-09-15 10:23 ` Ville Syrjälä
0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2023-09-15 10:23 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Sep 14, 2023 at 04:21:18PM -0700, Manasi Navare wrote:
> On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Implement low refresh rate (LRR) where we change the vblank
> > length by hand as requested, but otherwise keep the timing
> > generator running in non-VRR mode (ie. fixed refresh rate).
> >
> > The panel itself must support VRR for this to work, and
> > only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
> > we need to make the switch properly. The double buffer
> > latching happens at the start of transcoders undelayed
> > vblank. The other thing that we change is
> > TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
> > that in DP mode. But I decided to keep writing it anyway
> > just to avoid more special cases in readout/state check.
> >
> > v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
> > the hardware
> > v3: Reconcile with VRR fastset
> > Adjust update_lrr flag behaviour
> > Make sure timings stay within VRR range
> >
> > TODO: Hook LRR into the automatic DRRS downclocking stuff?
> >
> > Cc: Manasi Navare <navaremanasi@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
> > drivers/gpu/drm/i915/display/intel_display.c | 60 +++++++++++++++++--
> > .../drm/i915/display/intel_display_device.h | 1 +
> > .../drm/i915/display/intel_display_types.h | 3 +-
> > drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 7 files changed, 71 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index aaddd8c0cfa0..5d18145da279 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> >
> > crtc_state->update_pipe = false;
> > crtc_state->update_m_n = false;
> > + crtc_state->update_lrr = false;
> > crtc_state->disable_lp_wm = false;
> > crtc_state->disable_cxsr = false;
> > crtc_state->update_wm_pre = false;
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index a39e31c1ca85..22e85fe7e8aa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> > /* timing changes should happen with VRR disabled */
> > drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
> > - new_crtc_state->update_m_n);
> > + new_crtc_state->update_m_n || new_crtc_state->update_lrr);
> >
> > if (intel_vrr_is_push_sent(crtc_state))
> > *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> > @@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > *max = *vblank_start - 1;
> >
> > /*
> > - * M/N is double buffered on the transcoder's undelayed vblank,
> > - * so with seamless M/N we must evade both vblanks.
> > + * M/N and TRANS_VTOTAL are double buffered on the transcoder's
> > + * undelayed vblank, so with seamless M/N and LRR we must evade
> > + * both vblanks.
> > */
> > - if (new_crtc_state->update_m_n)
> > + if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> > *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f0bb5c70ebfc..74cca5af8b4e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> > {
> > return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > (new_crtc_state->vrr.enable &&
> > - (new_crtc_state->update_m_n ||
> > + (new_crtc_state->update_m_n || new_crtc_state->update_m_n ||
>
> Did you mean to add new_crtc_state->update_lrr in the condition for
> vrr_enabling ?
Aye. Good catch. Looks like a rebase fail on my part.
>
> > vrr_params_changed(old_crtc_state, new_crtc_state)));
> > }
> >
> > @@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> > {
> > return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > (old_crtc_state->vrr.enable &&
> > - (new_crtc_state->update_m_n ||
> > + (new_crtc_state->update_m_n || new_crtc_state->update_m_n ||
> > vrr_params_changed(old_crtc_state, new_crtc_state)));
> > }
> >
> > @@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> > VTOTAL(crtc_vtotal - 1));
> > }
> >
> > +static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> > + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > +
> > + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > + crtc_vtotal = adjusted_mode->crtc_vtotal;
> > + crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> > + crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > +
> > + drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
> > +
> > + /*
> > + * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
> > + * But let's write it anyway to keep the state checker happy.
> > + */
> > + intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> > + VBLANK_START(crtc_vblank_start - 1) |
> > + VBLANK_END(crtc_vblank_end - 1));
> > + /*
> > + * The double buffer latch point for TRANS_VTOTAL
> > + * is the transcoder's undelayed vblank.
> > + */
> > + intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> > + VACTIVE(crtc_vdisplay - 1) |
> > + VTOTAL(crtc_vtotal - 1));
> > +}
> > +
> > static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> > PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> > PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> > - PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> > PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> > - PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> > PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> > PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> > + if (!fastset || !pipe_config->update_lrr) { \
> > + PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> > + PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> > + } \
> > } while (0)
> >
> > #define PIPE_CONF_CHECK_RECT(name) do { \
> > @@ -5420,6 +5453,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > crtc_state->uapi.mode_changed = true;
> > crtc_state->update_pipe = false;
> > crtc_state->update_m_n = false;
> > + crtc_state->update_lrr = false;
> >
> > ret = drm_atomic_add_affected_connectors(&state->base,
> > &crtc->base);
> > @@ -5537,6 +5571,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > {
> > struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
> >
> > + /* only allow LRR when the timings stay within the VRR range */
> > + if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
> > + new_crtc_state->update_lrr = false;
> > +
> > if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> > drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
> > else
> > @@ -5547,6 +5585,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > &new_crtc_state->dp_m_n))
> > new_crtc_state->update_m_n = false;
> >
> > + if (intel_crtc_needs_modeset(new_crtc_state) ||
> > + (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> > + old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
> > + new_crtc_state->update_lrr = false;
> > +
> > if (!intel_crtc_needs_modeset(new_crtc_state))
> > new_crtc_state->update_pipe = true;
> > }
> > @@ -6262,6 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > new_crtc_state->update_m_n = false;
> > + new_crtc_state->update_lrr = false;
> > }
> > }
> >
> > @@ -6275,6 +6319,7 @@ int intel_atomic_check(struct drm_device *dev,
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > new_crtc_state->update_m_n = false;
> > + new_crtc_state->update_lrr = false;
> > }
> > }
> >
> > @@ -6283,6 +6328,7 @@ int intel_atomic_check(struct drm_device *dev,
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > new_crtc_state->update_m_n = false;
> > + new_crtc_state->update_lrr = false;
> > }
> > }
> > }
> > @@ -6464,6 +6510,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> > if (new_crtc_state->update_m_n)
> > intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
> > &new_crtc_state->dp_m_n);
> > +
> > + if (new_crtc_state->update_lrr)
> > + intel_set_transcoder_timings_lrr(new_crtc_state);
> > }
> >
> > static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> > @@ -6600,7 +6649,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > *
> > * FIXME Should be synchronized with the start of vblank somehow...
> > */
> > - if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
> > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > + new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> > intel_crtc_update_active_timings(new_crtc_state,
> > new_crtc_state->vrr.enable);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 8198401aa5be..ee77750af82b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -56,6 +56,7 @@ struct drm_printer;
> > #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> > #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> > #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
> > +#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
> > #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
> > #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
> > #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 2f35560d7e4e..536c642eb562 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1084,6 +1084,7 @@ struct intel_crtc_state {
> > unsigned fb_bits; /* framebuffers to flip */
> > bool update_pipe; /* can a fast modeset be performed? */
> > bool update_m_n; /* update M/N seamlessly during fastset? */
> > + bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
> > bool disable_cxsr;
> > bool update_wm_pre, update_wm_post; /* watermarks are updated */
> > bool fifo_changed; /* FIFO split is changed */
> > @@ -1383,7 +1384,7 @@ struct intel_crtc_state {
> >
> > /* Variable Refresh Rate state */
> > struct {
> > - bool enable;
> > + bool enable, in_range;
> > u8 pipeline_full;
> > u16 flipline, vmin, vmax, guardband;
> > } vrr;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 12731ad725a8..5d905f932cb4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -120,9 +120,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> > if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> > return;
> >
> > - if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
> > + crtc_state->vrr.in_range =
> > + intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
> > + if (!crtc_state->vrr.in_range)
> > return;
> >
> > + if (HAS_LRR(i915))
> > + crtc_state->update_lrr = true;
> > +
> > vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> > adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
> > vmax = adjusted_mode->crtc_clock * 1000 /
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e00e4d569ba9..26cc03832f73 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5628,6 +5628,7 @@ enum skl_power_gate {
> > #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
> > #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
> > #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
> > +#define DOUBLE_BUFFER_VACTIVE REG_BIT(8) /* tgl+ */
>
> This reg bit is not used anywhere in this patch.
Yeah, originally I thought it might affect this. But I *think* it
actually only affects DSI transcoders. The spec is a bit of a mess
around this stuff tbh.
>
> Regards
> Manasi
>
> > #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
> > #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
> > #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
> > --
> > 2.41.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+
2023-09-01 13:04 ` [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+ Ville Syrjala
2023-09-14 23:21 ` Manasi Navare
@ 2023-09-15 10:38 ` Ville Syrjala
2023-09-18 23:16 ` Manasi Navare
1 sibling, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2023-09-15 10:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Implement low refresh rate (LRR) where we change the vblank
length by hand as requested, but otherwise keep the timing
generator running in non-VRR mode (ie. fixed refresh rate).
The panel itself must support VRR for this to work, and
only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
we need to make the switch properly. The double buffer
latching happens at the start of transcoders undelayed
vblank. The other thing that we change is
TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
that in DP mode. But I decided to keep writing it anyway
just to avoid more special cases in readout/state check.
v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
the hardware
v3: Reconcile with VRR fastset
Adjust update_lrr flag behaviour
Make sure timings stay within VRR range
v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi)
Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi)
TODO: Hook LRR into the automatic DRRS downclocking stuff?
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
drivers/gpu/drm/i915/display/intel_display.c | 60 +++++++++++++++++--
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 3 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
6 files changed, 70 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index aaddd8c0cfa0..5d18145da279 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->update_pipe = false;
crtc_state->update_m_n = false;
+ crtc_state->update_lrr = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
crtc_state->update_wm_pre = false;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index a39e31c1ca85..22e85fe7e8aa 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
/* timing changes should happen with VRR disabled */
drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
- new_crtc_state->update_m_n);
+ new_crtc_state->update_m_n || new_crtc_state->update_lrr);
if (intel_vrr_is_push_sent(crtc_state))
*vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
@@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
*max = *vblank_start - 1;
/*
- * M/N is double buffered on the transcoder's undelayed vblank,
- * so with seamless M/N we must evade both vblanks.
+ * M/N and TRANS_VTOTAL are double buffered on the transcoder's
+ * undelayed vblank, so with seamless M/N and LRR we must evade
+ * both vblanks.
*/
- if (new_crtc_state->update_m_n)
+ if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
*min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f0bb5c70ebfc..988558ccf794 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
{
return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
(new_crtc_state->vrr.enable &&
- (new_crtc_state->update_m_n ||
+ (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
@@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
{
return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
(old_crtc_state->vrr.enable &&
- (new_crtc_state->update_m_n ||
+ (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
@@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
VTOTAL(crtc_vtotal - 1));
}
+static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
+
+ crtc_vdisplay = adjusted_mode->crtc_vdisplay;
+ crtc_vtotal = adjusted_mode->crtc_vtotal;
+ crtc_vblank_start = adjusted_mode->crtc_vblank_start;
+ crtc_vblank_end = adjusted_mode->crtc_vblank_end;
+
+ drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
+
+ /*
+ * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
+ * But let's write it anyway to keep the state checker happy.
+ */
+ intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+ VBLANK_START(crtc_vblank_start - 1) |
+ VBLANK_END(crtc_vblank_end - 1));
+ /*
+ * The double buffer latch point for TRANS_VTOTAL
+ * is the transcoder's undelayed vblank.
+ */
+ intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+ VACTIVE(crtc_vdisplay - 1) |
+ VTOTAL(crtc_vtotal - 1));
+}
+
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
- PIPE_CONF_CHECK_I(name.crtc_vtotal); \
PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
- PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+ if (!fastset || !pipe_config->update_lrr) { \
+ PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+ PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+ } \
} while (0)
#define PIPE_CONF_CHECK_RECT(name) do { \
@@ -5420,6 +5453,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
crtc_state->uapi.mode_changed = true;
crtc_state->update_pipe = false;
crtc_state->update_m_n = false;
+ crtc_state->update_lrr = false;
ret = drm_atomic_add_affected_connectors(&state->base,
&crtc->base);
@@ -5537,6 +5571,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
{
struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
+ /* only allow LRR when the timings stay within the VRR range */
+ if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
+ new_crtc_state->update_lrr = false;
+
if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
else
@@ -5547,6 +5585,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
&new_crtc_state->dp_m_n))
new_crtc_state->update_m_n = false;
+ if (intel_crtc_needs_modeset(new_crtc_state) ||
+ (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
+ old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
+ new_crtc_state->update_lrr = false;
+
if (!intel_crtc_needs_modeset(new_crtc_state))
new_crtc_state->update_pipe = true;
}
@@ -6262,6 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
new_crtc_state->update_m_n = false;
+ new_crtc_state->update_lrr = false;
}
}
@@ -6275,6 +6319,7 @@ int intel_atomic_check(struct drm_device *dev,
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
new_crtc_state->update_m_n = false;
+ new_crtc_state->update_lrr = false;
}
}
@@ -6283,6 +6328,7 @@ int intel_atomic_check(struct drm_device *dev,
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
new_crtc_state->update_m_n = false;
+ new_crtc_state->update_lrr = false;
}
}
}
@@ -6464,6 +6510,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
if (new_crtc_state->update_m_n)
intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
&new_crtc_state->dp_m_n);
+
+ if (new_crtc_state->update_lrr)
+ intel_set_transcoder_timings_lrr(new_crtc_state);
}
static void commit_pipe_pre_planes(struct intel_atomic_state *state,
@@ -6600,7 +6649,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
*
* FIXME Should be synchronized with the start of vblank somehow...
*/
- if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
+ if (vrr_enabling(old_crtc_state, new_crtc_state) ||
+ new_crtc_state->update_m_n || new_crtc_state->update_lrr)
intel_crtc_update_active_timings(new_crtc_state,
new_crtc_state->vrr.enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 8198401aa5be..ee77750af82b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -56,6 +56,7 @@ struct drm_printer;
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
#define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
+#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2f35560d7e4e..536c642eb562 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1084,6 +1084,7 @@ struct intel_crtc_state {
unsigned fb_bits; /* framebuffers to flip */
bool update_pipe; /* can a fast modeset be performed? */
bool update_m_n; /* update M/N seamlessly during fastset? */
+ bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
bool disable_cxsr;
bool update_wm_pre, update_wm_post; /* watermarks are updated */
bool fifo_changed; /* FIFO split is changed */
@@ -1383,7 +1384,7 @@ struct intel_crtc_state {
/* Variable Refresh Rate state */
struct {
- bool enable;
+ bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
} vrr;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 12731ad725a8..5d905f932cb4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -120,9 +120,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
return;
- if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
+ crtc_state->vrr.in_range =
+ intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
+ if (!crtc_state->vrr.in_range)
return;
+ if (HAS_LRR(i915))
+ crtc_state->update_lrr = true;
+
vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
vmax = adjusted_mode->crtc_clock * 1000 /
--
2.41.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+
2023-09-15 10:38 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2023-09-18 23:16 ` Manasi Navare
2023-09-20 18:47 ` Manasi Navare
0 siblings, 1 reply; 52+ messages in thread
From: Manasi Navare @ 2023-09-18 23:16 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Thanks Ville for the respin, the changes look good now.
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Fri, Sep 15, 2023 at 3:38 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Implement low refresh rate (LRR) where we change the vblank
> length by hand as requested, but otherwise keep the timing
> generator running in non-VRR mode (ie. fixed refresh rate).
>
> The panel itself must support VRR for this to work, and
> only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
> we need to make the switch properly. The double buffer
> latching happens at the start of transcoders undelayed
> vblank. The other thing that we change is
> TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
> that in DP mode. But I decided to keep writing it anyway
> just to avoid more special cases in readout/state check.
>
> v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
> the hardware
> v3: Reconcile with VRR fastset
> Adjust update_lrr flag behaviour
> Make sure timings stay within VRR range
> v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi)
> Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi)
>
> TODO: Hook LRR into the automatic DRRS downclocking stuff?
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
> drivers/gpu/drm/i915/display/intel_display.c | 60 +++++++++++++++++--
> .../drm/i915/display/intel_display_device.h | 1 +
> .../drm/i915/display/intel_display_types.h | 3 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
> 6 files changed, 70 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index aaddd8c0cfa0..5d18145da279 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>
> crtc_state->update_pipe = false;
> crtc_state->update_m_n = false;
> + crtc_state->update_lrr = false;
> crtc_state->disable_lp_wm = false;
> crtc_state->disable_cxsr = false;
> crtc_state->update_wm_pre = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index a39e31c1ca85..22e85fe7e8aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> /* timing changes should happen with VRR disabled */
> drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
> - new_crtc_state->update_m_n);
> + new_crtc_state->update_m_n || new_crtc_state->update_lrr);
>
> if (intel_vrr_is_push_sent(crtc_state))
> *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> @@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> *max = *vblank_start - 1;
>
> /*
> - * M/N is double buffered on the transcoder's undelayed vblank,
> - * so with seamless M/N we must evade both vblanks.
> + * M/N and TRANS_VTOTAL are double buffered on the transcoder's
> + * undelayed vblank, so with seamless M/N and LRR we must evade
> + * both vblanks.
> */
> - if (new_crtc_state->update_m_n)
> + if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f0bb5c70ebfc..988558ccf794 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> {
> return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> (new_crtc_state->vrr.enable &&
> - (new_crtc_state->update_m_n ||
> + (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
> vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> @@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> {
> return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> (old_crtc_state->vrr.enable &&
> - (new_crtc_state->update_m_n ||
> + (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
> vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> @@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> VTOTAL(crtc_vtotal - 1));
> }
>
> +static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> +
> + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> + crtc_vtotal = adjusted_mode->crtc_vtotal;
> + crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> + crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> +
> + drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
> +
> + /*
> + * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
> + * But let's write it anyway to keep the state checker happy.
> + */
> + intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> + VBLANK_START(crtc_vblank_start - 1) |
> + VBLANK_END(crtc_vblank_end - 1));
> + /*
> + * The double buffer latch point for TRANS_VTOTAL
> + * is the transcoder's undelayed vblank.
> + */
> + intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> + VACTIVE(crtc_vdisplay - 1) |
> + VTOTAL(crtc_vtotal - 1));
> +}
> +
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> - PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> - PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> + if (!fastset || !pipe_config->update_lrr) { \
> + PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> + PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> + } \
> } while (0)
>
> #define PIPE_CONF_CHECK_RECT(name) do { \
> @@ -5420,6 +5453,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> crtc_state->uapi.mode_changed = true;
> crtc_state->update_pipe = false;
> crtc_state->update_m_n = false;
> + crtc_state->update_lrr = false;
>
> ret = drm_atomic_add_affected_connectors(&state->base,
> &crtc->base);
> @@ -5537,6 +5571,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> {
> struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
>
> + /* only allow LRR when the timings stay within the VRR range */
> + if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
> + new_crtc_state->update_lrr = false;
> +
> if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
> else
> @@ -5547,6 +5585,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> &new_crtc_state->dp_m_n))
> new_crtc_state->update_m_n = false;
>
> + if (intel_crtc_needs_modeset(new_crtc_state) ||
> + (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> + old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
> + new_crtc_state->update_lrr = false;
> +
> if (!intel_crtc_needs_modeset(new_crtc_state))
> new_crtc_state->update_pipe = true;
> }
> @@ -6262,6 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> new_crtc_state->update_m_n = false;
> + new_crtc_state->update_lrr = false;
> }
> }
>
> @@ -6275,6 +6319,7 @@ int intel_atomic_check(struct drm_device *dev,
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> new_crtc_state->update_m_n = false;
> + new_crtc_state->update_lrr = false;
> }
> }
>
> @@ -6283,6 +6328,7 @@ int intel_atomic_check(struct drm_device *dev,
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> new_crtc_state->update_m_n = false;
> + new_crtc_state->update_lrr = false;
> }
> }
> }
> @@ -6464,6 +6510,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> if (new_crtc_state->update_m_n)
> intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
> &new_crtc_state->dp_m_n);
> +
> + if (new_crtc_state->update_lrr)
> + intel_set_transcoder_timings_lrr(new_crtc_state);
> }
>
> static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> @@ -6600,7 +6649,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> *
> * FIXME Should be synchronized with the start of vblank somehow...
> */
> - if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
> + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> + new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> intel_crtc_update_active_timings(new_crtc_state,
> new_crtc_state->vrr.enable);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 8198401aa5be..ee77750af82b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -56,6 +56,7 @@ struct drm_printer;
> #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
> +#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
> #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
> #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
> #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2f35560d7e4e..536c642eb562 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1084,6 +1084,7 @@ struct intel_crtc_state {
> unsigned fb_bits; /* framebuffers to flip */
> bool update_pipe; /* can a fast modeset be performed? */
> bool update_m_n; /* update M/N seamlessly during fastset? */
> + bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
> bool disable_cxsr;
> bool update_wm_pre, update_wm_post; /* watermarks are updated */
> bool fifo_changed; /* FIFO split is changed */
> @@ -1383,7 +1384,7 @@ struct intel_crtc_state {
>
> /* Variable Refresh Rate state */
> struct {
> - bool enable;
> + bool enable, in_range;
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> } vrr;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 12731ad725a8..5d905f932cb4 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -120,9 +120,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> return;
>
> - if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
> + crtc_state->vrr.in_range =
> + intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
> + if (!crtc_state->vrr.in_range)
> return;
>
> + if (HAS_LRR(i915))
> + crtc_state->update_lrr = true;
> +
> vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
> vmax = adjusted_mode->crtc_clock * 1000 /
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+
2023-09-18 23:16 ` Manasi Navare
@ 2023-09-20 18:47 ` Manasi Navare
2023-09-20 19:40 ` Ville Syrjälä
0 siblings, 1 reply; 52+ messages in thread
From: Manasi Navare @ 2023-09-20 18:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Hi Ville,
Quick question here on the use case and the trigger for the LRR case
which is within VRR range.
Could this perhaps be used if we had a virtual mode say 40Hz that now
falls in the VRR range (30 -120Hz) that is
exposed through the connector mode list and then if we do a modest to
40Hz that would make update_lrr = true within VRR and
hand adjust the vtotal to that exact value?
I am looking at adding this virtual mode to DRM soon, wondering if
this would be how the kernel would actual set the timings for it.
Regards
Manasi
On Mon, Sep 18, 2023 at 4:16 PM Manasi Navare <navaremanasi@chromium.org> wrote:
>
> Thanks Ville for the respin, the changes look good now.
>
> Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
>
> Manasi
>
>
> On Fri, Sep 15, 2023 at 3:38 AM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Implement low refresh rate (LRR) where we change the vblank
> > length by hand as requested, but otherwise keep the timing
> > generator running in non-VRR mode (ie. fixed refresh rate).
> >
> > The panel itself must support VRR for this to work, and
> > only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
> > we need to make the switch properly. The double buffer
> > latching happens at the start of transcoders undelayed
> > vblank. The other thing that we change is
> > TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
> > that in DP mode. But I decided to keep writing it anyway
> > just to avoid more special cases in readout/state check.
> >
> > v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
> > the hardware
> > v3: Reconcile with VRR fastset
> > Adjust update_lrr flag behaviour
> > Make sure timings stay within VRR range
> > v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi)
> > Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi)
> >
> > TODO: Hook LRR into the automatic DRRS downclocking stuff?
> >
> > Cc: Manasi Navare <navaremanasi@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
> > drivers/gpu/drm/i915/display/intel_display.c | 60 +++++++++++++++++--
> > .../drm/i915/display/intel_display_device.h | 1 +
> > .../drm/i915/display/intel_display_types.h | 3 +-
> > drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
> > 6 files changed, 70 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index aaddd8c0cfa0..5d18145da279 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> >
> > crtc_state->update_pipe = false;
> > crtc_state->update_m_n = false;
> > + crtc_state->update_lrr = false;
> > crtc_state->disable_lp_wm = false;
> > crtc_state->disable_cxsr = false;
> > crtc_state->update_wm_pre = false;
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index a39e31c1ca85..22e85fe7e8aa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> > /* timing changes should happen with VRR disabled */
> > drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
> > - new_crtc_state->update_m_n);
> > + new_crtc_state->update_m_n || new_crtc_state->update_lrr);
> >
> > if (intel_vrr_is_push_sent(crtc_state))
> > *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> > @@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > *max = *vblank_start - 1;
> >
> > /*
> > - * M/N is double buffered on the transcoder's undelayed vblank,
> > - * so with seamless M/N we must evade both vblanks.
> > + * M/N and TRANS_VTOTAL are double buffered on the transcoder's
> > + * undelayed vblank, so with seamless M/N and LRR we must evade
> > + * both vblanks.
> > */
> > - if (new_crtc_state->update_m_n)
> > + if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> > *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f0bb5c70ebfc..988558ccf794 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> > {
> > return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > (new_crtc_state->vrr.enable &&
> > - (new_crtc_state->update_m_n ||
> > + (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
> > vrr_params_changed(old_crtc_state, new_crtc_state)));
> > }
> >
> > @@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> > {
> > return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > (old_crtc_state->vrr.enable &&
> > - (new_crtc_state->update_m_n ||
> > + (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
> > vrr_params_changed(old_crtc_state, new_crtc_state)));
> > }
> >
> > @@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> > VTOTAL(crtc_vtotal - 1));
> > }
> >
> > +static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> > + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > +
> > + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > + crtc_vtotal = adjusted_mode->crtc_vtotal;
> > + crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> > + crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > +
> > + drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
> > +
> > + /*
> > + * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
> > + * But let's write it anyway to keep the state checker happy.
> > + */
> > + intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> > + VBLANK_START(crtc_vblank_start - 1) |
> > + VBLANK_END(crtc_vblank_end - 1));
> > + /*
> > + * The double buffer latch point for TRANS_VTOTAL
> > + * is the transcoder's undelayed vblank.
> > + */
> > + intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> > + VACTIVE(crtc_vdisplay - 1) |
> > + VTOTAL(crtc_vtotal - 1));
> > +}
> > +
> > static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> > PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> > PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> > - PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> > PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> > - PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> > PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> > PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> > + if (!fastset || !pipe_config->update_lrr) { \
> > + PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> > + PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> > + } \
> > } while (0)
> >
> > #define PIPE_CONF_CHECK_RECT(name) do { \
> > @@ -5420,6 +5453,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > crtc_state->uapi.mode_changed = true;
> > crtc_state->update_pipe = false;
> > crtc_state->update_m_n = false;
> > + crtc_state->update_lrr = false;
> >
> > ret = drm_atomic_add_affected_connectors(&state->base,
> > &crtc->base);
> > @@ -5537,6 +5571,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > {
> > struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
> >
> > + /* only allow LRR when the timings stay within the VRR range */
> > + if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
> > + new_crtc_state->update_lrr = false;
> > +
> > if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> > drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
> > else
> > @@ -5547,6 +5585,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > &new_crtc_state->dp_m_n))
> > new_crtc_state->update_m_n = false;
> >
> > + if (intel_crtc_needs_modeset(new_crtc_state) ||
> > + (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> > + old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
> > + new_crtc_state->update_lrr = false;
> > +
> > if (!intel_crtc_needs_modeset(new_crtc_state))
> > new_crtc_state->update_pipe = true;
> > }
> > @@ -6262,6 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > new_crtc_state->update_m_n = false;
> > + new_crtc_state->update_lrr = false;
> > }
> > }
> >
> > @@ -6275,6 +6319,7 @@ int intel_atomic_check(struct drm_device *dev,
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > new_crtc_state->update_m_n = false;
> > + new_crtc_state->update_lrr = false;
> > }
> > }
> >
> > @@ -6283,6 +6328,7 @@ int intel_atomic_check(struct drm_device *dev,
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > new_crtc_state->update_m_n = false;
> > + new_crtc_state->update_lrr = false;
> > }
> > }
> > }
> > @@ -6464,6 +6510,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> > if (new_crtc_state->update_m_n)
> > intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
> > &new_crtc_state->dp_m_n);
> > +
> > + if (new_crtc_state->update_lrr)
> > + intel_set_transcoder_timings_lrr(new_crtc_state);
> > }
> >
> > static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> > @@ -6600,7 +6649,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > *
> > * FIXME Should be synchronized with the start of vblank somehow...
> > */
> > - if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
> > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > + new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> > intel_crtc_update_active_timings(new_crtc_state,
> > new_crtc_state->vrr.enable);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 8198401aa5be..ee77750af82b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -56,6 +56,7 @@ struct drm_printer;
> > #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> > #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> > #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
> > +#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
> > #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
> > #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
> > #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 2f35560d7e4e..536c642eb562 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1084,6 +1084,7 @@ struct intel_crtc_state {
> > unsigned fb_bits; /* framebuffers to flip */
> > bool update_pipe; /* can a fast modeset be performed? */
> > bool update_m_n; /* update M/N seamlessly during fastset? */
> > + bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
> > bool disable_cxsr;
> > bool update_wm_pre, update_wm_post; /* watermarks are updated */
> > bool fifo_changed; /* FIFO split is changed */
> > @@ -1383,7 +1384,7 @@ struct intel_crtc_state {
> >
> > /* Variable Refresh Rate state */
> > struct {
> > - bool enable;
> > + bool enable, in_range;
> > u8 pipeline_full;
> > u16 flipline, vmin, vmax, guardband;
> > } vrr;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 12731ad725a8..5d905f932cb4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -120,9 +120,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> > if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> > return;
> >
> > - if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
> > + crtc_state->vrr.in_range =
> > + intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
> > + if (!crtc_state->vrr.in_range)
> > return;
> >
> > + if (HAS_LRR(i915))
> > + crtc_state->update_lrr = true;
> > +
> > vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> > adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
> > vmax = adjusted_mode->crtc_clock * 1000 /
> > --
> > 2.41.0
> >
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+
2023-09-20 18:47 ` Manasi Navare
@ 2023-09-20 19:40 ` Ville Syrjälä
2023-09-20 20:40 ` Manasi Navare
0 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjälä @ 2023-09-20 19:40 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Sep 20, 2023 at 11:47:05AM -0700, Manasi Navare wrote:
> Hi Ville,
>
> Quick question here on the use case and the trigger for the LRR case
> which is within VRR range.
> Could this perhaps be used if we had a virtual mode say 40Hz that now
> falls in the VRR range (30 -120Hz) that is
> exposed through the connector mode list and then if we do a modest to
> 40Hz that would make update_lrr = true within VRR and
> hand adjust the vtotal to that exact value?
> I am looking at adding this virtual mode to DRM soon, wondering if
> this would be how the kernel would actual set the timings for it.
Userspace can supply any mode it wants. So just take whatever higher
refresh rate mode you have and increase vtotal until you reach
the desired lower vrefresh rate and feed that to the kernel.
>
> Regards
> Manasi
>
> On Mon, Sep 18, 2023 at 4:16 PM Manasi Navare <navaremanasi@chromium.org> wrote:
> >
> > Thanks Ville for the respin, the changes look good now.
> >
> > Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
> >
> > Manasi
> >
> >
> > On Fri, Sep 15, 2023 at 3:38 AM Ville Syrjala
> > <ville.syrjala@linux.intel.com> wrote:
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Implement low refresh rate (LRR) where we change the vblank
> > > length by hand as requested, but otherwise keep the timing
> > > generator running in non-VRR mode (ie. fixed refresh rate).
> > >
> > > The panel itself must support VRR for this to work, and
> > > only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
> > > we need to make the switch properly. The double buffer
> > > latching happens at the start of transcoders undelayed
> > > vblank. The other thing that we change is
> > > TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
> > > that in DP mode. But I decided to keep writing it anyway
> > > just to avoid more special cases in readout/state check.
> > >
> > > v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
> > > the hardware
> > > v3: Reconcile with VRR fastset
> > > Adjust update_lrr flag behaviour
> > > Make sure timings stay within VRR range
> > > v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi)
> > > Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi)
> > >
> > > TODO: Hook LRR into the automatic DRRS downclocking stuff?
> > >
> > > Cc: Manasi Navare <navaremanasi@chromium.org>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > > drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
> > > drivers/gpu/drm/i915/display/intel_display.c | 60 +++++++++++++++++--
> > > .../drm/i915/display/intel_display_device.h | 1 +
> > > .../drm/i915/display/intel_display_types.h | 3 +-
> > > drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
> > > 6 files changed, 70 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > index aaddd8c0cfa0..5d18145da279 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > @@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> > >
> > > crtc_state->update_pipe = false;
> > > crtc_state->update_m_n = false;
> > > + crtc_state->update_lrr = false;
> > > crtc_state->disable_lp_wm = false;
> > > crtc_state->disable_cxsr = false;
> > > crtc_state->update_wm_pre = false;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > index a39e31c1ca85..22e85fe7e8aa 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > @@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > > if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> > > /* timing changes should happen with VRR disabled */
> > > drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
> > > - new_crtc_state->update_m_n);
> > > + new_crtc_state->update_m_n || new_crtc_state->update_lrr);
> > >
> > > if (intel_vrr_is_push_sent(crtc_state))
> > > *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> > > @@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > > *max = *vblank_start - 1;
> > >
> > > /*
> > > - * M/N is double buffered on the transcoder's undelayed vblank,
> > > - * so with seamless M/N we must evade both vblanks.
> > > + * M/N and TRANS_VTOTAL are double buffered on the transcoder's
> > > + * undelayed vblank, so with seamless M/N and LRR we must evade
> > > + * both vblanks.
> > > */
> > > - if (new_crtc_state->update_m_n)
> > > + if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> > > *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index f0bb5c70ebfc..988558ccf794 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> > > {
> > > return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > > (new_crtc_state->vrr.enable &&
> > > - (new_crtc_state->update_m_n ||
> > > + (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
> > > vrr_params_changed(old_crtc_state, new_crtc_state)));
> > > }
> > >
> > > @@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> > > {
> > > return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > > (old_crtc_state->vrr.enable &&
> > > - (new_crtc_state->update_m_n ||
> > > + (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
> > > vrr_params_changed(old_crtc_state, new_crtc_state)));
> > > }
> > >
> > > @@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> > > VTOTAL(crtc_vtotal - 1));
> > > }
> > >
> > > +static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> > > + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > > +
> > > + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > > + crtc_vtotal = adjusted_mode->crtc_vtotal;
> > > + crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> > > + crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > > +
> > > + drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
> > > +
> > > + /*
> > > + * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
> > > + * But let's write it anyway to keep the state checker happy.
> > > + */
> > > + intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> > > + VBLANK_START(crtc_vblank_start - 1) |
> > > + VBLANK_END(crtc_vblank_end - 1));
> > > + /*
> > > + * The double buffer latch point for TRANS_VTOTAL
> > > + * is the transcoder's undelayed vblank.
> > > + */
> > > + intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> > > + VACTIVE(crtc_vdisplay - 1) |
> > > + VTOTAL(crtc_vtotal - 1));
> > > +}
> > > +
> > > static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> > > {
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > @@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> > > PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> > > PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> > > - PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> > > PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> > > - PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> > > PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> > > PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> > > + if (!fastset || !pipe_config->update_lrr) { \
> > > + PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> > > + PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> > > + } \
> > > } while (0)
> > >
> > > #define PIPE_CONF_CHECK_RECT(name) do { \
> > > @@ -5420,6 +5453,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > > crtc_state->uapi.mode_changed = true;
> > > crtc_state->update_pipe = false;
> > > crtc_state->update_m_n = false;
> > > + crtc_state->update_lrr = false;
> > >
> > > ret = drm_atomic_add_affected_connectors(&state->base,
> > > &crtc->base);
> > > @@ -5537,6 +5571,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > > {
> > > struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
> > >
> > > + /* only allow LRR when the timings stay within the VRR range */
> > > + if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
> > > + new_crtc_state->update_lrr = false;
> > > +
> > > if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> > > drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
> > > else
> > > @@ -5547,6 +5585,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > > &new_crtc_state->dp_m_n))
> > > new_crtc_state->update_m_n = false;
> > >
> > > + if (intel_crtc_needs_modeset(new_crtc_state) ||
> > > + (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> > > + old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
> > > + new_crtc_state->update_lrr = false;
> > > +
> > > if (!intel_crtc_needs_modeset(new_crtc_state))
> > > new_crtc_state->update_pipe = true;
> > > }
> > > @@ -6262,6 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
> > > new_crtc_state->uapi.mode_changed = true;
> > > new_crtc_state->update_pipe = false;
> > > new_crtc_state->update_m_n = false;
> > > + new_crtc_state->update_lrr = false;
> > > }
> > > }
> > >
> > > @@ -6275,6 +6319,7 @@ int intel_atomic_check(struct drm_device *dev,
> > > new_crtc_state->uapi.mode_changed = true;
> > > new_crtc_state->update_pipe = false;
> > > new_crtc_state->update_m_n = false;
> > > + new_crtc_state->update_lrr = false;
> > > }
> > > }
> > >
> > > @@ -6283,6 +6328,7 @@ int intel_atomic_check(struct drm_device *dev,
> > > new_crtc_state->uapi.mode_changed = true;
> > > new_crtc_state->update_pipe = false;
> > > new_crtc_state->update_m_n = false;
> > > + new_crtc_state->update_lrr = false;
> > > }
> > > }
> > > }
> > > @@ -6464,6 +6510,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> > > if (new_crtc_state->update_m_n)
> > > intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
> > > &new_crtc_state->dp_m_n);
> > > +
> > > + if (new_crtc_state->update_lrr)
> > > + intel_set_transcoder_timings_lrr(new_crtc_state);
> > > }
> > >
> > > static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> > > @@ -6600,7 +6649,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > > *
> > > * FIXME Should be synchronized with the start of vblank somehow...
> > > */
> > > - if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
> > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > + new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> > > intel_crtc_update_active_timings(new_crtc_state,
> > > new_crtc_state->vrr.enable);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> > > index 8198401aa5be..ee77750af82b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > > @@ -56,6 +56,7 @@ struct drm_printer;
> > > #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> > > #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> > > #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
> > > +#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
> > > #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
> > > #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
> > > #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 2f35560d7e4e..536c642eb562 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1084,6 +1084,7 @@ struct intel_crtc_state {
> > > unsigned fb_bits; /* framebuffers to flip */
> > > bool update_pipe; /* can a fast modeset be performed? */
> > > bool update_m_n; /* update M/N seamlessly during fastset? */
> > > + bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
> > > bool disable_cxsr;
> > > bool update_wm_pre, update_wm_post; /* watermarks are updated */
> > > bool fifo_changed; /* FIFO split is changed */
> > > @@ -1383,7 +1384,7 @@ struct intel_crtc_state {
> > >
> > > /* Variable Refresh Rate state */
> > > struct {
> > > - bool enable;
> > > + bool enable, in_range;
> > > u8 pipeline_full;
> > > u16 flipline, vmin, vmax, guardband;
> > > } vrr;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > > index 12731ad725a8..5d905f932cb4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > > @@ -120,9 +120,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> > > if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> > > return;
> > >
> > > - if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
> > > + crtc_state->vrr.in_range =
> > > + intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
> > > + if (!crtc_state->vrr.in_range)
> > > return;
> > >
> > > + if (HAS_LRR(i915))
> > > + crtc_state->update_lrr = true;
> > > +
> > > vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> > > adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
> > > vmax = adjusted_mode->crtc_clock * 1000 /
> > > --
> > > 2.41.0
> > >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+
2023-09-20 19:40 ` Ville Syrjälä
@ 2023-09-20 20:40 ` Manasi Navare
0 siblings, 0 replies; 52+ messages in thread
From: Manasi Navare @ 2023-09-20 20:40 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Sep 20, 2023 at 12:40 PM Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
>
> On Wed, Sep 20, 2023 at 11:47:05AM -0700, Manasi Navare wrote:
> > Hi Ville,
> >
> > Quick question here on the use case and the trigger for the LRR case
> > which is within VRR range.
> > Could this perhaps be used if we had a virtual mode say 40Hz that now
> > falls in the VRR range (30 -120Hz) that is
> > exposed through the connector mode list and then if we do a modest to
> > 40Hz that would make update_lrr = true within VRR and
> > hand adjust the vtotal to that exact value?
> > I am looking at adding this virtual mode to DRM soon, wondering if
> > this would be how the kernel would actual set the timings for it.
>
> Userspace can supply any mode it wants. So just take whatever higher
> refresh rate mode you have and increase vtotal until you reach
> the desired lower vrefresh rate and feed that to the kernel.
Okay perfect that makes sense.
So effectively if i create specific modes lower than the highest
refresh rate, then
userspace can request a modeset to any of the lower refresh rate virtual mode
and the kernel would stretch out the vtotal manually corresponding to
the vtotal of
that virtual mode timing and modeset to that seamlessly in a fastset fashion.
Is this correct?
Regards
Manasi
>
> >
> > Regards
> > Manasi
> >
> > On Mon, Sep 18, 2023 at 4:16 PM Manasi Navare <navaremanasi@chromium.org> wrote:
> > >
> > > Thanks Ville for the respin, the changes look good now.
> > >
> > > Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
> > >
> > > Manasi
> > >
> > >
> > > On Fri, Sep 15, 2023 at 3:38 AM Ville Syrjala
> > > <ville.syrjala@linux.intel.com> wrote:
> > > >
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Implement low refresh rate (LRR) where we change the vblank
> > > > length by hand as requested, but otherwise keep the timing
> > > > generator running in non-VRR mode (ie. fixed refresh rate).
> > > >
> > > > The panel itself must support VRR for this to work, and
> > > > only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
> > > > we need to make the switch properly. The double buffer
> > > > latching happens at the start of transcoders undelayed
> > > > vblank. The other thing that we change is
> > > > TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
> > > > that in DP mode. But I decided to keep writing it anyway
> > > > just to avoid more special cases in readout/state check.
> > > >
> > > > v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
> > > > the hardware
> > > > v3: Reconcile with VRR fastset
> > > > Adjust update_lrr flag behaviour
> > > > Make sure timings stay within VRR range
> > > > v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi)
> > > > Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi)
> > > >
> > > > TODO: Hook LRR into the automatic DRRS downclocking stuff?
> > > >
> > > > Cc: Manasi Navare <navaremanasi@chromium.org>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > > > drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
> > > > drivers/gpu/drm/i915/display/intel_display.c | 60 +++++++++++++++++--
> > > > .../drm/i915/display/intel_display_device.h | 1 +
> > > > .../drm/i915/display/intel_display_types.h | 3 +-
> > > > drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
> > > > 6 files changed, 70 insertions(+), 11 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > index aaddd8c0cfa0..5d18145da279 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > @@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> > > >
> > > > crtc_state->update_pipe = false;
> > > > crtc_state->update_m_n = false;
> > > > + crtc_state->update_lrr = false;
> > > > crtc_state->disable_lp_wm = false;
> > > > crtc_state->disable_cxsr = false;
> > > > crtc_state->update_wm_pre = false;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > index a39e31c1ca85..22e85fe7e8aa 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > @@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > > > if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> > > > /* timing changes should happen with VRR disabled */
> > > > drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
> > > > - new_crtc_state->update_m_n);
> > > > + new_crtc_state->update_m_n || new_crtc_state->update_lrr);
> > > >
> > > > if (intel_vrr_is_push_sent(crtc_state))
> > > > *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> > > > @@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > > > *max = *vblank_start - 1;
> > > >
> > > > /*
> > > > - * M/N is double buffered on the transcoder's undelayed vblank,
> > > > - * so with seamless M/N we must evade both vblanks.
> > > > + * M/N and TRANS_VTOTAL are double buffered on the transcoder's
> > > > + * undelayed vblank, so with seamless M/N and LRR we must evade
> > > > + * both vblanks.
> > > > */
> > > > - if (new_crtc_state->update_m_n)
> > > > + if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> > > > *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> > > > }
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index f0bb5c70ebfc..988558ccf794 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> > > > {
> > > > return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > > > (new_crtc_state->vrr.enable &&
> > > > - (new_crtc_state->update_m_n ||
> > > > + (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
> > > > vrr_params_changed(old_crtc_state, new_crtc_state)));
> > > > }
> > > >
> > > > @@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> > > > {
> > > > return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> > > > (old_crtc_state->vrr.enable &&
> > > > - (new_crtc_state->update_m_n ||
> > > > + (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
> > > > vrr_params_changed(old_crtc_state, new_crtc_state)));
> > > > }
> > > >
> > > > @@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> > > > VTOTAL(crtc_vtotal - 1));
> > > > }
> > > >
> > > > +static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > > + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> > > > + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > > > +
> > > > + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > > > + crtc_vtotal = adjusted_mode->crtc_vtotal;
> > > > + crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> > > > + crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > > > +
> > > > + drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
> > > > +
> > > > + /*
> > > > + * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
> > > > + * But let's write it anyway to keep the state checker happy.
> > > > + */
> > > > + intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> > > > + VBLANK_START(crtc_vblank_start - 1) |
> > > > + VBLANK_END(crtc_vblank_end - 1));
> > > > + /*
> > > > + * The double buffer latch point for TRANS_VTOTAL
> > > > + * is the transcoder's undelayed vblank.
> > > > + */
> > > > + intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> > > > + VACTIVE(crtc_vdisplay - 1) |
> > > > + VTOTAL(crtc_vtotal - 1));
> > > > +}
> > > > +
> > > > static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> > > > {
> > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > @@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > > PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> > > > PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> > > > PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> > > > - PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> > > > PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> > > > - PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> > > > PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> > > > PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> > > > + if (!fastset || !pipe_config->update_lrr) { \
> > > > + PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> > > > + PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> > > > + } \
> > > > } while (0)
> > > >
> > > > #define PIPE_CONF_CHECK_RECT(name) do { \
> > > > @@ -5420,6 +5453,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > > > crtc_state->uapi.mode_changed = true;
> > > > crtc_state->update_pipe = false;
> > > > crtc_state->update_m_n = false;
> > > > + crtc_state->update_lrr = false;
> > > >
> > > > ret = drm_atomic_add_affected_connectors(&state->base,
> > > > &crtc->base);
> > > > @@ -5537,6 +5571,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > > > {
> > > > struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
> > > >
> > > > + /* only allow LRR when the timings stay within the VRR range */
> > > > + if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
> > > > + new_crtc_state->update_lrr = false;
> > > > +
> > > > if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> > > > drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
> > > > else
> > > > @@ -5547,6 +5585,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > > > &new_crtc_state->dp_m_n))
> > > > new_crtc_state->update_m_n = false;
> > > >
> > > > + if (intel_crtc_needs_modeset(new_crtc_state) ||
> > > > + (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> > > > + old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
> > > > + new_crtc_state->update_lrr = false;
> > > > +
> > > > if (!intel_crtc_needs_modeset(new_crtc_state))
> > > > new_crtc_state->update_pipe = true;
> > > > }
> > > > @@ -6262,6 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
> > > > new_crtc_state->uapi.mode_changed = true;
> > > > new_crtc_state->update_pipe = false;
> > > > new_crtc_state->update_m_n = false;
> > > > + new_crtc_state->update_lrr = false;
> > > > }
> > > > }
> > > >
> > > > @@ -6275,6 +6319,7 @@ int intel_atomic_check(struct drm_device *dev,
> > > > new_crtc_state->uapi.mode_changed = true;
> > > > new_crtc_state->update_pipe = false;
> > > > new_crtc_state->update_m_n = false;
> > > > + new_crtc_state->update_lrr = false;
> > > > }
> > > > }
> > > >
> > > > @@ -6283,6 +6328,7 @@ int intel_atomic_check(struct drm_device *dev,
> > > > new_crtc_state->uapi.mode_changed = true;
> > > > new_crtc_state->update_pipe = false;
> > > > new_crtc_state->update_m_n = false;
> > > > + new_crtc_state->update_lrr = false;
> > > > }
> > > > }
> > > > }
> > > > @@ -6464,6 +6510,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> > > > if (new_crtc_state->update_m_n)
> > > > intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
> > > > &new_crtc_state->dp_m_n);
> > > > +
> > > > + if (new_crtc_state->update_lrr)
> > > > + intel_set_transcoder_timings_lrr(new_crtc_state);
> > > > }
> > > >
> > > > static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> > > > @@ -6600,7 +6649,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > > > *
> > > > * FIXME Should be synchronized with the start of vblank somehow...
> > > > */
> > > > - if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
> > > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > + new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> > > > intel_crtc_update_active_timings(new_crtc_state,
> > > > new_crtc_state->vrr.enable);
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> > > > index 8198401aa5be..ee77750af82b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > > > @@ -56,6 +56,7 @@ struct drm_printer;
> > > > #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> > > > #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> > > > #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
> > > > +#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
> > > > #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
> > > > #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
> > > > #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 2f35560d7e4e..536c642eb562 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1084,6 +1084,7 @@ struct intel_crtc_state {
> > > > unsigned fb_bits; /* framebuffers to flip */
> > > > bool update_pipe; /* can a fast modeset be performed? */
> > > > bool update_m_n; /* update M/N seamlessly during fastset? */
> > > > + bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
> > > > bool disable_cxsr;
> > > > bool update_wm_pre, update_wm_post; /* watermarks are updated */
> > > > bool fifo_changed; /* FIFO split is changed */
> > > > @@ -1383,7 +1384,7 @@ struct intel_crtc_state {
> > > >
> > > > /* Variable Refresh Rate state */
> > > > struct {
> > > > - bool enable;
> > > > + bool enable, in_range;
> > > > u8 pipeline_full;
> > > > u16 flipline, vmin, vmax, guardband;
> > > > } vrr;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > > > index 12731ad725a8..5d905f932cb4 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > > > @@ -120,9 +120,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> > > > if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> > > > return;
> > > >
> > > > - if (!intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)))
> > > > + crtc_state->vrr.in_range =
> > > > + intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
> > > > + if (!crtc_state->vrr.in_range)
> > > > return;
> > > >
> > > > + if (HAS_LRR(i915))
> > > > + crtc_state->update_lrr = true;
> > > > +
> > > > vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> > > > adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
> > > > vmax = adjusted_mode->crtc_clock * 1000 /
> > > > --
> > > > 2.41.0
> > > >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (11 preceding siblings ...)
2023-09-01 13:04 ` [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+ Ville Syrjala
@ 2023-09-01 16:00 ` Patchwork
2023-09-01 16:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (9 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-01 16:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff
URL : https://patchwork.freedesktop.org/series/123171/
State : warning
== Summary ==
Error: dim checkpatch failed
ceb5c675ed7d drm/i915: Move psr unlock out from the pipe update critical section
bcfae40b96e1 drm/i915: Change intel_pipe_update_{start, end}() calling convention
3a38a23eca3d drm/i915: Extract intel_crtc_vblank_evade_scanlines()
81dac61c36e3 drm/i915: Enable VRR later during fastsets
00a0d797849e drm/i915: Adjust seamless_m_n flag behaviour
a2b041a223d7 drm/i915: Optimize out redundant M/N updates
7b06d470ac13 drm/i915: Relocate is_in_vrr_range()
39518ca01e6b drm/i915: Validate that the timings are within the VRR range
15ff83c1a9a6 drm/i915: Disable VRR during seamless M/N changes
f083c4c91c2d drm/i915: Update VRR parameters in fastset
d141d9d2ed22 drm/i915: Assert that VRR is off during vblank evasion if necessary
2254c65953d4 drm/i915: Implement transcoder LRR for TGL+
-:173: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#173: FILE: drivers/gpu/drm/i915/display/intel_display.c:5589:
+ (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
-:174: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#174: FILE: drivers/gpu/drm/i915/display/intel_display.c:5590:
+ old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
total: 0 errors, 2 warnings, 0 checks, 208 lines checked
^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR, LRR, and M/N stuff
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (12 preceding siblings ...)
2023-09-01 16:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff Patchwork
@ 2023-09-01 16:00 ` Patchwork
2023-09-01 16:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (8 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-01 16:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff
URL : https://patchwork.freedesktop.org/series/123171/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: VRR, LRR, and M/N stuff
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (13 preceding siblings ...)
2023-09-01 16:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-09-01 16:16 ` Patchwork
2023-09-01 18:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev2) Patchwork
` (7 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-01 16:16 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 16274 bytes --]
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff
URL : https://patchwork.freedesktop.org/series/123171/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123171v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_123171v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_123171v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/index.html
Participating hosts (30 -> 39)
------------------------------
Additional (11): fi-kbl-7567u fi-bsw-n3050 fi-cfl-8700k fi-ilk-650 fi-apl-guc fi-kbl-guc fi-hsw-4770 fi-kbl-x1275 fi-cfl-8109u fi-blb-e6850 bat-mtlp-6
Missing (2): fi-kbl-soraka fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_123171v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- bat-mtlp-8: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/bat-mtlp-8/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-8/igt@i915_module_load@load.html
Known issues
------------
Here are the changes found in Patchwork_123171v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#7456])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html
* igt@debugfs_test@read_all_entries:
- fi-kbl-7567u: NOTRUN -> [ABORT][4] ([i915#8913])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-7567u/igt@debugfs_test@read_all_entries.html
* igt@fbdev@info:
- fi-kbl-x1275: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1849])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-x1275/igt@fbdev@info.html
- fi-kbl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1849])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-guc/igt@fbdev@info.html
- bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#1849] / [i915#2582])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@fbdev@info.html
* igt@fbdev@write:
- bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#2582]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@fbdev@write.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
- fi-kbl-x1275: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-x1275/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-apl-guc/igt@gem_lmem_swapping@basic.html
- fi-cfl-8700k: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-cfl-8700k/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][14] ([fdo#109271]) +18 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4613]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
- fi-kbl-x1275: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-x1275/igt@gem_lmem_swapping@verify-random.html
- fi-cfl-8109u: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
- fi-kbl-guc: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +3 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-guc/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#4083])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@gem_mmap@basic.html
* igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#4077]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#4079]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-mtlp-6: NOTRUN -> [SKIP][22] ([i915#3546])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][23] ([fdo#109271]) +21 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-ilk-650/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-blb-e6850: NOTRUN -> [SKIP][24] ([fdo#109271]) +30 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-blb-e6850/igt@i915_pm_rpm@module-reload.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-6: NOTRUN -> [SKIP][25] ([i915#6621])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-6: NOTRUN -> [SKIP][26] ([i915#6645])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][27] ([i915#4212]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770: NOTRUN -> [SKIP][28] ([fdo#109271]) +13 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-6: NOTRUN -> [SKIP][29] ([i915#5190])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cfl-8109u: NOTRUN -> [SKIP][30] ([fdo#109271]) +10 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-cfl-8109u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][31] ([i915#1845]) +11 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-guc: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#1845]) +8 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-guc/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-mtlp-6: NOTRUN -> [SKIP][33] ([i915#3637]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-apl-guc: NOTRUN -> [SKIP][34] ([fdo#109271]) +15 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-apl-guc/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cfl-8700k: NOTRUN -> [SKIP][35] ([fdo#109271]) +10 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-cfl-8700k/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-6: NOTRUN -> [SKIP][36] ([fdo#109285])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-6: NOTRUN -> [SKIP][37] ([i915#5274])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][38] ([i915#4342])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][39] ([i915#1845]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc:
- fi-kbl-x1275: NOTRUN -> [SKIP][40] ([fdo#109271]) +35 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][41] -> [ABORT][42] ([i915#8442] / [i915#8668])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-guc: NOTRUN -> [SKIP][43] ([fdo#109271]) +25 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-kbl-guc/igt@kms_pipe_crc_basic@suspend-read-crc.html
- bat-mtlp-6: NOTRUN -> [SKIP][44] ([i915#1845] / [i915#4078]) +4 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770: NOTRUN -> [DMESG-WARN][45] ([i915#8841]) +6 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1.html
* igt@kms_psr@cursor_plane_move:
- bat-mtlp-6: NOTRUN -> [SKIP][46] ([i915#1072]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#1072]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-6: NOTRUN -> [SKIP][48] ([i915#3555] / [i915#8809])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-mtlp-6: NOTRUN -> [SKIP][49] ([i915#1845] / [i915#3708])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-6: NOTRUN -> [SKIP][50] ([i915#3708] / [i915#4077]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-mtlp-6: NOTRUN -> [SKIP][51] ([i915#3708]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/bat-mtlp-6/igt@prime_vgem@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8913]: https://gitlab.freedesktop.org/drm/intel/issues/8913
Build changes
-------------
* Linux: CI_DRM_13588 -> Patchwork_123171v1
CI-20190529: 20190529
CI_DRM_13588: da6378eaa945d44a75141f9d9de5e237edb0e660 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7464: 7464
Patchwork_123171v1: da6378eaa945d44a75141f9d9de5e237edb0e660 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
5c3a8c12dfab drm/i915: Implement transcoder LRR for TGL+
7e50c8eac6b6 drm/i915: Assert that VRR is off during vblank evasion if necessary
0ab6f13b784f drm/i915: Update VRR parameters in fastset
b2c581927d27 drm/i915: Disable VRR during seamless M/N changes
23505e1153ce drm/i915: Validate that the timings are within the VRR range
32d724dafe98 drm/i915: Relocate is_in_vrr_range()
05aacd5640f3 drm/i915: Optimize out redundant M/N updates
85f4a6e75a76 drm/i915: Adjust seamless_m_n flag behaviour
ddd330918006 drm/i915: Enable VRR later during fastsets
46b4a408101a drm/i915: Extract intel_crtc_vblank_evade_scanlines()
c8cbc4bc9a7e drm/i915: Change intel_pipe_update_{start, end}() calling convention
343ff3b0f832 drm/i915: Move psr unlock out from the pipe update critical section
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v1/index.html
[-- Attachment #2: Type: text/html, Size: 20571 bytes --]
^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev2)
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (14 preceding siblings ...)
2023-09-01 16:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-09-01 18:38 ` Patchwork
2023-09-01 18:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-01 18:38 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff (rev2)
URL : https://patchwork.freedesktop.org/series/123171/
State : warning
== Summary ==
Error: dim checkpatch failed
c7fffe8e772b drm/i915: Move psr unlock out from the pipe update critical section
0431a7e05f0c drm/i915: Change intel_pipe_update_{start, end}() calling convention
92d923a61bcb drm/i915: Extract intel_crtc_vblank_evade_scanlines()
00208c178f7e drm/i915: Enable VRR later during fastsets
ba53ce94d6e6 drm/i915: Adjust seamless_m_n flag behaviour
b9e3a8d75a8b drm/i915: Optimize out redundant M/N updates
bb0955c10359 drm/i915: Relocate is_in_vrr_range()
73bdf859c6b4 drm/i915: Validate that the timings are within the VRR range
eb64fd4e8af4 drm/i915: Disable VRR during seamless M/N changes
75ddcb0cebab drm/i915: Update VRR parameters in fastset
40f26b86aaf1 drm/i915: Assert that VRR is off during vblank evasion if necessary
a39a2eb2de5e drm/i915: Implement transcoder LRR for TGL+
-:173: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#173: FILE: drivers/gpu/drm/i915/display/intel_display.c:5589:
+ (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
-:174: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#174: FILE: drivers/gpu/drm/i915/display/intel_display.c:5590:
+ old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
total: 0 errors, 2 warnings, 0 checks, 208 lines checked
^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR, LRR, and M/N stuff (rev2)
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (15 preceding siblings ...)
2023-09-01 18:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev2) Patchwork
@ 2023-09-01 18:38 ` Patchwork
2023-09-01 18:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-01 18:38 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff (rev2)
URL : https://patchwork.freedesktop.org/series/123171/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: VRR, LRR, and M/N stuff (rev2)
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (16 preceding siblings ...)
2023-09-01 18:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-09-01 18:58 ` Patchwork
2023-09-02 4:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-01 18:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 17730 bytes --]
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff (rev2)
URL : https://patchwork.freedesktop.org/series/123171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123171v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/index.html
Participating hosts (30 -> 40)
------------------------------
Additional (11): fi-kbl-7567u fi-bsw-n3050 fi-cfl-8700k fi-ilk-650 fi-apl-guc fi-kbl-guc fi-hsw-4770 fi-kbl-x1275 fi-cfl-8109u fi-blb-e6850 bat-mtlp-6
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_123171v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#7456])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html
* igt@debugfs_test@read_all_entries:
- fi-kbl-7567u: NOTRUN -> [ABORT][2] ([i915#8913])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-7567u/igt@debugfs_test@read_all_entries.html
* igt@fbdev@info:
- fi-kbl-x1275: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1849])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-x1275/igt@fbdev@info.html
- fi-kbl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-guc/igt@fbdev@info.html
- bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#1849] / [i915#2582])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@fbdev@info.html
* igt@fbdev@write:
- bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#2582]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@fbdev@write.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
- fi-kbl-x1275: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-x1275/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-apl-guc/igt@gem_lmem_swapping@basic.html
- fi-cfl-8700k: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-cfl-8700k/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][12] ([fdo#109271]) +18 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#4613]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
- fi-kbl-x1275: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-x1275/igt@gem_lmem_swapping@verify-random.html
- fi-cfl-8109u: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
- fi-kbl-guc: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-guc/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4083])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@gem_mmap@basic.html
* igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#4077]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#4079]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#3546])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][21] ([fdo#109271]) +21 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-ilk-650/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-blb-e6850: NOTRUN -> [SKIP][22] ([fdo#109271]) +30 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-blb-e6850/igt@i915_pm_rpm@module-reload.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-6: NOTRUN -> [SKIP][23] ([i915#6621])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][24] -> [DMESG-FAIL][25] ([i915#5334] / [i915#7872])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@mman:
- bat-rpls-2: [PASS][26] -> [TIMEOUT][27] ([i915#6794] / [i915#7392])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/bat-rpls-2/igt@i915_selftest@live@mman.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-rpls-2/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][28] -> [ABORT][29] ([i915#7982])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/bat-mtlp-8/igt@i915_selftest@live@requests.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-8/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-11: [PASS][30] -> [DMESG-FAIL][31] ([i915#7913])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/bat-dg2-11/igt@i915_selftest@live@workarounds.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-dg2-11/igt@i915_selftest@live@workarounds.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: [PASS][32] -> [WARN][33] ([i915#8747])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-6: NOTRUN -> [SKIP][34] ([i915#6645])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][35] ([i915#4212]) +8 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770: NOTRUN -> [SKIP][36] ([fdo#109271]) +13 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-6: NOTRUN -> [SKIP][37] ([i915#5190])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cfl-8109u: NOTRUN -> [SKIP][38] ([fdo#109271]) +10 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-cfl-8109u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][39] ([i915#1845]) +11 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-guc: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#1845]) +8 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-guc/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-mtlp-6: NOTRUN -> [SKIP][41] ([i915#3637]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-apl-guc: NOTRUN -> [SKIP][42] ([fdo#109271]) +15 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-apl-guc/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cfl-8700k: NOTRUN -> [SKIP][43] ([fdo#109271]) +10 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-cfl-8700k/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-6: NOTRUN -> [SKIP][44] ([fdo#109285])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-6: NOTRUN -> [SKIP][45] ([i915#5274])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][46] ([i915#4342])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][47] ([i915#1845]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc:
- fi-kbl-x1275: NOTRUN -> [SKIP][48] ([fdo#109271]) +35 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-guc: NOTRUN -> [SKIP][49] ([fdo#109271]) +25 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-kbl-guc/igt@kms_pipe_crc_basic@suspend-read-crc.html
- bat-mtlp-6: NOTRUN -> [SKIP][50] ([i915#1845] / [i915#4078]) +4 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770: NOTRUN -> [DMESG-WARN][51] ([i915#8841]) +6 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1.html
* igt@kms_psr@cursor_plane_move:
- bat-mtlp-6: NOTRUN -> [SKIP][52] ([i915#1072]) +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#1072]) +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-6: NOTRUN -> [SKIP][54] ([i915#3555] / [i915#8809])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-mtlp-6: NOTRUN -> [SKIP][55] ([i915#1845] / [i915#3708])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-6: NOTRUN -> [SKIP][56] ([i915#3708] / [i915#4077]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-mtlp-6: NOTRUN -> [SKIP][57] ([i915#3708]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-mtlp-6/igt@prime_vgem@basic-write.html
#### Warnings ####
* igt@kms_psr@primary_page_flip:
- bat-rplp-1: [SKIP][58] ([i915#1072]) -> [ABORT][59] ([i915#8442] / [i915#8668] / [i915#8860])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/bat-rplp-1/igt@kms_psr@primary_page_flip.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/bat-rplp-1/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8860]: https://gitlab.freedesktop.org/drm/intel/issues/8860
[i915#8913]: https://gitlab.freedesktop.org/drm/intel/issues/8913
Build changes
-------------
* Linux: CI_DRM_13588 -> Patchwork_123171v2
CI-20190529: 20190529
CI_DRM_13588: da6378eaa945d44a75141f9d9de5e237edb0e660 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7464: 7464
Patchwork_123171v2: da6378eaa945d44a75141f9d9de5e237edb0e660 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
618abd1aa624 drm/i915: Implement transcoder LRR for TGL+
69a79f9093e4 drm/i915: Assert that VRR is off during vblank evasion if necessary
7f538f53ce42 drm/i915: Update VRR parameters in fastset
7c16c4c2068b drm/i915: Disable VRR during seamless M/N changes
e0078a6d82ff drm/i915: Validate that the timings are within the VRR range
de0a2a1f5499 drm/i915: Relocate is_in_vrr_range()
edb0f293b71d drm/i915: Optimize out redundant M/N updates
f410ec04b6eb drm/i915: Adjust seamless_m_n flag behaviour
f1db3855fbb0 drm/i915: Enable VRR later during fastsets
e46ce6c940f8 drm/i915: Extract intel_crtc_vblank_evade_scanlines()
d0b358304ac3 drm/i915: Change intel_pipe_update_{start, end}() calling convention
d9f254b5adf5 drm/i915: Move psr unlock out from the pipe update critical section
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/index.html
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^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: VRR, LRR, and M/N stuff (rev2)
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (17 preceding siblings ...)
2023-09-01 18:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-09-02 4:49 ` Patchwork
2023-09-15 11:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev3) Patchwork
` (3 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-02 4:49 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 65751 bytes --]
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff (rev2)
URL : https://patchwork.freedesktop.org/series/123171/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13588_full -> Patchwork_123171v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_123171v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_123171v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_123171v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2.html
#### Warnings ####
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-dg2: [FAIL][2] ([fdo#103375]) -> [INCOMPLETE][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg2-5/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-5/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_dirtyfb@dirtyfb-ioctl@drrs-dp-2}:
- shard-dg2: NOTRUN -> [SKIP][4] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-dp-2.html
* {igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-3}:
- shard-dg1: NOTRUN -> [SKIP][5] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-12/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-3.html
New tests
---------
New tests have been introduced between CI_DRM_13588_full and Patchwork_123171v2_full:
### New IGT tests (94) ###
* igt@kms_cursor_crc@cursor-offscreen-128x128@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-128x128@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-128x42@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-128x42@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-256x256@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-256x256@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-256x85@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-256x85@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-64x21@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-64x21@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-64x21@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x42@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x42@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x42@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-256x256@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-256x256@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-256x256@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-64x64@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-64x64@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-64x64@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-128x128@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-128x128@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-128x128@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-128x42@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-128x42@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-128x42@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-256x256@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-256x256@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-256x256@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-256x85@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-256x85@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-256x85@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-64x21@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-64x21@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-64x21@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-64x64@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-64x64@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-64x64@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-128x128@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-128x128@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-128x128@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-128x42@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-128x42@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-256x256@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-256x256@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-256x256@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-256x85@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-256x85@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-256x85@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-64x21@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-64x21@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-64x21@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-64x64@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-64x64@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-64x64@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-128x128@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-128x128@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-128x128@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-128x42@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-128x42@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-256x256@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-256x256@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-256x256@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-256x85@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-256x85@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-64x21@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-64x21@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-64x64@pipe-a-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-64x64@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-sliding-64x64@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@overlay@pipe-a-edp-1-size-128:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@overlay@pipe-a-edp-1-size-256:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@overlay@pipe-a-edp-1-size-64:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@primary@pipe-a-edp-1-size-128:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@primary@pipe-a-edp-1-size-256:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@primary@pipe-a-edp-1-size-64:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@viewport@pipe-a-edp-1-size-128:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@viewport@pipe-a-edp-1-size-256:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_cursor@viewport@pipe-a-edp-1-size-64:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_123171v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#8411])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#8414]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@drm_fdinfo@busy-check-all@bcs0.html
* igt@drm_fdinfo@busy-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#8414]) +9 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@drm_fdinfo@busy-check-all@vecs1.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [PASS][9] -> [FAIL][10] ([i915#7742])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_ctx_persistence@legacy-engines-hostile:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1099])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-snb4/igt@gem_ctx_persistence@legacy-engines-hostile.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][12] ([i915#5882]) +9 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][13] -> [FAIL][14] ([i915#5784])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg1-17/igt@gem_eio@reset-stress.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-19/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#4771])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#4036])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglu: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-tglu-6/igt@gem_exec_fair@basic-flow@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-tglu-9/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none:
- shard-dg1: NOTRUN -> [SKIP][19] ([i915#3539] / [i915#4852])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-none-solo:
- shard-mtlp: NOTRUN -> [SKIP][20] ([i915#4473])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-mtlp-5/igt@gem_exec_fair@basic-none-solo.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][21] ([i915#2842])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-glk1/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [PASS][22] -> [FAIL][23] ([i915#2842])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-apl3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-apl1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#3539] / [i915#4852]) +4 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@gem_exec_flush@basic-wb-pro-default.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-dg2: NOTRUN -> [SKIP][25] ([fdo#109283] / [i915#5107])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@gem_exec_params@rsvd2-dirt.html
- shard-rkl: NOTRUN -> [SKIP][26] ([fdo#109283])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-cpu-gtt:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#3281]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@gem_exec_reloc@basic-cpu-gtt.html
- shard-dg1: NOTRUN -> [SKIP][28] ([i915#3281]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@gem_exec_reloc@basic-cpu-gtt.html
* igt@gem_exec_reloc@basic-wc-gtt-active:
- shard-rkl: NOTRUN -> [SKIP][29] ([i915#3281]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gem_exec_reloc@basic-wc-gtt-active.html
* igt@gem_exec_schedule@preempt-queue:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#4537] / [i915#4812])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_huc_copy@huc-copy:
- shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#2190])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-glk1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#4613]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gem_lmem_swapping@basic.html
* igt@gem_media_fill@media-fill:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#8289])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@gem_media_fill@media-fill.html
* igt@gem_mmap@big-bo:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#4083]) +4 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@gem_mmap@big-bo.html
* igt@gem_mmap_gtt@big-bo:
- shard-dg1: NOTRUN -> [SKIP][35] ([i915#4077])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@gem_mmap_gtt@big-bo.html
* igt@gem_partial_pwrite_pread@write-display:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#3282])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@gem_partial_pwrite_pread@write-display.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#4270]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@gem_pxp@protected-raw-src-copy-not-readible.html
- shard-rkl: NOTRUN -> [SKIP][38] ([i915#4270])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#4270])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_tiled_swapping@non-threaded:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4077]) +5 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#3297]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@gem_userptr_blits@unsync-unmap.html
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#3297])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen3_mixed_blits:
- shard-dg1: NOTRUN -> [SKIP][43] ([fdo#109289])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@gen3_mixed_blits.html
* igt@gen7_exec_parse@basic-offset:
- shard-dg2: NOTRUN -> [SKIP][44] ([fdo#109289]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@gen7_exec_parse@basic-offset.html
- shard-rkl: NOTRUN -> [SKIP][45] ([fdo#109289]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][46] -> [ABORT][47] ([i915#5566])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-apl4/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-param:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#2856]) +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@gen9_exec_parse@bb-start-param.html
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#2527]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_backlight@basic-brightness:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#5354] / [i915#7561])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@i915_pm_backlight@basic-brightness.html
- shard-rkl: NOTRUN -> [SKIP][51] ([i915#7561])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglu: [PASS][52] -> [SKIP][53] ([i915#4281])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-tglu-9/igt@i915_pm_dc@dc9-dpms.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-tglu-5/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg2: [PASS][54] -> [SKIP][55] ([i915#1937])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg2-10/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
- shard-rkl: [PASS][56] -> [SKIP][57] ([i915#1937])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- shard-dg1: [PASS][58] -> [FAIL][59] ([i915#3591])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg2: [PASS][60] -> [SKIP][61] ([i915#1397])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg2-12/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_selftest@live@migrate:
- shard-mtlp: [PASS][62] -> [DMESG-FAIL][63] ([i915#7699])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-mtlp-2/igt@i915_selftest@live@migrate.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-mtlp-4/igt@i915_selftest@live@migrate.html
* igt@i915_suspend@forcewake:
- shard-snb: NOTRUN -> [DMESG-WARN][64] ([i915#8841]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-snb4/igt@i915_suspend@forcewake.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#4212])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-dp-4-4-mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#8709]) +11 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-dp-4-4-mc_ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#8502]) +7 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [FAIL][68] ([i915#8247]) +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-2/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html
* igt@kms_async_flips@crc@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [FAIL][69] ([i915#8247]) +3 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-12/igt@kms_async_flips@crc@pipe-b-hdmi-a-3.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#4538] / [i915#5286])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-rkl: NOTRUN -> [SKIP][71] ([i915#5286])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][72] ([fdo#111614])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-mtlp: [PASS][73] -> [FAIL][74] ([i915#3743])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#5190]) +5 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#4538] / [i915#5190]) +3 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-rkl: NOTRUN -> [SKIP][77] ([fdo#110723]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#3734] / [i915#5354] / [i915#6095])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_ccs@pipe-a-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#5354] / [i915#6095]) +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf_tiled_ccs:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#3689] / [i915#5354] / [i915#6095]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-bad-aux-stride-4_tiled_mtl_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#5354]) +24 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@kms_ccs@pipe-c-bad-aux-stride-4_tiled_mtl_mc_ccs.html
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#5354] / [i915#6095]) +5 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_ccs@pipe-c-bad-aux-stride-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#3689] / [i915#3886] / [i915#5354]) +4 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#3886]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-glk9/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#3689] / [i915#5354]) +13 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][87] ([i915#5354]) +6 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_ccs.html
* igt@kms_chamelium_color@ctm-max:
- shard-dg1: NOTRUN -> [SKIP][88] ([fdo#111827])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_color@ctm-negative:
- shard-dg2: NOTRUN -> [SKIP][89] ([fdo#111827]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_chamelium_color@ctm-negative.html
- shard-rkl: NOTRUN -> [SKIP][90] ([fdo#111827])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#7828])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#7828])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#7828]) +4 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@mei_interface:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#7118]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#3555]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_cursor_crc@cursor-onscreen-max-size.html
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#3555])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#3359]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_cursor_crc@cursor-random-512x512.html
- shard-rkl: NOTRUN -> [SKIP][98] ([i915#3359])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-rkl: NOTRUN -> [SKIP][99] ([fdo#111825]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-dg2: NOTRUN -> [SKIP][100] ([fdo#109274] / [i915#5354]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][101] -> [FAIL][102] ([i915#2346]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#9227])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#3555] / [i915#3840])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-snb: NOTRUN -> [SKIP][105] ([fdo#109271] / [fdo#111767])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-snb4/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-dg2: NOTRUN -> [SKIP][106] ([fdo#109274])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#8381]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a4:
- shard-dg1: [PASS][108] -> [FAIL][109] ([fdo#103375]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg1-16/igt@kms_flip@flip-vs-suspend@c-hdmi-a4.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-14/igt@kms_flip@flip-vs-suspend@c-hdmi-a4.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#2672]) +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#2672])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-dg2: NOTRUN -> [SKIP][112] ([fdo#109285])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_force_connector_basic@force-load-detect.html
- shard-rkl: NOTRUN -> [SKIP][113] ([fdo#109285] / [i915#4098])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#8708]) +4 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][115] ([i915#3458]) +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
- shard-dg1: NOTRUN -> [SKIP][116] ([fdo#111825]) +3 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#3458]) +9 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
- shard-rkl: NOTRUN -> [SKIP][118] ([i915#3023]) +3 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#8708]) +8 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][120] ([fdo#111825] / [i915#1825]) +6 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
- shard-glk: NOTRUN -> [SKIP][121] ([fdo#109271]) +34 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-glk9/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html
* igt@kms_hdr@bpc-switch:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#3555] / [i915#8228]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-10/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@invalid-hdr:
- shard-rkl: NOTRUN -> [SKIP][123] ([i915#3555] / [i915#8228])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-1/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg1: NOTRUN -> [SKIP][124] ([i915#3555] / [i915#8228])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_plane_lowres@tiling-y:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#8821])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][126] ([i915#6953])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-dg1: NOTRUN -> [FAIL][127] ([i915#8292])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-19/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][128] ([i915#5176]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-1/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#5176]) +7 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-dp-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][130] ([i915#5176]) +15 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-19/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][131] ([i915#5235]) +15 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-17/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][132] ([i915#5235]) +5 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][133] ([fdo#109271]) +102 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-snb4/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#5235]) +23 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-10/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#6524] / [i915#6805])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#658])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-dg1: NOTRUN -> [SKIP][137] ([i915#1072]) +1 similar issue
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_dpms:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#1072]) +4 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_psr@psr2_dpms.html
* igt@kms_psr@sprite_mmap_gtt:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#1072]) +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_psr@sprite_mmap_gtt.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#4235] / [i915#5190])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: NOTRUN -> [SKIP][141] ([fdo#111615] / [i915#5289])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#4235])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_selftest@drm_format_helper:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#8661])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_selftest@drm_format_helper.html
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#8661])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_selftest@drm_format_helper.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#4070] / [i915#533] / [i915#6768])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_vrr@flip-suspend:
- shard-dg1: NOTRUN -> [SKIP][146] ([i915#3555])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@kms_vrr@flip-suspend.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2: NOTRUN -> [FAIL][147] ([i915#6806])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@perf_pmu@frequency@gt0.html
- shard-dg1: NOTRUN -> [FAIL][148] ([i915#6806])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@perf_pmu@frequency@gt0.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#8516])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@perf_pmu@rc6-all-gts.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#2575]) +6 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@v3d/v3d_submit_cl@simple-flush-cache.html
- shard-rkl: NOTRUN -> [SKIP][151] ([fdo#109315]) +1 similar issue
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@v3d/v3d_submit_csd@bad-multisync-extension:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#2575]) +1 similar issue
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@v3d/v3d_submit_csd@bad-multisync-extension.html
* igt@v3d/v3d_wait_bo@unused-bo-0ns:
- shard-mtlp: NOTRUN -> [SKIP][153] ([i915#2575])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-mtlp-5/igt@v3d/v3d_wait_bo@unused-bo-0ns.html
* igt@vc4/vc4_mmap@mmap-bad-handle:
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#7711]) +1 similar issue
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@vc4/vc4_mmap@mmap-bad-handle.html
* igt@vc4/vc4_perfmon@create-single-perfmon:
- shard-dg1: NOTRUN -> [SKIP][155] ([i915#7711])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@vc4/vc4_perfmon@create-single-perfmon.html
* igt@vc4/vc4_tiling@get-bad-handle:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#7711]) +4 similar issues
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@vc4/vc4_tiling@get-bad-handle.html
#### Possible fixes ####
* igt@gem_busy@close-race:
- shard-glk: [ABORT][157] ([i915#6016]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-glk8/igt@gem_busy@close-race.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-glk9/igt@gem_busy@close-race.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][159] ([i915#6268]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_freq@sysfs@gt0:
- shard-dg2: [FAIL][161] ([i915#6786]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg2-12/igt@gem_ctx_freq@sysfs@gt0.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@gem_ctx_freq@sysfs@gt0.html
* igt@gem_eio@hibernate:
- shard-dg1: [ABORT][163] ([i915#7975] / [i915#8213]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg1-14/igt@gem_eio@hibernate.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-18/igt@gem_eio@hibernate.html
- shard-dg2: [ABORT][165] ([i915#7975] / [i915#8213]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg2-3/igt@gem_eio@hibernate.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-11/igt@gem_eio@hibernate.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][167] ([i915#2842]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][169] ([i915#2842]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fence@basic-busy-all:
- shard-rkl: [ABORT][171] -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-rkl-6/igt@gem_exec_fence@basic-busy-all.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@gem_exec_fence@basic-busy-all.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [TIMEOUT][173] ([i915#5493]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-snb: [INCOMPLETE][175] ([i915#8295]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctx0.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-snb5/igt@gem_ppgtt@blt-vs-render-ctx0.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-dg1: [SKIP][177] ([i915#1397]) -> [PASS][178] +1 similar issue
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg1-15/igt@i915_pm_rpm@modeset-lpsp.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-19/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [SKIP][179] ([i915#1397]) -> [PASS][180] +1 similar issue
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg2-10/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-1/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
- shard-rkl: [SKIP][181] ([i915#1397]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-2/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][183] ([i915#7790]) -> [PASS][184]
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-snb5/igt@i915_pm_rps@reset.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-snb4/igt@i915_pm_rps@reset.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [FAIL][185] ([i915#5138]) -> [PASS][186] +1 similar issue
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-mtlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-mtlp-8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-mtlp: [FAIL][187] ([i915#3743]) -> [PASS][188]
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-mtlp-7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-mtlp-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][189] ([i915#2346]) -> [PASS][190]
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-dg2: [INCOMPLETE][191] -> [PASS][192]
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg2-5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-12/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@enable-disable@0-rcs0:
- shard-dg2: [FAIL][193] ([i915#8724]) -> [PASS][194]
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg2-11/igt@perf@enable-disable@0-rcs0.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg2-6/igt@perf@enable-disable@0-rcs0.html
#### Warnings ####
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][195] ([i915#8561]) -> [DMESG-FAIL][196] ([i915#1982] / [i915#8561])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-mtlp-5/igt@kms_async_flips@crc@pipe-a-edp-1.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-mtlp-2/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][197] ([i915#4816]) -> [SKIP][198] ([i915#4070] / [i915#4816])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_psr@cursor_plane_move:
- shard-dg1: [SKIP][199] ([i915#1072] / [i915#4078]) -> [SKIP][200] ([i915#1072])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-dg1-16/igt@kms_psr@cursor_plane_move.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-dg1-14/igt@kms_psr@cursor_plane_move.html
* igt@sysfs_preempt_timeout@timeout@vecs0:
- shard-mtlp: [TIMEOUT][201] ([i915#8521]) -> [ABORT][202] ([i915#8521] / [i915#8865])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13588/shard-mtlp-7/igt@sysfs_preempt_timeout@timeout@vecs0.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/shard-mtlp-3/igt@sysfs_preempt_timeout@timeout@vecs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#6016]: https://gitlab.freedesktop.org/drm/intel/issues/6016
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6786]: https://gitlab.freedesktop.org/drm/intel/issues/6786
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6806]: https://gitlab.freedesktop.org/drm/intel/issues/6806
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8724]: https://gitlab.freedesktop.org/drm/intel/issues/8724
[i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
[i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
Build changes
-------------
* Linux: CI_DRM_13588 -> Patchwork_123171v2
CI-20190529: 20190529
CI_DRM_13588: da6378eaa945d44a75141f9d9de5e237edb0e660 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7464: 7464
Patchwork_123171v2: da6378eaa945d44a75141f9d9de5e237edb0e660 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/index.html
[-- Attachment #2: Type: text/html, Size: 79358 bytes --]
^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev3)
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (18 preceding siblings ...)
2023-09-02 4:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-09-15 11:18 ` Patchwork
2023-09-15 11:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-15 11:18 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff (rev3)
URL : https://patchwork.freedesktop.org/series/123171/
State : warning
== Summary ==
Error: dim checkpatch failed
f109dbfb222e drm/i915: Move psr unlock out from the pipe update critical section
b0cd3befc8d8 drm/i915: Change intel_pipe_update_{start, end}() calling convention
ac4a04c6ee67 drm/i915: Extract intel_crtc_vblank_evade_scanlines()
d94b8ec8df75 drm/i915: Enable VRR later during fastsets
3736cd1a5634 drm/i915: Adjust seamless_m_n flag behaviour
bfe2861ee4f5 drm/i915: Optimize out redundant M/N updates
bcbc7331c4dd drm/i915: Relocate is_in_vrr_range()
2327b8d3bceb drm/i915: Validate that the timings are within the VRR range
67b63054531a drm/i915: Disable VRR during seamless M/N changes
65fc33454c03 drm/i915: Update VRR parameters in fastset
0706f6c0bc1d drm/i915: Assert that VRR is off during vblank evasion if necessary
d85bf5ffbe6c drm/i915: Implement transcoder LRR for TGL+
-:175: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#175: FILE: drivers/gpu/drm/i915/display/intel_display.c:5621:
+ (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
-:176: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#176: FILE: drivers/gpu/drm/i915/display/intel_display.c:5622:
+ old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
total: 0 errors, 2 warnings, 0 checks, 201 lines checked
^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR, LRR, and M/N stuff (rev3)
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (19 preceding siblings ...)
2023-09-15 11:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev3) Patchwork
@ 2023-09-15 11:18 ` Patchwork
2023-09-15 11:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-09-20 18:54 ` [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Manasi Navare
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-15 11:18 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff (rev3)
URL : https://patchwork.freedesktop.org/series/123171/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 52+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: VRR, LRR, and M/N stuff (rev3)
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (20 preceding siblings ...)
2023-09-15 11:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-09-15 11:34 ` Patchwork
2023-09-20 18:54 ` [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Manasi Navare
22 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2023-09-15 11:34 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10320 bytes --]
== Series Details ==
Series: drm/i915: VRR, LRR, and M/N stuff (rev3)
URL : https://patchwork.freedesktop.org/series/123171/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13636 -> Patchwork_123171v3
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_123171v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_123171v3, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/index.html
Participating hosts (38 -> 39)
------------------------------
Additional (2): bat-dg2-8 fi-pnv-d510
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_123171v3:
### IGT changes ###
#### Possible regressions ####
* igt@gem_lmem_swapping@random-engines@lmem0:
- bat-dg2-11: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/bat-dg2-11/igt@gem_lmem_swapping@random-engines@lmem0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-11/igt@gem_lmem_swapping@random-engines@lmem0.html
Known issues
------------
Here are the changes found in Patchwork_123171v3 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-hsw-4770: [PASS][3] -> [FAIL][4] ([i915#8293])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/fi-hsw-4770/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/fi-hsw-4770/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap@basic:
- bat-dg2-8: NOTRUN -> [SKIP][5] ([i915#4083])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-8: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg2-8: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#6621])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-dg2-8: NOTRUN -> [SKIP][9] ([i915#6645])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#5190])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#4215] / [i915#5190])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#4212]) +7 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8: NOTRUN -> [SKIP][14] ([fdo#109285])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#5274])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#1845]) +3 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_psr@cursor_plane_move:
- bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#1072]) +3 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510: NOTRUN -> [SKIP][18] ([fdo#109271]) +31 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#3555])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-8: NOTRUN -> [SKIP][20] ([i915#3708])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][21] ([i915#3708] / [i915#4077]) +1 other test skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-dg2-8: NOTRUN -> [SKIP][22] ([i915#3291] / [i915#3708]) +2 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-dg2-8/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- bat-mtlp-8: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/bat-mtlp-8/igt@i915_module_load@reload.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-mtlp-8/igt@i915_module_load@reload.html
* igt@i915_selftest@live@mman:
- bat-rpls-1: [TIMEOUT][25] ([i915#6794] / [i915#7392]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/bat-rpls-1/igt@i915_selftest@live@mman.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-rpls-1/igt@i915_selftest@live@mman.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-1: [WARN][27] ([i915#8747]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13636/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747
Build changes
-------------
* Linux: CI_DRM_13636 -> Patchwork_123171v3
CI-20190529: 20190529
CI_DRM_13636: 371f885605df83e5fd5680580b5bda86a10e7f7c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7489: c31111635650e76263faee031292290b1a393f2a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_123171v3: 371f885605df83e5fd5680580b5bda86a10e7f7c @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7757455b194c drm/i915: Implement transcoder LRR for TGL+
e79a11691ce7 drm/i915: Assert that VRR is off during vblank evasion if necessary
ad27196e84a1 drm/i915: Update VRR parameters in fastset
f175c3e8e7f2 drm/i915: Disable VRR during seamless M/N changes
d3fc9c1f6ac5 drm/i915: Validate that the timings are within the VRR range
8c938ff6aad2 drm/i915: Relocate is_in_vrr_range()
6cbab6eb59fb drm/i915: Optimize out redundant M/N updates
e6780eedcbc9 drm/i915: Adjust seamless_m_n flag behaviour
2dcd450ae00d drm/i915: Enable VRR later during fastsets
a32019f922ba drm/i915: Extract intel_crtc_vblank_evade_scanlines()
04cf2c3be1b0 drm/i915: Change intel_pipe_update_{start, end}() calling convention
31d6bcbcbcca drm/i915: Move psr unlock out from the pipe update critical section
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v3/index.html
[-- Attachment #2: Type: text/html, Size: 11789 bytes --]
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff
2023-09-01 13:04 [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Ville Syrjala
` (21 preceding siblings ...)
2023-09-15 11:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-09-20 18:54 ` Manasi Navare
2023-09-20 20:56 ` Ville Syrjälä
22 siblings, 1 reply; 52+ messages in thread
From: Manasi Navare @ 2023-09-20 18:54 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Hi Ville,
After the comments have been addressed, I have completed reviewing the
patches. Is there anything
else blocking this from getting merged? Could we get this merged if
everything looks good?
Regards
Manasi
On Fri, Sep 1, 2023 at 6:04 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Attempt to make VRR, LRR, and M/N updates coexist nicely,
> allowing fastsets whenever feasible.
>
> Lightly smoke tested on my adl.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
>
> Ville Syrjälä (12):
> drm/i915: Move psr unlock out from the pipe update critical section
> drm/i915: Change intel_pipe_update_{start,end}() calling convention
> drm/i915: Extract intel_crtc_vblank_evade_scanlines()
> drm/i915: Enable VRR later during fastsets
> drm/i915: Adjust seamless_m_n flag behaviour
> drm/i915: Optimize out redundant M/N updates
> drm/i915: Relocate is_in_vrr_range()
> drm/i915: Validate that the timings are within the VRR range
> drm/i915: Disable VRR during seamless M/N changes
> drm/i915: Update VRR parameters in fastset
> drm/i915: Assert that VRR is off during vblank evasion if necessary
> drm/i915: Implement transcoder LRR for TGL+
>
> drivers/gpu/drm/i915/display/intel_atomic.c | 2 +
> drivers/gpu/drm/i915/display/intel_crtc.c | 110 ++++++++------
> drivers/gpu/drm/i915/display/intel_crtc.h | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 135 ++++++++++++++----
> .../drm/i915/display/intel_display_device.h | 1 +
> .../drm/i915/display/intel_display_types.h | 5 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_panel.c | 17 +--
> drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++-
> drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 11 files changed, 212 insertions(+), 86 deletions(-)
>
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff
2023-09-20 18:54 ` [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff Manasi Navare
@ 2023-09-20 20:56 ` Ville Syrjälä
0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2023-09-20 20:56 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Sep 20, 2023 at 11:54:41AM -0700, Manasi Navare wrote:
> Hi Ville,
>
> After the comments have been addressed, I have completed reviewing the
> patches. Is there anything
> else blocking this from getting merged? Could we get this merged if
> everything looks good?
Series pushed to drm-intel-next, Thanks for the reviews everyone.
>
> Regards
> Manasi
>
> On Fri, Sep 1, 2023 at 6:04 AM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Attempt to make VRR, LRR, and M/N updates coexist nicely,
> > allowing fastsets whenever feasible.
> >
> > Lightly smoke tested on my adl.
> >
> > Cc: Manasi Navare <navaremanasi@chromium.org>
> >
> > Ville Syrjälä (12):
> > drm/i915: Move psr unlock out from the pipe update critical section
> > drm/i915: Change intel_pipe_update_{start,end}() calling convention
> > drm/i915: Extract intel_crtc_vblank_evade_scanlines()
> > drm/i915: Enable VRR later during fastsets
> > drm/i915: Adjust seamless_m_n flag behaviour
> > drm/i915: Optimize out redundant M/N updates
> > drm/i915: Relocate is_in_vrr_range()
> > drm/i915: Validate that the timings are within the VRR range
> > drm/i915: Disable VRR during seamless M/N changes
> > drm/i915: Update VRR parameters in fastset
> > drm/i915: Assert that VRR is off during vblank evasion if necessary
> > drm/i915: Implement transcoder LRR for TGL+
> >
> > drivers/gpu/drm/i915/display/intel_atomic.c | 2 +
> > drivers/gpu/drm/i915/display/intel_crtc.c | 110 ++++++++------
> > drivers/gpu/drm/i915/display/intel_crtc.h | 6 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 135 ++++++++++++++----
> > .../drm/i915/display/intel_display_device.h | 1 +
> > .../drm/i915/display/intel_display_types.h | 5 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_panel.c | 17 +--
> > drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++-
> > drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 11 files changed, 212 insertions(+), 86 deletions(-)
> >
> > --
> > 2.41.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 52+ messages in thread