From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Matt Roper <matthew.d.roper@intel.com>
Subject: [Intel-gfx] [PATCH v2 16/27] drm/i915/xe2lpd: Handle port AUX interrupts
Date: Thu, 7 Sep 2023 08:37:46 -0700 [thread overview]
Message-ID: <20230907153757.2249452-17-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20230907153757.2249452-1-lucas.demarchi@intel.com>
From: Gustavo Sousa <gustavo.sousa@intel.com>
Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.
While at it, drop some trailing newlines.
BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 5 ++---
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 62ce55475554..bff4a76310c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(dev_priv) >= 20)
+ return 0;
+ else if (DISPLAY_VER(dev_priv) >= 14)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB;
else if (DISPLAY_VER(dev_priv) >= 13)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 95a7ea94f417..3398cc21bd26 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
u32 pin_mask = 0, long_mask = 0;
+ if (DISPLAY_VER(i915) >= 20)
+ trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
+
for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
u32 val;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f5dd5361263..2f115d339913 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4467,13 +4467,12 @@
#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
-
#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
-
#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
-
+#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
+#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
--
2.40.1
next prev parent reply other threads:[~2023-09-07 15:40 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-07 15:37 [Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES Lucas De Marchi
2023-09-07 16:04 ` Matt Roper
2023-09-07 20:35 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 02/27] drm/i915/lnl: Add display definitions Lucas De Marchi
2023-09-07 16:10 ` Matt Roper
2023-09-08 23:25 ` [Intel-gfx] [Intel-xe] " Lucas De Marchi
2023-09-08 23:37 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 03/27] drm/i915/xe2lpd: FBC is now supported on all pipes Lucas De Marchi
2023-09-08 8:54 ` [Intel-gfx] [Intel-xe] " Govindapillai, Vinod
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 04/27] drm/i915: Re-order if/else ladder in intel_detect_pch() Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH Lucas De Marchi
2023-09-07 17:04 ` Matt Roper
2023-09-07 20:43 ` Lucas De Marchi
2023-09-08 0:57 ` Matt Roper
2023-09-08 4:07 ` Lucas De Marchi
2023-09-08 5:39 ` Ville Syrjälä
2023-09-08 5:51 ` Lucas De Marchi
2023-09-08 5:56 ` Ville Syrjälä
2023-09-08 6:03 ` [Intel-gfx] [Intel-xe] " Ville Syrjälä
2023-09-08 13:13 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 06/27] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 07/27] drm/i915/display: Consolidate saved port bits in intel_digital_port Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 08/27] drm/i915/xe2lpd: Move D2D enable/disable Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA Lucas De Marchi
2023-09-07 17:52 ` Matt Roper
2023-09-08 13:05 ` [Intel-gfx] [Intel-xe] " Gustavo Sousa
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 10/27] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 11/27] drm/i915/xe2lpd: Register DE_RRMR has been removed Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well Lucas De Marchi
2023-09-07 16:53 ` Vodapalli, Ravi Kumar
2023-09-07 16:55 ` Vodapalli, Ravi Kumar
2023-09-07 16:56 ` Vodapalli, Ravi Kumar
2023-09-07 17:57 ` Matt Roper
2023-09-07 19:24 ` Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 13/27] drm/i915/xe2lpd: Add DC state support Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 14/27] drm/i915/display: Remove FBC capability from fused off pipes Lucas De Marchi
2023-09-08 8:55 ` [Intel-gfx] [Intel-xe] " Govindapillai, Vinod
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 15/27] FIXME: drm/i915/xe2lpd: Add support for DP aux channels Lucas De Marchi
2023-09-07 15:37 ` Lucas De Marchi [this message]
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 17/27] drm/i915/xe2lpd: Read pin assignment from IOM Lucas De Marchi
2023-09-08 6:55 ` Kahola, Mika
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 18/27] drm/i915/xe2lpd: Enable odd size and panning for planar yuv Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 19/27] drm/i915/xe2lpd: Add support for HPD Lucas De Marchi
2023-09-07 20:42 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 20/27] drm/i915/xe2lpd: Extend Wa_15010685871 Lucas De Marchi
2023-09-07 20:52 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 21/27] drm/i915/lnl: Add gmbus/ddc support Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 22/27] drm/i915/lnl: Add CDCLK table Lucas De Marchi
2023-09-07 21:52 ` Matt Roper
2023-09-07 22:48 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 23/27] drm/i915/lnl: Start using CDCLK through PLL Lucas De Marchi
2023-09-07 22:13 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 24/27] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf Lucas De Marchi
2023-09-08 22:43 ` Matt Roper
2023-09-11 8:06 ` Lisovskiy, Stanislav
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence Lucas De Marchi
2023-09-07 16:55 ` Vodapalli, Ravi Kumar
2023-09-08 22:17 ` Matt Roper
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 26/27] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane Lucas De Marchi
2023-09-07 15:37 ` [Intel-gfx] [PATCH v2 27/27] drm/i915/xe2lpd: Update mbus on post plane updates Lucas De Marchi
2023-09-07 19:39 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display (rev3) Patchwork
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