[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Mitul Golani]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 82 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 83 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f05b52381a83..d1b202e14e5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 								      DP_DSC_YCbCr420_Native)),
 			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
 								      DP_DSC_YCbCr444)));
+		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1436,6 +1438,83 @@ static const struct file_operations i915_dsc_output_format_fops = {
 	.write = i915_dsc_output_format_write
 };
 
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(to_intel_connector(connector));
+	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_fractional_bpp_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+		(dsc_fractional_bpp_enable) ? "true" : "false");
+	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+					struct file *file)
+{
+	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_fractional_bpp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_fractional_bpp_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1513,6 +1592,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_output_format", 0644, root,
 				    connector, &i915_dsc_output_format_fops);
+
+		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9eb7b8912076..6e76f1274b0c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1797,6 +1797,7 @@ struct intel_dp {
 	/* Display stream compression testing */
 	bool force_dsc_en;
 	int force_dsc_output_format;
+	bool force_dsc_fractional_bpp_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.25.1

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Kandpal, Suraj]

> Subject: [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional
> bpp
> 
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show to
> depict sink's precision.
> Also, new debugfs entry is created to enforce fractional bpp.
> If Force_DSC_Fractional_BPP_en is set then while iterating over output bpp
> with fractional step size we will continue if output_bpp is computed as integer.
> With this approach, we will be able to validate DSC with fractional bpp.
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 82 +++++++++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  2 files changed, 83 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f05b52381a83..d1b202e14e5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file
> *m, void *data)
> 
> DP_DSC_YCbCr420_Native)),
> 
> str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> 
> DP_DSC_YCbCr444)));
> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>  		seq_printf(m, "Force_DSC_Enable: %s\n",
>  			   str_yes_no(intel_dp->force_dsc_en));
>  		if (!intel_dp_is_edp(intel_dp))
> @@ -1436,6 +1438,83 @@ static const struct file_operations
> i915_dsc_output_format_fops = {
>  	.write = i915_dsc_output_format_write
>  };
> 
> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> +{
> +	struct drm_connector *connector = m->private;
> +	struct drm_device *dev = connector->dev;
> +	struct drm_crtc *crtc;
> +	struct intel_dp *intel_dp;
> +	struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> +	int ret;
> +
> +	if (!encoder)
> +		return -ENODEV;
> +
> +	ret = drm_modeset_lock_single_interruptible(&dev-
> >mode_config.connection_mutex);
> +	if (ret)
> +		return ret;
> +
> +	crtc = connector->state->crtc;
> +	if (connector->status != connector_status_connected || !crtc) {
> +		ret = -ENODEV;
> +		goto out;
> +	}
> +
> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
> +
> +out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
> +

The above function should be on a new line and the extra new line can be removed
return and modeset_unlock

With that fixed
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> +	return ret;
> +}
> +
> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
> +					     const char __user *ubuf,
> +					     size_t len, loff_t *offp)
> +{
> +	struct drm_connector *connector =
> +		((struct seq_file *)file->private_data)->private;
> +	struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	bool dsc_fractional_bpp_enable = false;
> +	int ret;
> +
> +	if (len == 0)
> +		return 0;
> +
> +	drm_dbg(&i915->drm,
> +		"Copied %zu bytes from user to force fractional bpp for
> DSC\n", len);
> +
> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
> +	if (ret < 0)
> +		return ret;
> +
> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
> +		(dsc_fractional_bpp_enable) ? "true" : "false");
> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
> +
> +	*offp += len;
> +
> +	return len;
> +}
> +
> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
> +					struct file *file)
> +{
> +	return single_open(file, i915_dsc_fractional_bpp_show,
> +inode->i_private); }
> +
> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
> +	.owner = THIS_MODULE,
> +	.open = i915_dsc_fractional_bpp_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = i915_dsc_fractional_bpp_write };
> +
>  /*
>   * Returns the Current CRTC's bpc.
>   * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
> @@ -1513,6 +1592,9 @@ void intel_connector_debugfs_add(struct
> intel_connector *intel_connector)
> 
>  		debugfs_create_file("i915_dsc_output_format", 0644, root,
>  				    connector, &i915_dsc_output_format_fops);
> +
> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
> +				    connector, &i915_dsc_fractional_bpp_fops);
>  	}
> 
>  	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9eb7b8912076..6e76f1274b0c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1797,6 +1797,7 @@ struct intel_dp {
>  	/* Display stream compression testing */
>  	bool force_dsc_en;
>  	int force_dsc_output_format;
> +	bool force_dsc_fractional_bpp_en;
>  	int force_dsc_bpc;
> 
>  	bool hobl_failed;
> --
> 2.25.1

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Mitul Golani]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.

v2:
Add drm_modeset_unlock to new line(Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 84 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f05b52381a83..776ab96def1f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 								      DP_DSC_YCbCr420_Native)),
 			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
 								      DP_DSC_YCbCr444)));
+		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
 	.write = i915_dsc_output_format_write
 };
 
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(to_intel_connector(connector));
+	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_fractional_bpp_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+		(dsc_fractional_bpp_enable) ? "true" : "false");
+	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+					struct file *file)
+{
+	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_fractional_bpp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_fractional_bpp_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_output_format", 0644, root,
 				    connector, &i915_dsc_output_format_fops);
+
+		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 69bcabec4a29..27b31cb4c7b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1797,6 +1797,7 @@ struct intel_dp {
 	/* Display stream compression testing */
 	bool force_dsc_en;
 	int force_dsc_output_format;
+	bool force_dsc_fractional_bpp_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.25.1

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Mitul Golani]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.

v2:
Add drm_modeset_unlock to new line(Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 84 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f05b52381a83..776ab96def1f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 								      DP_DSC_YCbCr420_Native)),
 			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
 								      DP_DSC_YCbCr444)));
+		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
 	.write = i915_dsc_output_format_write
 };
 
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(to_intel_connector(connector));
+	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_fractional_bpp_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+		(dsc_fractional_bpp_enable) ? "true" : "false");
+	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+					struct file *file)
+{
+	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_fractional_bpp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_fractional_bpp_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_output_format", 0644, root,
 				    connector, &i915_dsc_output_format_fops);
+
+		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 69bcabec4a29..27b31cb4c7b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1797,6 +1797,7 @@ struct intel_dp {
 	/* Display stream compression testing */
 	bool force_dsc_en;
 	int force_dsc_output_format;
+	bool force_dsc_fractional_bpp_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.25.1

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Jani Nikula]

On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
>
> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
> to depict sink's precision.
> Also, new debugfs entry is created to enforce fractional bpp.
> If Force_DSC_Fractional_BPP_en is set then while iterating over
> output bpp with fractional step size we will continue if output_bpp is
> computed as integer. With this approach, we will be able to validate
> DSC with fractional bpp.
>
> v2:
> Add drm_modeset_unlock to new line(Suraj)
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  2 files changed, 84 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f05b52381a83..776ab96def1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>  								      DP_DSC_YCbCr420_Native)),
>  			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>  								      DP_DSC_YCbCr444)));
> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>  		seq_printf(m, "Force_DSC_Enable: %s\n",
>  			   str_yes_no(intel_dp->force_dsc_en));
>  		if (!intel_dp_is_edp(intel_dp))
> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>  	.write = i915_dsc_output_format_write
>  };
>  
> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> +{
> +	struct drm_connector *connector = m->private;
> +	struct drm_device *dev = connector->dev;
> +	struct drm_crtc *crtc;
> +	struct intel_dp *intel_dp;
> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	int ret;
> +
> +	if (!encoder)
> +		return -ENODEV;
> +
> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
> +	if (ret)
> +		return ret;
> +
> +	crtc = connector->state->crtc;
> +	if (connector->status != connector_status_connected || !crtc) {
> +		ret = -ENODEV;
> +		goto out;
> +	}
> +
> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));

Why "Force_DSC_Fractional_BPP_Enable" in the output?

Usually debugfs files, like sysfs files, for stuff like this should be
attributes, one thing per file. Why print a long name for it, if the
name of the debugfs file is the name of the attribute?

And even if you print it for humans, why the underscores?

> +
> +out:
> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
> +
> +	return ret;
> +}
> +
> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
> +					     const char __user *ubuf,
> +					     size_t len, loff_t *offp)
> +{
> +	struct drm_connector *connector =
> +		((struct seq_file *)file->private_data)->private;

I know this is copy-pasted from elsewhere, but really it's nicer to
avoid the cast, and copy-paste from the places that get this right:

	struct seq_file *m = file->private_data;
        struct drm_connector *connector = m->private;

> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	bool dsc_fractional_bpp_enable = false;
> +	int ret;
> +
> +	if (len == 0)
> +		return 0;

kstrtobool_from_user() has this covered.

> +
> +	drm_dbg(&i915->drm,
> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);

That's useless.

> +
> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
> +	if (ret < 0)
> +		return ret;
> +
> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
> +		(dsc_fractional_bpp_enable) ? "true" : "false");

Is this useful?

> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
> +
> +	*offp += len;
> +
> +	return len;
> +}
> +
> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
> +					struct file *file)
> +{
> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
> +}
> +
> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
> +	.owner = THIS_MODULE,
> +	.open = i915_dsc_fractional_bpp_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = i915_dsc_fractional_bpp_write
> +};
> +
>  /*
>   * Returns the Current CRTC's bpc.
>   * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>  
>  		debugfs_create_file("i915_dsc_output_format", 0644, root,
>  				    connector, &i915_dsc_output_format_fops);
> +
> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
> +				    connector, &i915_dsc_fractional_bpp_fops);
>  	}
>  
>  	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 69bcabec4a29..27b31cb4c7b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1797,6 +1797,7 @@ struct intel_dp {
>  	/* Display stream compression testing */
>  	bool force_dsc_en;
>  	int force_dsc_output_format;
> +	bool force_dsc_fractional_bpp_en;
>  	int force_dsc_bpc;
>  
>  	bool hobl_failed;

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Sharma, Swati2]

On 21-Sep-23 1:30 PM, Jani Nikula wrote:
> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
>> to depict sink's precision.
>> Also, new debugfs entry is created to enforce fractional bpp.
>> If Force_DSC_Fractional_BPP_en is set then while iterating over
>> output bpp with fractional step size we will continue if output_bpp is
>> computed as integer. With this approach, we will be able to validate
>> DSC with fractional bpp.
>>
>> v2:
>> Add drm_modeset_unlock to new line(Suraj)
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   2 files changed, 84 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index f05b52381a83..776ab96def1f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>   								      DP_DSC_YCbCr420_Native)),
>>   			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>   								      DP_DSC_YCbCr444)));
>> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
>> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>>   		seq_printf(m, "Force_DSC_Enable: %s\n",
>>   			   str_yes_no(intel_dp->force_dsc_en));
>>   		if (!intel_dp_is_edp(intel_dp))
>> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>>   	.write = i915_dsc_output_format_write
>>   };
>>   
>> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>> +{
>> +	struct drm_connector *connector = m->private;
>> +	struct drm_device *dev = connector->dev;
>> +	struct drm_crtc *crtc;
>> +	struct intel_dp *intel_dp;
>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>> +	int ret;
>> +
>> +	if (!encoder)
>> +		return -ENODEV;
>> +
>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>> +	if (ret)
>> +		return ret;
>> +
>> +	crtc = connector->state->crtc;
>> +	if (connector->status != connector_status_connected || !crtc) {
>> +		ret = -ENODEV;
>> +		goto out;
>> +	}
>> +
>> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
>> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
>> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
> 
> Why "Force_DSC_Fractional_BPP_Enable" in the output?
> 
> Usually debugfs files, like sysfs files, for stuff like this should be
> attributes, one thing per file. Why print a long name for it, if the
> name of the debugfs file is the name of the attribute?
> 
> And even if you print it for humans, why the underscores?

Hi Jani,
Followed same strategy as we are doing for other dsc scenarios like
force_dsc.
Even naming convention followed same as other dsc stuff like 
Force_DSC_Enable, etc.
All DSC related enteries have underscores in its naming convention.

May be i can consolidate other dsc debugfs enteries into
one as a cleanup task later. But it will impact IGT aswell. And i'm not 
sure if we can break compatibility but since IGT (intel as only vendor) 
is the only consumer, may be we change at both places and clean it up.

> 
>> +
>> +out:
>> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>> +
>> +	return ret;
>> +}
>> +
>> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>> +					     const char __user *ubuf,
>> +					     size_t len, loff_t *offp)
>> +{
>> +	struct drm_connector *connector =
>> +		((struct seq_file *)file->private_data)->private;
> 
> I know this is copy-pasted from elsewhere, but really it's nicer to
> avoid the cast, and copy-paste from the places that get this right:
> 
> 	struct seq_file *m = file->private_data;
>          struct drm_connector *connector = m->private;

Done.

> 
>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +	bool dsc_fractional_bpp_enable = false;
>> +	int ret;
>> +
>> +	if (len == 0)
>> +		return 0;
> 
> kstrtobool_from_user() has this covered.

Done.

> 
>> +
>> +	drm_dbg(&i915->drm,
>> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
> 
> That's useless.

Done.

> 
>> +
>> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
>> +		(dsc_fractional_bpp_enable) ? "true" : "false");
> 
> Is this useful?

Yes, to know when fractional bpp is enabled.

> 
>> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>> +
>> +	*offp += len;
>> +
>> +	return len;
>> +}
>> +
>> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
>> +					struct file *file)
>> +{
>> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
>> +}
>> +
>> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
>> +	.owner = THIS_MODULE,
>> +	.open = i915_dsc_fractional_bpp_open,
>> +	.read = seq_read,
>> +	.llseek = seq_lseek,
>> +	.release = single_release,
>> +	.write = i915_dsc_fractional_bpp_write
>> +};
>> +
>>   /*
>>    * Returns the Current CRTC's bpc.
>>    * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>   
>>   		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>   				    connector, &i915_dsc_output_format_fops);
>> +
>> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
>> +				    connector, &i915_dsc_fractional_bpp_fops);
>>   	}
>>   
>>   	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 69bcabec4a29..27b31cb4c7b4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1797,6 +1797,7 @@ struct intel_dp {
>>   	/* Display stream compression testing */
>>   	bool force_dsc_en;
>>   	int force_dsc_output_format;
>> +	bool force_dsc_fractional_bpp_en;
>>   	int force_dsc_bpc;
>>   
>>   	bool hobl_failed;
> 

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Jani Nikula]

On Thu, 21 Sep 2023, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
> On 21-Sep-23 1:30 PM, Jani Nikula wrote:
>> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>>> From: Swati Sharma <swati2.sharma@intel.com>
>>>
>>> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
>>> to depict sink's precision.
>>> Also, new debugfs entry is created to enforce fractional bpp.
>>> If Force_DSC_Fractional_BPP_en is set then while iterating over
>>> output bpp with fractional step size we will continue if output_bpp is
>>> computed as integer. With this approach, we will be able to validate
>>> DSC with fractional bpp.
>>>
>>> v2:
>>> Add drm_modeset_unlock to new line(Suraj)
>>>
>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>> ---
>>>   .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>>   2 files changed, 84 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> index f05b52381a83..776ab96def1f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>>   								      DP_DSC_YCbCr420_Native)),
>>>   			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>>   								      DP_DSC_YCbCr444)));
>>> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
>>> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>>>   		seq_printf(m, "Force_DSC_Enable: %s\n",
>>>   			   str_yes_no(intel_dp->force_dsc_en));
>>>   		if (!intel_dp_is_edp(intel_dp))
>>> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>>>   	.write = i915_dsc_output_format_write
>>>   };
>>>   
>>> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>>> +{
>>> +	struct drm_connector *connector = m->private;
>>> +	struct drm_device *dev = connector->dev;
>>> +	struct drm_crtc *crtc;
>>> +	struct intel_dp *intel_dp;
>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>> +	int ret;
>>> +
>>> +	if (!encoder)
>>> +		return -ENODEV;
>>> +
>>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	crtc = connector->state->crtc;
>>> +	if (connector->status != connector_status_connected || !crtc) {
>>> +		ret = -ENODEV;
>>> +		goto out;
>>> +	}
>>> +
>>> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
>>> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
>>> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>> 
>> Why "Force_DSC_Fractional_BPP_Enable" in the output?
>> 
>> Usually debugfs files, like sysfs files, for stuff like this should be
>> attributes, one thing per file. Why print a long name for it, if the
>> name of the debugfs file is the name of the attribute?
>> 
>> And even if you print it for humans, why the underscores?
>
> Hi Jani,
> Followed same strategy as we are doing for other dsc scenarios like
> force_dsc.
> Even naming convention followed same as other dsc stuff like 
> Force_DSC_Enable, etc.
> All DSC related enteries have underscores in its naming convention.

There's value in that, though maybe my comment highlights I'm not fond
of the existing stuff. ;)

> May be i can consolidate other dsc debugfs enteries into
> one as a cleanup task later. But it will impact IGT aswell. And i'm not 
> sure if we can break compatibility but since IGT (intel as only vendor) 
> is the only consumer, may be we change at both places and clean it up.

We can do what we want with debugfs, as long as we change both the
driver and igt.

>
>> 
>>> +
>>> +out:
>>> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>>> +
>>> +	return ret;
>>> +}
>>> +
>>> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>>> +					     const char __user *ubuf,
>>> +					     size_t len, loff_t *offp)
>>> +{
>>> +	struct drm_connector *connector =
>>> +		((struct seq_file *)file->private_data)->private;
>> 
>> I know this is copy-pasted from elsewhere, but really it's nicer to
>> avoid the cast, and copy-paste from the places that get this right:
>> 
>> 	struct seq_file *m = file->private_data;
>>          struct drm_connector *connector = m->private;
>
> Done.
>
>> 
>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>> +	bool dsc_fractional_bpp_enable = false;
>>> +	int ret;
>>> +
>>> +	if (len == 0)
>>> +		return 0;
>> 
>> kstrtobool_from_user() has this covered.
>
> Done.
>
>> 
>>> +
>>> +	drm_dbg(&i915->drm,
>>> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>> 
>> That's useless.
>
> Done.
>
>> 
>>> +
>>> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>>> +	if (ret < 0)
>>> +		return ret;
>>> +
>>> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
>>> +		(dsc_fractional_bpp_enable) ? "true" : "false");
>> 
>> Is this useful?
>
> Yes, to know when fractional bpp is enabled.

I think it would be more useful to debug log this at the use site, not
when you're setting the debugfs knob.

BR,
Jani.




>
>> 
>>> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>>> +
>>> +	*offp += len;
>>> +
>>> +	return len;
>>> +}
>>> +
>>> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
>>> +					struct file *file)
>>> +{
>>> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
>>> +}
>>> +
>>> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
>>> +	.owner = THIS_MODULE,
>>> +	.open = i915_dsc_fractional_bpp_open,
>>> +	.read = seq_read,
>>> +	.llseek = seq_lseek,
>>> +	.release = single_release,
>>> +	.write = i915_dsc_fractional_bpp_write
>>> +};
>>> +
>>>   /*
>>>    * Returns the Current CRTC's bpc.
>>>    * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>>> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>>   
>>>   		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>>   				    connector, &i915_dsc_output_format_fops);
>>> +
>>> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
>>> +				    connector, &i915_dsc_fractional_bpp_fops);
>>>   	}
>>>   
>>>   	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 69bcabec4a29..27b31cb4c7b4 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1797,6 +1797,7 @@ struct intel_dp {
>>>   	/* Display stream compression testing */
>>>   	bool force_dsc_en;
>>>   	int force_dsc_output_format;
>>> +	bool force_dsc_fractional_bpp_en;
>>>   	int force_dsc_bpc;
>>>   
>>>   	bool hobl_failed;
>> 

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Sharma, Swati2]

On 21-Sep-23 5:44 PM, Jani Nikula wrote:
> On Thu, 21 Sep 2023, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
>> On 21-Sep-23 1:30 PM, Jani Nikula wrote:
>>> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>>>> From: Swati Sharma <swati2.sharma@intel.com>
>>>>
>>>> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
>>>> to depict sink's precision.
>>>> Also, new debugfs entry is created to enforce fractional bpp.
>>>> If Force_DSC_Fractional_BPP_en is set then while iterating over
>>>> output bpp with fractional step size we will continue if output_bpp is
>>>> computed as integer. With this approach, we will be able to validate
>>>> DSC with fractional bpp.
>>>>
>>>> v2:
>>>> Add drm_modeset_unlock to new line(Suraj)
>>>>
>>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>>> ---
>>>>    .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>>>    .../drm/i915/display/intel_display_types.h    |  1 +
>>>>    2 files changed, 84 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>> index f05b52381a83..776ab96def1f 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>>>    								      DP_DSC_YCbCr420_Native)),
>>>>    			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>>>    								      DP_DSC_YCbCr444)));
>>>> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
>>>> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>>>>    		seq_printf(m, "Force_DSC_Enable: %s\n",
>>>>    			   str_yes_no(intel_dp->force_dsc_en));
>>>>    		if (!intel_dp_is_edp(intel_dp))
>>>> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>>>>    	.write = i915_dsc_output_format_write
>>>>    };
>>>>    
>>>> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>>>> +{
>>>> +	struct drm_connector *connector = m->private;
>>>> +	struct drm_device *dev = connector->dev;
>>>> +	struct drm_crtc *crtc;
>>>> +	struct intel_dp *intel_dp;
>>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>>> +	int ret;
>>>> +
>>>> +	if (!encoder)
>>>> +		return -ENODEV;
>>>> +
>>>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>>>> +	if (ret)
>>>> +		return ret;
>>>> +
>>>> +	crtc = connector->state->crtc;
>>>> +	if (connector->status != connector_status_connected || !crtc) {
>>>> +		ret = -ENODEV;
>>>> +		goto out;
>>>> +	}
>>>> +
>>>> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
>>>> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
>>>> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>>>
>>> Why "Force_DSC_Fractional_BPP_Enable" in the output?
>>>
>>> Usually debugfs files, like sysfs files, for stuff like this should be
>>> attributes, one thing per file. Why print a long name for it, if the
>>> name of the debugfs file is the name of the attribute?
>>>
>>> And even if you print it for humans, why the underscores?
>>
>> Hi Jani,
>> Followed same strategy as we are doing for other dsc scenarios like
>> force_dsc.
>> Even naming convention followed same as other dsc stuff like
>> Force_DSC_Enable, etc.
>> All DSC related enteries have underscores in its naming convention.
> 
> There's value in that, though maybe my comment highlights I'm not fond
> of the existing stuff. ;)

Sure, I can work on cleanup part later.

> 
>> May be i can consolidate other dsc debugfs enteries into
>> one as a cleanup task later. But it will impact IGT aswell. And i'm not
>> sure if we can break compatibility but since IGT (intel as only vendor)
>> is the only consumer, may be we change at both places and clean it up.
> 
> We can do what we want with debugfs, as long as we change both the
> driver and igt.

Sure, will make corresponding changes in both IGT and KMD.

> 
>>
>>>
>>>> +
>>>> +out:
>>>> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>>>> +
>>>> +	return ret;
>>>> +}
>>>> +
>>>> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>>>> +					     const char __user *ubuf,
>>>> +					     size_t len, loff_t *offp)
>>>> +{
>>>> +	struct drm_connector *connector =
>>>> +		((struct seq_file *)file->private_data)->private;
>>>
>>> I know this is copy-pasted from elsewhere, but really it's nicer to
>>> avoid the cast, and copy-paste from the places that get this right:
>>>
>>> 	struct seq_file *m = file->private_data;
>>>           struct drm_connector *connector = m->private;
>>
>> Done.
>>
>>>
>>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>>> +	bool dsc_fractional_bpp_enable = false;
>>>> +	int ret;
>>>> +
>>>> +	if (len == 0)
>>>> +		return 0;
>>>
>>> kstrtobool_from_user() has this covered.
>>
>> Done.
>>
>>>
>>>> +
>>>> +	drm_dbg(&i915->drm,
>>>> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>>>
>>> That's useless.
>>
>> Done.
>>
>>>
>>>> +
>>>> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>>>> +	if (ret < 0)
>>>> +		return ret;
>>>> +
>>>> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
>>>> +		(dsc_fractional_bpp_enable) ? "true" : "false");
>>>
>>> Is this useful?
>>
>> Yes, to know when fractional bpp is enabled.
> 
> I think it would be more useful to debug log this at the use site, not
> when you're setting the debugfs knob.

We already have those in IGT. Like said, to maintain consitency with 
other dsc func() like fec_support_write(), this debug print is added 
here. I can drop and will drop from fec_support_write() too during cleanup.

> 
> BR,
> Jani.
> 
> 
> 
> 
>>
>>>
>>>> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>>>> +
>>>> +	*offp += len;
>>>> +
>>>> +	return len;
>>>> +}
>>>> +
>>>> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
>>>> +					struct file *file)
>>>> +{
>>>> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
>>>> +}
>>>> +
>>>> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
>>>> +	.owner = THIS_MODULE,
>>>> +	.open = i915_dsc_fractional_bpp_open,
>>>> +	.read = seq_read,
>>>> +	.llseek = seq_lseek,
>>>> +	.release = single_release,
>>>> +	.write = i915_dsc_fractional_bpp_write
>>>> +};
>>>> +
>>>>    /*
>>>>     * Returns the Current CRTC's bpc.
>>>>     * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>>>> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>>>    
>>>>    		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>>>    				    connector, &i915_dsc_output_format_fops);
>>>> +
>>>> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
>>>> +				    connector, &i915_dsc_fractional_bpp_fops);
>>>>    	}
>>>>    
>>>>    	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> index 69bcabec4a29..27b31cb4c7b4 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> @@ -1797,6 +1797,7 @@ struct intel_dp {
>>>>    	/* Display stream compression testing */
>>>>    	bool force_dsc_en;
>>>>    	int force_dsc_output_format;
>>>> +	bool force_dsc_fractional_bpp_en;
>>>>    	int force_dsc_bpc;
>>>>    
>>>>    	bool hobl_failed;
>>>
> 

With above KMD changes IGT is already rb'ed and validated
https://patchwork.freedesktop.org/series/117493/#rev12
I request if we can get ack on this. As cleanup task,
will make changes as requested.

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Jani Nikula]

On Thu, 21 Sep 2023, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
> On 21-Sep-23 5:44 PM, Jani Nikula wrote:
>> On Thu, 21 Sep 2023, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
>>> On 21-Sep-23 1:30 PM, Jani Nikula wrote:
>>>> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>>>>> From: Swati Sharma <swati2.sharma@intel.com>
>>>>>
>>>>> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
>>>>> to depict sink's precision.
>>>>> Also, new debugfs entry is created to enforce fractional bpp.
>>>>> If Force_DSC_Fractional_BPP_en is set then while iterating over
>>>>> output bpp with fractional step size we will continue if output_bpp is
>>>>> computed as integer. With this approach, we will be able to validate
>>>>> DSC with fractional bpp.
>>>>>
>>>>> v2:
>>>>> Add drm_modeset_unlock to new line(Suraj)
>>>>>
>>>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>>>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>>>> ---
>>>>>    .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>>>>    .../drm/i915/display/intel_display_types.h    |  1 +
>>>>>    2 files changed, 84 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>>> index f05b52381a83..776ab96def1f 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>>> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>>>>    								      DP_DSC_YCbCr420_Native)),
>>>>>    			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>>>>    								      DP_DSC_YCbCr444)));
>>>>> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
>>>>> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>>>>>    		seq_printf(m, "Force_DSC_Enable: %s\n",
>>>>>    			   str_yes_no(intel_dp->force_dsc_en));
>>>>>    		if (!intel_dp_is_edp(intel_dp))
>>>>> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>>>>>    	.write = i915_dsc_output_format_write
>>>>>    };
>>>>>    
>>>>> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>>>>> +{
>>>>> +	struct drm_connector *connector = m->private;
>>>>> +	struct drm_device *dev = connector->dev;
>>>>> +	struct drm_crtc *crtc;
>>>>> +	struct intel_dp *intel_dp;
>>>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>>>> +	int ret;
>>>>> +
>>>>> +	if (!encoder)
>>>>> +		return -ENODEV;
>>>>> +
>>>>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>>>>> +	if (ret)
>>>>> +		return ret;
>>>>> +
>>>>> +	crtc = connector->state->crtc;
>>>>> +	if (connector->status != connector_status_connected || !crtc) {
>>>>> +		ret = -ENODEV;
>>>>> +		goto out;
>>>>> +	}
>>>>> +
>>>>> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
>>>>> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
>>>>> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>>>>
>>>> Why "Force_DSC_Fractional_BPP_Enable" in the output?
>>>>
>>>> Usually debugfs files, like sysfs files, for stuff like this should be
>>>> attributes, one thing per file. Why print a long name for it, if the
>>>> name of the debugfs file is the name of the attribute?
>>>>
>>>> And even if you print it for humans, why the underscores?
>>>
>>> Hi Jani,
>>> Followed same strategy as we are doing for other dsc scenarios like
>>> force_dsc.
>>> Even naming convention followed same as other dsc stuff like
>>> Force_DSC_Enable, etc.
>>> All DSC related enteries have underscores in its naming convention.
>> 
>> There's value in that, though maybe my comment highlights I'm not fond
>> of the existing stuff. ;)
>
> Sure, I can work on cleanup part later.
>
>> 
>>> May be i can consolidate other dsc debugfs enteries into
>>> one as a cleanup task later. But it will impact IGT aswell. And i'm not
>>> sure if we can break compatibility but since IGT (intel as only vendor)
>>> is the only consumer, may be we change at both places and clean it up.
>> 
>> We can do what we want with debugfs, as long as we change both the
>> driver and igt.
>
> Sure, will make corresponding changes in both IGT and KMD.
>
>> 
>>>
>>>>
>>>>> +
>>>>> +out:
>>>>> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>>>>> +
>>>>> +	return ret;
>>>>> +}
>>>>> +
>>>>> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>>>>> +					     const char __user *ubuf,
>>>>> +					     size_t len, loff_t *offp)
>>>>> +{
>>>>> +	struct drm_connector *connector =
>>>>> +		((struct seq_file *)file->private_data)->private;
>>>>
>>>> I know this is copy-pasted from elsewhere, but really it's nicer to
>>>> avoid the cast, and copy-paste from the places that get this right:
>>>>
>>>> 	struct seq_file *m = file->private_data;
>>>>           struct drm_connector *connector = m->private;
>>>
>>> Done.
>>>
>>>>
>>>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>>>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>>>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>>>> +	bool dsc_fractional_bpp_enable = false;
>>>>> +	int ret;
>>>>> +
>>>>> +	if (len == 0)
>>>>> +		return 0;
>>>>
>>>> kstrtobool_from_user() has this covered.
>>>
>>> Done.
>>>
>>>>
>>>>> +
>>>>> +	drm_dbg(&i915->drm,
>>>>> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>>>>
>>>> That's useless.
>>>
>>> Done.
>>>
>>>>
>>>>> +
>>>>> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>>>>> +	if (ret < 0)
>>>>> +		return ret;
>>>>> +
>>>>> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
>>>>> +		(dsc_fractional_bpp_enable) ? "true" : "false");
>>>>
>>>> Is this useful?
>>>
>>> Yes, to know when fractional bpp is enabled.
>> 
>> I think it would be more useful to debug log this at the use site, not
>> when you're setting the debugfs knob.
>
> We already have those in IGT. Like said, to maintain consitency with 
> other dsc func() like fec_support_write(), this debug print is added 
> here. I can drop and will drop from fec_support_write() too during cleanup.
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> 
>> 
>>>
>>>>
>>>>> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>>>>> +
>>>>> +	*offp += len;
>>>>> +
>>>>> +	return len;
>>>>> +}
>>>>> +
>>>>> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
>>>>> +					struct file *file)
>>>>> +{
>>>>> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
>>>>> +}
>>>>> +
>>>>> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
>>>>> +	.owner = THIS_MODULE,
>>>>> +	.open = i915_dsc_fractional_bpp_open,
>>>>> +	.read = seq_read,
>>>>> +	.llseek = seq_lseek,
>>>>> +	.release = single_release,
>>>>> +	.write = i915_dsc_fractional_bpp_write
>>>>> +};
>>>>> +
>>>>>    /*
>>>>>     * Returns the Current CRTC's bpc.
>>>>>     * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>>>>> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>>>>    
>>>>>    		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>>>>    				    connector, &i915_dsc_output_format_fops);
>>>>> +
>>>>> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
>>>>> +				    connector, &i915_dsc_fractional_bpp_fops);
>>>>>    	}
>>>>>    
>>>>>    	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>> index 69bcabec4a29..27b31cb4c7b4 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>> @@ -1797,6 +1797,7 @@ struct intel_dp {
>>>>>    	/* Display stream compression testing */
>>>>>    	bool force_dsc_en;
>>>>>    	int force_dsc_output_format;
>>>>> +	bool force_dsc_fractional_bpp_en;
>>>>>    	int force_dsc_bpc;
>>>>>    
>>>>>    	bool hobl_failed;
>>>>
>> 
>
> With above KMD changes IGT is already rb'ed and validated
> https://patchwork.freedesktop.org/series/117493/#rev12
> I request if we can get ack on this. As cleanup task,
> will make changes as requested.

Okay then.

BR,
Jani.


-- 
Jani Nikula, Intel

[Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Mitul Golani]

This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchwork.freedesktop.org/series/105200/).

The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Ankit Nautiyal (5):
  drm/display/dp: Add helper function to get DSC bpp precision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
 drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
 drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
 drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
 .../drm/i915/display/intel_display_debugfs.c  | 84 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
 drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
 .../i915/display/intel_fractional_helper.h    | 36 ++++++++
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
 include/drm/display/drm_dp_helper.h           |  1 +
 16 files changed, 276 insertions(+), 74 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h

-- 
2.25.1

[Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp precision

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Add helper to get the DSC bits_per_pixel precision for the DP sink.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
 include/drm/display/drm_dp_helper.h     |  1 +
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 8a1b64c57dfd..5c23d5b8fc50 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
 }
 EXPORT_SYMBOL(drm_dp_read_desc);
 
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+	switch (bpp_increment_dpcd) {
+	case DP_DSC_BITS_PER_PIXEL_1_16:
+		return 16;
+	case DP_DSC_BITS_PER_PIXEL_1_8:
+		return 8;
+	case DP_DSC_BITS_PER_PIXEL_1_4:
+		return 4;
+	case DP_DSC_BITS_PER_PIXEL_1_2:
+		return 2;
+	case DP_DSC_BITS_PER_PIXEL_1_1:
+		return 1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
 /**
  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
  * supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 3369104e2d25..6968d4d87931 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 }
 
 /* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 				   bool is_edp);
 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-- 
2.25.1

[Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.

v2:
-Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
 with compressed bpp. (Suraj)
-Fix comment styling. (Suraj)

v3:
-Add separate file for 6.4 fixed point helper(Jani, Nikula)
-Add comment for magic values(Suraj)

v4:
Fix checkpatch warnings caused by renaming(Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +++---
 drivers/gpu/drm/i915/display/intel_audio.c    |  3 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |  6 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 ++--
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_types.h    |  3 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 33 ++++++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 26 ++++++++------
 .../i915/display/intel_fractional_helper.h    | 36 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  5 +--
 10 files changed, 93 insertions(+), 38 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c4585e445198..77b73bd61076 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -43,6 +43,7 @@
 #include "intel_de.h"
 #include "intel_dsi.h"
 #include "intel_dsi_vbt.h"
+#include "intel_fractional_helper.h"
 #include "intel_panel.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -330,7 +331,7 @@ static int afe_clk(struct intel_encoder *encoder,
 	int bpp;
 
 	if (crtc_state->dsc.compression_enable)
-		bpp = crtc_state->dsc.compressed_bpp;
+		bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 	else
 		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
@@ -860,7 +861,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	 * compressed and non-compressed bpp.
 	 */
 	if (crtc_state->dsc.compression_enable) {
-		mul = crtc_state->dsc.compressed_bpp;
+		mul = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 	}
 
@@ -884,7 +885,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 		int bpp, line_time_us, byte_clk_period_ns;
 
 		if (crtc_state->dsc.compression_enable)
-			bpp = crtc_state->dsc.compressed_bpp;
+			bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 		else
 			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
@@ -1451,8 +1452,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode =
 					&pipe_config->hw.adjusted_mode;
 
-	if (pipe_config->dsc.compressed_bpp) {
-		int div = pipe_config->dsc.compressed_bpp;
+	if (pipe_config->dsc.compressed_bpp_x16) {
+		int div = intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16);
 		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
 		adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 19605264a35c..4f1db1581316 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -35,6 +35,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_fractional_helper.h"
 #include "intel_lpe_audio.h"
 
 /**
@@ -528,7 +529,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
-	vdsc_bpp = crtc_state->dsc.compressed_bpp;
+	vdsc_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 	cdclk = i915->display.cdclk.hw.cdclk;
 	/* fec= 0.972261, using rounding multiplier of 1000000 */
 	fec_coeff = 972261;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4e8f1e91bb08..616492a1a7ef 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -33,6 +33,7 @@
 #include "i915_reg.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
+#include "intel_fractional_helper.h"
 #include "intel_gmbus.h"
 
 #define _INTEL_BIOS_PRIVATE
@@ -3392,8 +3393,9 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
 
 	crtc_state->pipe_bpp = bpc * 3;
 
-	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
-					     VBT_DSC_MAX_BPP(dsc->max_bpp));
+	crtc_state->dsc.compressed_bpp_x16 =
+		intel_fractional_bpp_to_x16(min(crtc_state->pipe_bpp,
+						VBT_DSC_MAX_BPP(dsc->max_bpp)));
 
 	/*
 	 * FIXME: This is ugly, and slice count should take DSC engine
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b55a3f75f392..31d008ddd014 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -34,6 +34,7 @@
 #include "intel_de.h"
 #include "intel_dp.h"
 #include "intel_display_types.h"
+#include "intel_fractional_helper.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pci_config.h"
 #include "intel_pcode.h"
@@ -2598,8 +2599,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
 		 */
 		int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
-		int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
-				   (2 * bigjoiner_interface_bits);
+		int min_cdclk_bj =
+			(intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16) *
+			 pixel_clock) / (2 * bigjoiner_interface_bits);
 
 		min_cdclk = max(min_cdclk, min_cdclk_bj);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index edbcf5968804..a9943505a80b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5415,7 +5415,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_I(dsc.compression_enable);
 	PIPE_CONF_CHECK_I(dsc.dsc_split);
-	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
+	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
 
 	PIPE_CONF_CHECK_BOOL(splitter.enable);
 	PIPE_CONF_CHECK_I(splitter.link_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2328f5e66cd8..c691ec2670c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1354,7 +1354,8 @@ struct intel_crtc_state {
 	struct {
 		bool compression_enable;
 		bool dsc_split;
-		u16 compressed_bpp;
+		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
+		u16 compressed_bpp_x16;
 		u8 slice_count;
 		struct drm_dsc_config config;
 	} dsc;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f16d9fa88fe1..2a7ff3318498 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -64,6 +64,7 @@
 #include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
+#include "intel_fractional_helper.h"
 #include "intel_fifo_underrun.h"
 #include "intel_hdcp.h"
 #include "intel_hdmi.h"
@@ -1863,7 +1864,8 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      valid_dsc_bpp[i],
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
+			pipe_config->dsc.compressed_bpp_x16 =
+				intel_fractional_bpp_to_x16(valid_dsc_bpp[i]);
 			return 0;
 		}
 	}
@@ -1901,7 +1903,8 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      compressed_bpp,
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp = compressed_bpp;
+			pipe_config->dsc.compressed_bpp_x16 =
+				intel_fractional_bpp_to_x16(compressed_bpp);
 			return 0;
 		}
 	}
@@ -2085,7 +2088,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	/* Compressed BPP should be less than the Input DSC bpp */
 	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
 
-	pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
+	pipe_config->dsc.compressed_bpp_x16 =
+		intel_fractional_bpp_to_x16(max(dsc_min_bpp, dsc_max_bpp));
 
 	pipe_config->pipe_bpp = pipe_bpp;
 
@@ -2171,18 +2175,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
 	if (ret < 0) {
 		drm_dbg_kms(&dev_priv->drm,
-			    "Cannot compute valid DSC parameters for Input Bpp = %d "
-			    "Compressed BPP = %d\n",
+			    "Cannot compute valid DSC parameters for Input Bpp = %d Compressed BPP = %d.%d\n",
 			    pipe_config->pipe_bpp,
-			    pipe_config->dsc.compressed_bpp);
+			    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
+			    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16));
 		return ret;
 	}
 
 	pipe_config->dsc.compression_enable = true;
-	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
-		    "Compressed Bpp = %d Slice Count = %d\n",
+	drm_dbg_kms(&dev_priv->drm,
+		    "DP DSC computed with Input Bpp = %d Compressed Bpp = %d.%d Slice Count = %d\n",
 		    pipe_config->pipe_bpp,
-		    pipe_config->dsc.compressed_bpp,
+		    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
+		    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16),
 		    pipe_config->dsc.slice_count);
 
 	return 0;
@@ -2261,15 +2266,17 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 
 	if (pipe_config->dsc.compression_enable) {
 		drm_dbg_kms(&i915->drm,
-			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
+			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n",
 			    pipe_config->lane_count, pipe_config->port_clock,
 			    pipe_config->pipe_bpp,
-			    pipe_config->dsc.compressed_bpp);
+			    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
+			    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16));
 
 		drm_dbg_kms(&i915->drm,
 			    "DP link rate required %i available %i\n",
 			    intel_dp_link_required(adjusted_mode->crtc_clock,
-						   pipe_config->dsc.compressed_bpp),
+						   intel_fractional_bpp_from_x16
+						   (pipe_config->dsc.compressed_bpp_x16)),
 			    intel_dp_max_data_rate(pipe_config->port_clock,
 						   pipe_config->lane_count));
 	} else {
@@ -2705,7 +2712,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
 
 	if (pipe_config->dsc.compression_enable)
-		link_bpp = pipe_config->dsc.compressed_bpp;
+		link_bpp = pipe_config->dsc.compressed_bpp_x16;
 	else
 		link_bpp = intel_dp_output_bpp(pipe_config->output_format,
 					       pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index ff3accebf0a8..64e1a8cba3d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -41,6 +41,7 @@
 #include "intel_dp_hdcp.h"
 #include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
+#include "intel_fractional_helper.h"
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
 #include "skl_scaler.h"
@@ -140,7 +141,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 		if (!dsc)
 			crtc_state->pipe_bpp = bpp;
 		else
-			crtc_state->dsc.compressed_bpp = bpp;
+			crtc_state->dsc.compressed_bpp_x16 = intel_fractional_bpp_to_x16(bpp);
 		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 	}
 
@@ -238,13 +239,14 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 	if (slots < 0)
 		return slots;
 
-	last_compressed_bpp = crtc_state->dsc.compressed_bpp;
+	last_compressed_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 
-	crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
-									last_compressed_bpp,
-									crtc_state->pipe_bpp);
+	crtc_state->dsc.compressed_bpp_x16 =
+		intel_fractional_bpp_to_x16(intel_dp_dsc_nearest_valid_bpp(i915,
+									   last_compressed_bpp,
+									   crtc_state->pipe_bpp));
 
-	if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
+	if (crtc_state->dsc.compressed_bpp_x16 != intel_fractional_bpp_to_x16(last_compressed_bpp))
 		need_timeslot_recalc = true;
 
 	/*
@@ -252,15 +254,17 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 	 * the actual compressed bpp we use.
 	 */
 	if (need_timeslot_recalc) {
-		slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
-							     crtc_state->dsc.compressed_bpp,
-							     crtc_state->dsc.compressed_bpp,
-							     limits, conn_state, 2 * 3, true);
+		slots =
+		intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
+						     intel_fractional_bpp_from_x16
+						     (crtc_state->dsc.compressed_bpp_x16),
+		intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16),
+		limits, conn_state, 2 * 3, true);
 		if (slots < 0)
 			return slots;
 	}
 
-	intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
+	intel_link_compute_m_n(intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16),
 			       crtc_state->lane_count,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_fractional_helper.h b/drivers/gpu/drm/i915/display/intel_fractional_helper.h
new file mode 100644
index 000000000000..0212a9041c8f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_fractional_helper.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef __INTEL_FRACTIONAL_HELPERS_H__
+#define __INTEL_FRACTIONAL_HELPERS_H__
+
+ /*
+  * Convert a U6.4 fixed-point bits-per-pixel (bpp) value to an integer bpp value.
+  */
+static inline int intel_fractional_bpp_from_x16(int bpp_x16)
+{
+	return bpp_x16 >> 4;
+}
+
+/*
+ * Extract the fractional part of a U6.4 fixed-point bpp value based on the
+ * last 4 bits representing fractional bits, obtained by multiplying by 10000
+ * and then dividing by 16, as the bpp value is initially left-shifted by 4
+ * to allocate 4 bits for the fractional part.
+ */
+static inline int intel_fractional_bpp_decimal(int bpp_x16)
+{
+	return (bpp_x16 & 0xf) * 625;
+}
+
+/*
+ * Convert bits-per-pixel (bpp) to a U6.4 fixed-point representation.
+ */
+static inline int intel_fractional_bpp_to_x16(int bpp)
+{
+	return bpp << 4;
+}
+
+#endif /*  __INTEL_FRACTIONAL_HELPERS_H__ */
+
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 6757dbae9ee5..142c886f4776 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -15,6 +15,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsi.h"
+#include "intel_fractional_helper.h"
 #include "intel_qp_tables.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -248,7 +249,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
-	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
+	u16 compressed_bpp = intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16);
 	int err;
 	int ret;
 
@@ -874,7 +875,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	if (vdsc_cfg->native_420)
 		vdsc_cfg->bits_per_pixel >>= 1;
 
-	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+	crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
 
 	/* PPS 2 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
-- 
2.25.1

[Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.

v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
 drivers/gpu/drm/i915/display/intel_display.h | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 5 +++--
 drivers/gpu/drm/i915/display/intel_dp_mst.c  | 6 ++++--
 drivers/gpu/drm/i915/display/intel_fdi.c     | 2 +-
 5 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a9943505a80b..283e8dfa6dec 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2396,10 +2396,14 @@ void
 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
 		       int pixel_clock, int link_clock,
 		       struct intel_link_m_n *m_n,
-		       bool fec_enable)
+		       bool fec_enable,
+		       bool is_dsc_fractional_bpp)
 {
 	u32 data_clock = bits_per_pixel * pixel_clock;
 
+	if (is_dsc_fractional_bpp)
+		data_clock = DIV_ROUND_UP(data_clock, 16);
+
 	if (fec_enable)
 		data_clock = intel_dp_mode_to_fec_clock(data_clock);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 49ac8473b988..a4c4ca3cad65 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
 void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
-			    bool fec_enable);
+			    bool fec_enable, bool is_dsc_fractional_bpp);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
 enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2a7ff3318498..fc72590f93c6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2562,7 +2562,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 
 	intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
 			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
-			       pipe_config->fec_enable);
+			       pipe_config->fec_enable, false);
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
@@ -2744,7 +2744,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n,
-			       pipe_config->fec_enable);
+			       pipe_config->fec_enable,
+			       pipe_config->dsc.compression_enable);
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 64e1a8cba3d8..2d8a2a45f8fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -172,7 +172,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
 			       &crtc_state->dp_m_n,
-			       crtc_state->fec_enable);
+			       crtc_state->fec_enable,
+			       false);
 	crtc_state->dp_m_n.tu = slots;
 
 	return 0;
@@ -269,7 +270,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
 			       &crtc_state->dp_m_n,
-			       crtc_state->fec_enable);
+			       crtc_state->fec_enable,
+			       crtc_state->dsc.compression_enable);
 	crtc_state->dp_m_n.tu = slots;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 4d7d524c6801..3103ea881059 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
 	pipe_config->fdi_lanes = lane;
 
 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
-			       link_bw, &pipe_config->fdi_m_n, false);
+			       link_bw, &pipe_config->fdi_m_n, false, false);
 
 	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
 	if (ret == -EDEADLK)
-- 
2.25.1

[Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.

v2:
-Fixed tu_data calculation while dealing with U6.4 format. (Stan)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 4f1db1581316..3b08be54ce4f 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -522,25 +522,25 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	unsigned int link_clks_available, link_clks_required;
 	unsigned int tu_data, tu_line, link_clks_active;
 	unsigned int h_active, h_total, hblank_delta, pixel_clk;
-	unsigned int fec_coeff, cdclk, vdsc_bpp;
+	unsigned int fec_coeff, cdclk, vdsc_bppx16;
 	unsigned int link_clk, lanes;
 	unsigned int hblank_rise;
 
 	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
-	vdsc_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
+	vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
 	cdclk = i915->display.cdclk.hw.cdclk;
 	/* fec= 0.972261, using rounding multiplier of 1000000 */
 	fec_coeff = 972261;
 	link_clk = crtc_state->port_clock;
 	lanes = crtc_state->lane_count;
 
-	drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
-		    "lanes = %u vdsc_bpp = %u cdclk = %u\n",
-		    h_active, link_clk, lanes, vdsc_bpp, cdclk);
+	drm_dbg_kms(&i915->drm,
+		    "h_active = %u link_clk = %u : lanes = %u vdsc_bppx16 = %u cdclk = %u\n",
+		    h_active, link_clk, lanes, vdsc_bppx16, cdclk);
 
-	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
+	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
 		return 0;
 
 	link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
@@ -552,8 +552,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 		hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
 						  mul_u32_u32(link_clk, cdclk));
 
-	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
-			    mul_u32_u32(link_clk * lanes, fec_coeff));
+	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
+			    mul_u32_u32(link_clk * lanes * 16, fec_coeff));
 	tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
 			    mul_u32_u32(64 * pixel_clk, 1000000));
 	link_clks_active  = (tu_line - 1) * 64 + tu_data;
-- 
2.25.1

[Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp

[Mitul Golani]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Consider the fractional bpp while reading the qp values.

v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 ---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 25 +++++++++++++++----
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 543cdc46aa1d..600c815e37e4 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -34,9 +34,6 @@
  * These qp tables are as per the C model
  * and it has the rows pointing to bpps which increment
  * in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
  */
 static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 142c886f4776..e9f90c2c2ec4 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -78,8 +78,8 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
 static void
 calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 {
+	int bpp = intel_fractional_bpp_from_x16(vdsc_cfg->bits_per_pixel);
 	int bpc = vdsc_cfg->bits_per_component;
-	int bpp = vdsc_cfg->bits_per_pixel >> 4;
 	int qp_bpc_modifier = (bpc - 8) * 2;
 	int uncompressed_bpg_rate;
 	int first_line_bpg_offset;
@@ -149,7 +149,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 		static const s8 ofs_und8[] = {
 			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
 		};
-
+		/*
+		 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
+		 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
+		 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
+		 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
+		 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
+		 */
 		bpp_i  = bpp - 8;
 		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 			u8 range_bpg_offset;
@@ -179,6 +185,9 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 				range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
 		}
 	} else {
+		/* fractional bpp part * 10000 (for precision up to 4 decimal places) */
+		int fractional_bits = intel_fractional_bpp_decimal(vdsc_cfg->bits_per_pixel);
+
 		static const s8 ofs_und6[] = {
 			0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
 		};
@@ -192,7 +201,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
 		};
 
-		bpp_i  = (2 * (bpp - 6));
+		/*
+		 * QP table rows have values in increment of 0.5.
+		 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
+		 * and so on.
+		 * 0.5 fractional part with 4 decimal precision becomes 5000
+		 */
+		bpp_i  = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
+
 		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 			u8 range_bpg_offset;
 
@@ -280,8 +296,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
-	/* Gen 11 only supports integral values of bpp */
-	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
 
 	/*
 	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
-- 
2.25.1

[Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.

v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++----------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fc72590f93c6..6f4a25d024e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1716,15 +1716,15 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
 	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
 }
 
-static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
 					    u32 lane_count, u32 mode_clock,
 					    enum intel_output_format output_format,
 					    int timeslots)
 {
 	u32 available_bw, required_bw;
 
-	available_bw = (link_clock * lane_count * timeslots)  / 8;
-	required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+	available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
+	required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
 
 	return available_bw > required_bw;
 }
@@ -1732,7 +1732,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
 static int dsc_compute_link_config(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *pipe_config,
 				   struct link_config_limits *limits,
-				   u16 compressed_bpp,
+				   u16 compressed_bppx16,
 				   int timeslots)
 {
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
@@ -1747,8 +1747,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 		for (lane_count = limits->min_lane_count;
 		     lane_count <= limits->max_lane_count;
 		     lane_count <<= 1) {
-			if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
-							     adjusted_mode->clock,
+			if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
+							     lane_count, adjusted_mode->clock,
 							     pipe_config->output_format,
 							     timeslots))
 				continue;
@@ -1861,7 +1861,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
-					      valid_dsc_bpp[i],
+					      valid_dsc_bpp[i] << 4,
 					      timeslots);
 		if (ret == 0) {
 			pipe_config->dsc.compressed_bpp_x16 =
@@ -1888,23 +1888,31 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 			      int pipe_bpp,
 			      int timeslots)
 {
-	u16 compressed_bpp;
+	u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	u16 compressed_bppx16;
+	u8 bppx16_step;
 	int ret;
 
+	if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
+		bppx16_step = 16;
+	else
+		bppx16_step = 16 / bppx16_incr;
+
 	/* Compressed BPP should be less than the Input DSC bpp */
-	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+	dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
+	dsc_min_bpp = dsc_min_bpp << 4;
 
-	for (compressed_bpp = dsc_max_bpp;
-	     compressed_bpp >= dsc_min_bpp;
-	     compressed_bpp--) {
+	for (compressed_bppx16 = dsc_max_bpp;
+	     compressed_bppx16 >= dsc_min_bpp;
+	     compressed_bppx16 -= bppx16_step) {
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
-					      compressed_bpp,
+					      compressed_bppx16,
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp_x16 =
-				intel_fractional_bpp_to_x16(compressed_bpp);
+			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
 			return 0;
 		}
 	}
-- 
2.25.1

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Mitul Golani]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.

v2:
Add drm_modeset_unlock to new line(Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 84 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f05b52381a83..8de41c820eed 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 								      DP_DSC_YCbCr420_Native)),
 			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
 								      DP_DSC_YCbCr444)));
+		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1436,6 +1438,85 @@ static const struct file_operations i915_dsc_output_format_fops = {
 	.write = i915_dsc_output_format_write
 };
 
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(intel_connector);
+	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_fractional_bpp_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+		(dsc_fractional_bpp_enable) ? "true" : "false");
+	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+					struct file *file)
+{
+	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_fractional_bpp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_fractional_bpp_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1513,6 +1594,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_output_format", 0644, root,
 				    connector, &i915_dsc_output_format_fops);
+
+		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c691ec2670c3..e0fe283900a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1804,6 +1804,7 @@ struct intel_dp {
 	/* Display stream compression testing */
 	bool force_dsc_en;
 	int force_dsc_output_format;
+	bool force_dsc_fractional_bpp_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.25.1

[Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs

[Mitul Golani]

From: Swati Sharma <swati2.sharma@intel.com>

If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.

v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6f4a25d024e9..169d84130e4a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1906,6 +1906,9 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 	for (compressed_bppx16 = dsc_max_bpp;
 	     compressed_bppx16 >= dsc_min_bpp;
 	     compressed_bppx16 -= bppx16_step) {
+		if (intel_dp->force_dsc_fractional_bpp_en &&
+		    !intel_fractional_bpp_decimal(compressed_bppx16))
+			continue;
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
@@ -1913,6 +1916,10 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      timeslots);
 		if (ret == 0) {
 			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
+			if (intel_dp->force_dsc_fractional_bpp_en &&
+			    intel_fractional_bpp_decimal(compressed_bppx16))
+				drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
+
 			return 0;
 		}
 	}
-- 
2.25.1

Re: [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Sui Jingfeng]

Hi,


For coding style and wording part, this version looks fine for me after a brief skim.
Thanks for the patch. :-)


On 2023/9/26 16:23, Mitul Golani wrote:
> This patch series adds support for DSC fractional compressed bpp
> for MTL+. The series starts with some fixes, followed by patches that
> lay groundwork to iterate over valid compressed bpps to select the
> 'best' compressed bpp with optimal link configuration (taken from
> upstream series: https://patchwork.freedesktop.org/series/105200/).
>
> The later patches, add changes to accommodate compressed bpp with
> fractional part, including changes to QP calculations.
> To get the 'best' compressed bpp, we iterate over the valid compressed
> bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
> sink support.
>
> The last 2 patches add support to depict DSC sink's fractional support,
> and debugfs to enforce use of fractional bpp, while choosing an
> appropriate compressed bpp.
>
> Ankit Nautiyal (5):
>    drm/display/dp: Add helper function to get DSC bpp precision
>    drm/i915/display: Store compressed bpp in U6.4 format
>    drm/i915/display: Consider fractional vdsc bpp while computing m_n
>      values
>    drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
>    drm/i915/dp: Iterate over output bpp with fractional step size
>
> Swati Sharma (2):
>    drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
>    drm/i915/dsc: Allow DSC only with fractional bpp when forced from
>      debugfs
>
> Vandita Kulkarni (1):
>    drm/i915/dsc/mtl: Add support for fractional bpp
>
>   drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
>   drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
>   drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
>   drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
>   drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
>   drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
>   drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
>   .../drm/i915/display/intel_display_debugfs.c  | 84 +++++++++++++++++++
>   .../drm/i915/display/intel_display_types.h    |  4 +-
>   drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
>   drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
>   drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
>   .../i915/display/intel_fractional_helper.h    | 36 ++++++++
>   .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
>   include/drm/display/drm_dp_helper.h           |  1 +
>   16 files changed, 276 insertions(+), 74 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h
>

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev8)

[Patchwork]

== Series Details ==

Series: Add DSC fractional bpp support (rev8)
URL   : https://patchwork.freedesktop.org/series/111391/
State : warning

== Summary ==

Error: dim checkpatch failed
42171b637e55 drm/display/dp: Add helper function to get DSC bpp precision
0c66f9a2a7cf drm/i915/display: Store compressed bpp in U6.4 format
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:339: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#339: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 311 lines checked
93e90ae02a2e drm/i915/display: Consider fractional vdsc bpp while computing m_n values
c4174e47319b drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
53fe5efba35c drm/i915/dsc/mtl: Add support for fractional bpp
8c52fa521283 drm/i915/dp: Iterate over output bpp with fractional step size
b6f0df030c74 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
d48076975b8b drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC fractional bpp support (rev8)

[Patchwork]

== Series Details ==

Series: Add DSC fractional bpp support (rev8)
URL   : https://patchwork.freedesktop.org/series/111391/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add DSC fractional bpp support (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6945 bytes --]

== Series Details ==

Series: Add DSC fractional bpp support (rev8)
URL   : https://patchwork.freedesktop.org/series/111391/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13681 -> Patchwork_111391v8
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_111391v8 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111391v8, please notify your bug team (lgci.bug.filing@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/index.html

Participating hosts (41 -> 38)
------------------------------

  Additional (1): bat-dg2-14 
  Missing    (4): fi-kbl-soraka bat-dg2-9 fi-snb-2520m fi-bsw-n3050 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_111391v8:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@hangcheck:
    - fi-skl-guc:         [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/fi-skl-guc/igt@i915_selftest@live@hangcheck.html

  
Known issues
------------

  Here are the changes found in Patchwork_111391v8 that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - fi-hsw-4770:        [FAIL][3] ([i915#8293]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/fi-hsw-4770/boot.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/fi-hsw-4770/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - fi-hsw-4770:        NOTRUN -> [SKIP][5] ([fdo#109271]) +13 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-bsw-nick:        [PASS][6] -> [FAIL][7] ([i915#9276])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/fi-bsw-nick/igt@kms_frontbuffer_tracking@basic.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/fi-bsw-nick/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         NOTRUN -> [SKIP][8] ([i915#1845]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
    - fi-hsw-4770:        NOTRUN -> [DMESG-WARN][9] ([i915#8841]) +6 other tests dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-hsw-4770:        NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1072]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  
#### Possible fixes ####

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-guc:         [FAIL][11] ([IGT#3]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html

  
#### Warnings ####

  * igt@i915_selftest@live@requests:
    - bat-mtlp-8:         [ABORT][13] ([i915#9262]) -> [ABORT][14] ([i915#9414])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13681/bat-mtlp-8/igt@i915_selftest@live@requests.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/bat-mtlp-8/igt@i915_selftest@live@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
  [i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8981]: https://gitlab.freedesktop.org/drm/intel/issues/8981
  [i915#9262]: https://gitlab.freedesktop.org/drm/intel/issues/9262
  [i915#9276]: https://gitlab.freedesktop.org/drm/intel/issues/9276
  [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414


Build changes
-------------

  * Linux: CI_DRM_13681 -> Patchwork_111391v8

  CI-20190529: 20190529
  CI_DRM_13681: b57407d0de043fc22b000a941a404ab103849e06 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7503: 7503
  Patchwork_111391v8: b57407d0de043fc22b000a941a404ab103849e06 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

f2d98106ae48 drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
c8d180960c6a drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
41749bdb7cd5 drm/i915/dp: Iterate over output bpp with fractional step size
365f307f8e1f drm/i915/dsc/mtl: Add support for fractional bpp
52e072dc492a drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
1bf5d7a4480a drm/i915/display: Consider fractional vdsc bpp while computing m_n values
3f92fca8fd93 drm/i915/display: Store compressed bpp in U6.4 format
51914550de0e drm/display/dp: Add helper function to get DSC bpp precision

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v8/index.html

[-- Attachment #2: Type: text/html, Size: 6803 bytes --]

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Mitul Golani]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.

v2:
Add drm_modeset_unlock to new line(Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
---
 .../drm/i915/display/intel_display_debugfs.c  | 84 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f05b52381a83..8de41c820eed 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 								      DP_DSC_YCbCr420_Native)),
 			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
 								      DP_DSC_YCbCr444)));
+		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1436,6 +1438,85 @@ static const struct file_operations i915_dsc_output_format_fops = {
 	.write = i915_dsc_output_format_write
 };
 
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(intel_connector);
+	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_fractional_bpp_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+		(dsc_fractional_bpp_enable) ? "true" : "false");
+	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+					struct file *file)
+{
+	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_fractional_bpp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_fractional_bpp_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1513,6 +1594,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_output_format", 0644, root,
 				    connector, &i915_dsc_output_format_fops);
+
+		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 19da97584afa..d849620ffdc2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1805,6 +1805,7 @@ struct intel_dp {
 	/* Display stream compression testing */
 	bool force_dsc_en;
 	int force_dsc_output_format;
+	bool force_dsc_fractional_bpp_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.25.1