From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 08/12] drm/i915: Simplify snps/c10x DPLL state checker calling convetion
Date: Wed, 4 Oct 2023 18:56:03 +0300 [thread overview]
Message-ID: <20231004155607.7719-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20231004155607.7719-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Passing in the atomic state + crtc state is a bit weird. The latter
can be just the crtc (which is the normal calling convention used
in a lot of other places).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 3 ++-
drivers/gpu/drm/i915/display/intel_modeset_verify.c | 4 ++--
drivers/gpu/drm/i915/display/intel_snps_phy.c | 5 +++--
drivers/gpu/drm/i915/display/intel_snps_phy.h | 3 ++-
5 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1aba265afe41..0ef28f4be36e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3005,12 +3005,13 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
}
void intel_c10pll_state_verify(struct intel_atomic_state *state,
- const struct intel_crtc_state *new_crtc_state)
+ struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct intel_c10pll_state mpllb_hw_state = { 0 };
const struct intel_c10pll_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10;
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct intel_encoder *encoder;
enum phy phy;
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 43f2fdb662c5..0e0a38dac8cd 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -16,6 +16,7 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
+struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdmi;
@@ -34,7 +35,7 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10pll_state *pll_state);
void intel_c10pll_state_verify(struct intel_atomic_state *state,
- const struct intel_crtc_state *new_crtc_state);
+ struct intel_crtc *crtc);
void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state);
void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index bbee79aad0cd..b876ec34b1a3 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -237,8 +237,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
verify_connector_state(state, crtc);
verify_crtc_state(state, crtc);
intel_shared_dpll_state_verify(state, crtc);
- intel_mpllb_state_verify(state, new_crtc_state);
- intel_c10pll_state_verify(state, new_crtc_state);
+ intel_mpllb_state_verify(state, crtc);
+ intel_c10pll_state_verify(state, crtc);
}
void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index bdceb6bd474c..c0285365efae 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -1993,12 +1993,13 @@ int intel_snps_phy_check_hdmi_link_rate(int clock)
}
void intel_mpllb_state_verify(struct intel_atomic_state *state,
- const struct intel_crtc_state *new_crtc_state)
+ struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct intel_mpllb_state mpllb_hw_state = { 0 };
const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct intel_encoder *encoder;
if (!IS_DG2(i915))
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index 9d1d0c6a9cfe..515abf7c5902 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -10,6 +10,7 @@
struct drm_i915_private;
struct intel_atomic_state;
+struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
struct intel_mpllb_state;
@@ -33,6 +34,6 @@ int intel_snps_phy_check_hdmi_link_rate(int clock);
void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mpllb_state_verify(struct intel_atomic_state *state,
- const struct intel_crtc_state *new_crtc_state);
+ struct intel_crtc *crtc);
#endif /* __INTEL_SNPS_PHY_H__ */
--
2.41.0
next prev parent reply other threads:[~2023-10-04 15:56 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-04 15:55 [Intel-gfx] [PATCH 00/12] drm/i915: Display state checker cleanup Ville Syrjala
2023-10-04 15:55 ` [Intel-gfx] [PATCH 01/12] drm/i915/psr: Unify PSR pre/post plane update hooks Ville Syrjala
2023-10-04 15:55 ` [Intel-gfx] [PATCH 02/12] drm/i915: Stop clobbering old crtc state during state check Ville Syrjala
2023-10-04 15:55 ` [Intel-gfx] [PATCH 03/12] drm/i915: Constify the crtc states in the DPLL checker Ville Syrjala
2023-10-04 15:55 ` [Intel-gfx] [PATCH 04/12] drm/i915: Simplify DPLL state checker calling convention Ville Syrjala
2023-10-04 15:56 ` [Intel-gfx] [PATCH 05/12] drm/i915: Constify watermark state checker Ville Syrjala
2023-10-04 15:56 ` [Intel-gfx] [PATCH 06/12] drm/i915: Simplify watermark state checker calling convention Ville Syrjala
2023-10-04 16:57 ` Jani Nikula
2023-10-04 17:18 ` Ville Syrjälä
2023-10-05 12:27 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-10-05 13:08 ` Jani Nikula
2023-10-04 15:56 ` [Intel-gfx] [PATCH 07/12] drm/i915: Constify the snps/c10x PLL state checkers Ville Syrjala
2023-10-04 15:56 ` Ville Syrjala [this message]
2023-10-04 15:56 ` [Intel-gfx] [PATCH 09/12] drm/i915: Constify remainder of the state checker Ville Syrjala
2023-10-04 15:56 ` [Intel-gfx] [PATCH 10/12] drm/i915: Simplify the state checker calling convetions Ville Syrjala
2023-10-04 15:56 ` [Intel-gfx] [PATCH 11/12] drm/i915: s/pipe_config/crtc_state/ in the state checker Ville Syrjala
2023-10-04 15:56 ` [Intel-gfx] [PATCH 12/12] drm/i915: s/dev_priv/i915/ " Ville Syrjala
2023-10-04 16:58 ` [Intel-gfx] [PATCH 00/12] drm/i915: Display state checker cleanup Jani Nikula
2023-10-04 22:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-10-04 22:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-04 23:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-05 3:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Display state checker cleanup (rev2) Patchwork
2023-10-05 3:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-05 3:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-05 23:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Display state checker cleanup (rev3) Patchwork
2023-10-05 23:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-05 23:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-06 13:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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