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From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, ankit.k.nautiyal@intel.com,
	jani.nikula@intel.com
Subject: [PATCH v12 9/9] drm/i915/display: Compute Adaptive sync SDP params
Date: Wed,  5 Jun 2024 17:58:02 +0530	[thread overview]
Message-ID: <20240605122802.488124-10-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20240605122802.488124-1-mitulkumar.ajitkumar.golani@intel.com>

Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.

--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).

--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_dp_compute_as_sdp.

--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ac81b172b1ec..b5915c23302f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2637,11 +2637,19 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
-	as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
-	as_sdp->vtotal = adjusted_mode->vtotal;
-	as_sdp->target_rr = 0;
 	as_sdp->duration_incr_ms = 0;
 	as_sdp->duration_incr_ms = 0;
+
+	if (crtc_state->cmrr.enable) {
+		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+		as_sdp->vtotal = adjusted_mode->vtotal;
+		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+		as_sdp->target_rr_divider = true;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+		as_sdp->vtotal = adjusted_mode->vtotal;
+		as_sdp->target_rr = 0;
+	}
 }
 
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
-- 
2.25.1


  parent reply	other threads:[~2024-06-05 12:38 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-05 12:27 [PATCH v12 0/9] Implement CMRR Support Mitul Golani
2024-06-05 12:27 ` [PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for consistency Mitul Golani
2024-06-05 12:49   ` Golani, Mitulkumar Ajitkumar
2024-06-05 12:27 ` [PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest Mitul Golani
2024-06-05 12:50   ` Golani, Mitulkumar Ajitkumar
2024-06-05 12:27 ` [PATCH v12 3/9] gpu/drm/i915: Update indentation for VRR registers and bits Mitul Golani
2024-06-05 12:27 ` [PATCH v12 4/9] drm/i915: Separate VRR related register definitions Mitul Golani
2024-06-05 12:27 ` [PATCH v12 5/9] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-06-05 12:27 ` [PATCH v12 6/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Mitul Golani
2024-06-05 12:28 ` [PATCH v12 7/9] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-06-05 12:28 ` [PATCH v12 8/9] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-06-05 12:28 ` Mitul Golani [this message]
2024-06-05 14:38 ` ✗ Fi.CI.BUILD: failure for Implement CMRR Support (rev12) Patchwork

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